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Copyright 2014 Joey Hess <joeyh@debian.org> and contributors.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
   notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
   notice, this list of conditions and the following disclaimer in the
   documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY AUTHORS AND CONTRIBUTORS ``AS IS'' AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
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-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h183
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PortNames.h48
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device.h70
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h109
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/rtc_api.c203
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/analogin_api.c176
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/analogout_api.c161
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/gpio_api.c77
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/gpio_irq_api.c267
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/gpio_object.h75
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/i2c_api.c409
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/mbed_overrides.c35
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/pinmap.c143
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/port_api.c103
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/pwmout_api.c193
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/serial_api.c406
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/sleep.c61
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c269
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/us_ticker.c113
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/PeripheralPins.h66
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h82
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c188
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h183
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h48
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h70
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h110
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h84
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralPins.c192
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h183
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PortNames.h48
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h70
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h110
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogin_api.c193
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c146
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_api.c77
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_irq_api.c332
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h79
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/i2c_api.c480
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/mbed_overrides.c35
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/pinmap.c143
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/port_api.c103
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/pwmout_api.c201
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c209
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c396
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c98
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c298
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/us_ticker.c69
2777 files changed, 0 insertions, 1417318 deletions
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h
deleted file mode 100644
index 09437a256..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_H
-#define MBED_ANALOGIN_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGIN
-
-#include "analogin_api.h"
-
-namespace mbed {
-
-/** An analog input, used for reading the voltage on a pin
- *
- * Example:
- * @code
- * // Print messages when the AnalogIn is greater than 50%
- *
- * #include "mbed.h"
- *
- * AnalogIn temperature(p20);
- *
- * int main() {
- * while(1) {
- * if(temperature > 0.5) {
- * printf("Too hot! (%f)", temperature.read());
- * }
- * }
- * }
- * @endcode
- */
-class AnalogIn {
-
-public:
-
- /** Create an AnalogIn, connected to the specified pin
- *
- * @param pin AnalogIn pin to connect to
- * @param name (optional) A string to identify the object
- */
- AnalogIn(PinName pin) {
- analogin_init(&_adc, pin);
- }
-
- /** Read the input voltage, represented as a float in the range [0.0, 1.0]
- *
- * @returns A floating-point value representing the current input voltage, measured as a percentage
- */
- float read() {
- return analogin_read(&_adc);
- }
-
- /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
- *
- * @returns
- * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
- */
- unsigned short read_u16() {
- return analogin_read_u16(&_adc);
- }
-
-#ifdef MBED_OPERATORS
- /** An operator shorthand for read()
- *
- * The float() operator can be used as a shorthand for read() to simplify common code sequences
- *
- * Example:
- * @code
- * float x = volume.read();
- * float x = volume;
- *
- * if(volume.read() > 0.25) { ... }
- * if(volume > 0.25) { ... }
- * @endcode
- */
- operator float() {
- return read();
- }
-#endif
-
-protected:
- analogin_t _adc;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h
deleted file mode 100644
index 0b879a72b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_H
-#define MBED_ANALOGOUT_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGOUT
-
-#include "analogout_api.h"
-
-namespace mbed {
-
-/** An analog output, used for setting the voltage on a pin
- *
- * Example:
- * @code
- * // Make a sawtooth output
- *
- * #include "mbed.h"
- *
- * AnalogOut tri(p18);
- * int main() {
- * while(1) {
- * tri = tri + 0.01;
- * wait_us(1);
- * if(tri == 1) {
- * tri = 0;
- * }
- * }
- * }
- * @endcode
- */
-class AnalogOut {
-
-public:
-
- /** Create an AnalogOut connected to the specified pin
- *
- * @param AnalogOut pin to connect to (18)
- */
- AnalogOut(PinName pin) {
- analogout_init(&_dac, pin);
- }
-
- /** Set the output voltage, specified as a percentage (float)
- *
- * @param value A floating-point value representing the output voltage,
- * specified as a percentage. The value should lie between
- * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
- * Values outside this range will be saturated to 0.0f or 1.0f.
- */
- void write(float value) {
- analogout_write(&_dac, value);
- }
-
- /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
- *
- * @param value 16-bit unsigned short representing the output voltage,
- * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
- */
- void write_u16(unsigned short value) {
- analogout_write_u16(&_dac, value);
- }
-
- /** Return the current output voltage setting, measured as a percentage (float)
- *
- * @returns
- * A floating-point value representing the current voltage being output on the pin,
- * measured as a percentage. The returned value will lie between
- * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
- *
- * @note
- * This value may not match exactly the value set by a previous write().
- */
- float read() {
- return analogout_read(&_dac);
- }
-
-#ifdef MBED_OPERATORS
- /** An operator shorthand for write()
- */
- AnalogOut& operator= (float percent) {
- write(percent);
- return *this;
- }
-
- AnalogOut& operator= (AnalogOut& rhs) {
- write(rhs.read());
- return *this;
- }
-
- /** An operator shorthand for read()
- */
- operator float() {
- return read();
- }
-#endif
-
-protected:
- dac_t _dac;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h
deleted file mode 100644
index d1c9a9cd4..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSIN_H
-#define MBED_BUSIN_H
-
-#include "platform.h"
-#include "DigitalIn.h"
-
-namespace mbed {
-
-/** A digital input bus, used for reading the state of a collection of pins
- */
-class BusIn {
-
-public:
- /* Group: Configuration Methods */
-
- /** Create an BusIn, connected to the specified pins
- *
- * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
- *
- * @note
- * It is only required to specify as many pin variables as is required
- * for the bus; the rest will default to NC (not connected)
- */
- BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
- PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
- PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
- PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
- BusIn(PinName pins[16]);
-
- virtual ~BusIn();
-
- /** Read the value of the input bus
- *
- * @returns
- * An integer with each bit corresponding to the value read from the associated DigitalIn pin
- */
- int read();
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone
- */
- void mode(PinMode pull);
-
- /** Binary mask of bus pins connected to actual pins (not NC pins)
- * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
- *
- * @returns
- * Binary mask of connected pins
- */
- int mask() {
- return _nc_mask;
- }
-
-#ifdef MBED_OPERATORS
- /** A shorthand for read()
- */
- operator int();
-
- /** Access to particular bit in random-iterator fashion
- */
- DigitalIn & operator[] (int index);
-#endif
-
-protected:
- DigitalIn* _pin[16];
-
- /** Mask of bus's NC pins
- * If bit[n] is set to 1 - pin is connected
- * if bit[n] is cleared - pin is not connected (NC)
- */
- int _nc_mask;
-
- /* disallow copy constructor and assignment operators */
-private:
- BusIn(const BusIn&);
- BusIn & operator = (const BusIn&);
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h
deleted file mode 100644
index 54328fb02..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSINOUT_H
-#define MBED_BUSINOUT_H
-
-#include "DigitalInOut.h"
-
-namespace mbed {
-
-/** A digital input output bus, used for setting the state of a collection of pins
- */
-class BusInOut {
-
-public:
-
- /** Create an BusInOut, connected to the specified pins
- *
- * @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
- *
- * @note
- * It is only required to specify as many pin variables as is required
- * for the bus; the rest will default to NC (not connected)
- */
- BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
- PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
- PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
- PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
- BusInOut(PinName pins[16]);
-
- virtual ~BusInOut();
-
- /* Group: Access Methods */
-
- /** Write the value to the output bus
- *
- * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
- */
- void write(int value);
-
- /** Read the value currently output on the bus
- *
- * @returns
- * An integer with each bit corresponding to associated DigitalInOut pin setting
- */
- int read();
-
- /** Set as an output
- */
- void output();
-
- /** Set as an input
- */
- void input();
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone
- */
- void mode(PinMode pull);
-
- /** Binary mask of bus pins connected to actual pins (not NC pins)
- * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
- *
- * @returns
- * Binary mask of connected pins
- */
- int mask() {
- return _nc_mask;
- }
-
-#ifdef MBED_OPERATORS
- /** A shorthand for write()
- */
- BusInOut& operator= (int v);
- BusInOut& operator= (BusInOut& rhs);
-
- /** Access to particular bit in random-iterator fashion
- */
- DigitalInOut& operator[] (int index);
-
- /** A shorthand for read()
- */
- operator int();
-#endif
-
-protected:
- DigitalInOut* _pin[16];
-
- /** Mask of bus's NC pins
- * If bit[n] is set to 1 - pin is connected
- * if bit[n] is cleared - pin is not connected (NC)
- */
- int _nc_mask;
-
- /* disallow copy constructor and assignment operators */
-private:
- BusInOut(const BusInOut&);
- BusInOut & operator = (const BusInOut&);
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h
deleted file mode 100644
index 1c55be07e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSOUT_H
-#define MBED_BUSOUT_H
-
-#include "DigitalOut.h"
-
-namespace mbed {
-
-/** A digital output bus, used for setting the state of a collection of pins
- */
-class BusOut {
-
-public:
-
- /** Create an BusOut, connected to the specified pins
- *
- * @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
- *
- * @note
- * It is only required to specify as many pin variables as is required
- * for the bus; the rest will default to NC (not connected)
- */
- BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
- PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
- PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
- PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
- BusOut(PinName pins[16]);
-
- virtual ~BusOut();
-
- /** Write the value to the output bus
- *
- * @param value An integer specifying a bit to write for every corresponding DigitalOut pin
- */
- void write(int value);
-
- /** Read the value currently output on the bus
- *
- * @returns
- * An integer with each bit corresponding to associated DigitalOut pin setting
- */
- int read();
-
- /** Binary mask of bus pins connected to actual pins (not NC pins)
- * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
- *
- * @returns
- * Binary mask of connected pins
- */
- int mask() {
- return _nc_mask;
- }
-
-#ifdef MBED_OPERATORS
- /** A shorthand for write()
- */
- BusOut& operator= (int v);
- BusOut& operator= (BusOut& rhs);
-
- /** Access to particular bit in random-iterator fashion
- */
- DigitalOut& operator[] (int index);
-
- /** A shorthand for read()
- */
- operator int();
-#endif
-
-protected:
- DigitalOut* _pin[16];
-
- /** Mask of bus's NC pins
- * If bit[n] is set to 1 - pin is connected
- * if bit[n] is cleared - pin is not connected (NC)
- */
- int _nc_mask;
-
- /* disallow copy constructor and assignment operators */
-private:
- BusOut(const BusOut&);
- BusOut & operator = (const BusOut&);
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h
deleted file mode 100644
index db613f661..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_H
-#define MBED_CAN_H
-
-#include "platform.h"
-
-#if DEVICE_CAN
-
-#include "can_api.h"
-#include "can_helper.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** CANMessage class
- */
-class CANMessage : public CAN_Message {
-
-public:
- /** Creates empty CAN message.
- */
- CANMessage() : CAN_Message() {
- len = 8;
- type = CANData;
- format = CANStandard;
- id = 0;
- memset(data, 0, 8);
- }
-
- /** Creates CAN message with specific content.
- */
- CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
- len = _len & 0xF;
- type = _type;
- format = _format;
- id = _id;
- memcpy(data, _data, _len);
- }
-
- /** Creates CAN remote message.
- */
- CANMessage(int _id, CANFormat _format = CANStandard) {
- len = 0;
- type = CANRemote;
- format = _format;
- id = _id;
- memset(data, 0, 8);
- }
-};
-
-/** A can bus client, used for communicating with can devices
- */
-class CAN {
-
-public:
- /** Creates an CAN interface connected to specific pins.
- *
- * @param rd read from transmitter
- * @param td transmit to transmitter
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * Ticker ticker;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- * CAN can1(p9, p10);
- * CAN can2(p30, p29);
- *
- * char counter = 0;
- *
- * void send() {
- * if(can1.write(CANMessage(1337, &counter, 1))) {
- * printf("Message sent: %d\n", counter);
- * counter++;
- * }
- * led1 = !led1;
- * }
- *
- * int main() {
- * ticker.attach(&send, 1);
- * CANMessage msg;
- * while(1) {
- * if(can2.read(msg)) {
- * printf("Message received: %d\n\n", msg.data[0]);
- * led2 = !led2;
- * }
- * wait(0.2);
- * }
- * }
- * @endcode
- */
- CAN(PinName rd, PinName td);
- virtual ~CAN();
-
- /** Set the frequency of the CAN interface
- *
- * @param hz The bus frequency in hertz
- *
- * @returns
- * 1 if successful,
- * 0 otherwise
- */
- int frequency(int hz);
-
- /** Write a CANMessage to the bus.
- *
- * @param msg The CANMessage to write.
- *
- * @returns
- * 0 if write failed,
- * 1 if write was successful
- */
- int write(CANMessage msg);
-
- /** Read a CANMessage from the bus.
- *
- * @param msg A CANMessage to read to.
- * @param handle message filter handle (0 for any message)
- *
- * @returns
- * 0 if no message arrived,
- * 1 if message arrived
- */
- int read(CANMessage &msg, int handle = 0);
-
- /** Reset CAN interface.
- *
- * To use after error overflow.
- */
- void reset();
-
- /** Puts or removes the CAN interface into silent monitoring mode
- *
- * @param silent boolean indicating whether to go into silent mode or not
- */
- void monitor(bool silent);
-
- enum Mode {
- Reset = 0,
- Normal,
- Silent,
- LocalTest,
- GlobalTest,
- SilentTest
- };
-
- /** Change CAN operation to the specified mode
- *
- * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
- *
- * @returns
- * 0 if mode change failed or unsupported,
- * 1 if mode change was successful
- */
- int mode(Mode mode);
-
- /** Filter out incomming messages
- *
- * @param id the id to filter on
- * @param mask the mask applied to the id
- * @param format format to filter on (Default CANAny)
- * @param handle message filter handle (Optional)
- *
- * @returns
- * 0 if filter change failed or unsupported,
- * new filter handle if successful
- */
- int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
-
- /** Returns number of read errors to detect read overflow errors.
- */
- unsigned char rderror();
-
- /** Returns number of write errors to detect write overflow errors.
- */
- unsigned char tderror();
-
- enum IrqType {
- RxIrq = 0,
- TxIrq,
- EwIrq,
- DoIrq,
- WuIrq,
- EpIrq,
- AlIrq,
- BeIrq,
- IdIrq
- };
-
- /** Attach a function to call whenever a CAN frame received interrupt is
- * generated.
- *
- * @param fptr A pointer to a void function, or 0 to set as none
- * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
- */
- void attach(void (*fptr)(void), IrqType type=RxIrq);
-
- /** Attach a member function to call whenever a CAN frame received interrupt
- * is generated.
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
- */
- template<typename T>
- void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
- if((mptr != NULL) && (tptr != NULL)) {
- _irq[type].attach(tptr, mptr);
- can_irq_set(&_can, (CanIrqType)type, 1);
- }
- else {
- can_irq_set(&_can, (CanIrqType)type, 0);
- }
- }
-
- static void _irq_handler(uint32_t id, CanIrqType type);
-
-protected:
- can_t _can;
- FunctionPointer _irq[9];
-};
-
-} // namespace mbed
-
-#endif
-
-#endif // MBED_CAN_H
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h
deleted file mode 100644
index ebb796a3c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CALLCHAIN_H
-#define MBED_CALLCHAIN_H
-
-#include "FunctionPointer.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Group one or more functions in an instance of a CallChain, then call them in
- * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
- * but can be used for other purposes.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * CallChain chain;
- *
- * void first(void) {
- * printf("'first' function.\n");
- * }
- *
- * void second(void) {
- * printf("'second' function.\n");
- * }
- *
- * class Test {
- * public:
- * void f(void) {
- * printf("A::f (class member).\n");
- * }
- * };
- *
- * int main() {
- * Test test;
- *
- * chain.add(second);
- * chain.add_front(first);
- * chain.add(&test, &Test::f);
- * chain.call();
- * }
- * @endcode
- */
-
-typedef FunctionPointer* pFunctionPointer_t;
-
-class CallChain {
-public:
- /** Create an empty chain
- *
- * @param size (optional) Initial size of the chain
- */
- CallChain(int size = 4);
- virtual ~CallChain();
-
- /** Add a function at the end of the chain
- *
- * @param function A pointer to a void function
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add(void (*function)(void));
-
- /** Add a function at the end of the chain
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
- return common_add(new FunctionPointer(tptr, mptr));
- }
-
- /** Add a function at the beginning of the chain
- *
- * @param function A pointer to a void function
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add_front(void (*function)(void));
-
- /** Add a function at the beginning of the chain
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
- return common_add_front(new FunctionPointer(tptr, mptr));
- }
-
- /** Get the number of functions in the chain
- */
- int size() const;
-
- /** Get a function object from the chain
- *
- * @param i function object index
- *
- * @returns
- * The function object at position 'i' in the chain
- */
- pFunctionPointer_t get(int i) const;
-
- /** Look for a function object in the call chain
- *
- * @param f the function object to search
- *
- * @returns
- * The index of the function object if found, -1 otherwise.
- */
- int find(pFunctionPointer_t f) const;
-
- /** Clear the call chain (remove all functions in the chain).
- */
- void clear();
-
- /** Remove a function object from the chain
- *
- * @arg f the function object to remove
- *
- * @returns
- * true if the function object was found and removed, false otherwise.
- */
- bool remove(pFunctionPointer_t f);
-
- /** Call all the functions in the chain in sequence
- */
- void call();
-
-#ifdef MBED_OPERATORS
- void operator ()(void) {
- call();
- }
- pFunctionPointer_t operator [](int i) const {
- return get(i);
- }
-#endif
-
-private:
- void _check_size();
- pFunctionPointer_t common_add(pFunctionPointer_t pf);
- pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
-
- pFunctionPointer_t* _chain;
- int _size;
- int _elements;
-
- /* disallow copy constructor and assignment operators */
-private:
- CallChain(const CallChain&);
- CallChain & operator = (const CallChain&);
-};
-
-} // namespace mbed
-
-#endif
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h
deleted file mode 100644
index b089de9fa..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALIN_H
-#define MBED_DIGITALIN_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital input, used for reading the state of a pin
- *
- * Example:
- * @code
- * // Flash an LED while a DigitalIn is true
- *
- * #include "mbed.h"
- *
- * DigitalIn enable(p5);
- * DigitalOut led(LED1);
- *
- * int main() {
- * while(1) {
- * if(enable) {
- * led = !led;
- * }
- * wait(0.25);
- * }
- * }
- * @endcode
- */
-class DigitalIn {
-
-public:
- /** Create a DigitalIn connected to the specified pin
- *
- * @param pin DigitalIn pin to connect to
- */
- DigitalIn(PinName pin) : gpio() {
- gpio_init_in(&gpio, pin);
- }
-
- /** Create a DigitalIn connected to the specified pin
- *
- * @param pin DigitalIn pin to connect to
- * @param mode the initial mode of the pin
- */
- DigitalIn(PinName pin, PinMode mode) : gpio() {
- gpio_init_in_ex(&gpio, pin, mode);
- }
- /** Read the input, represented as 0 or 1 (int)
- *
- * @returns
- * An integer representing the state of the input pin,
- * 0 for logical 0, 1 for logical 1
- */
- int read() {
- return gpio_read(&gpio);
- }
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode pull) {
- gpio_mode(&gpio, pull);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * Non zero value if pin is connected to uc GPIO
- * 0 if gpio object was initialized with NC
- */
- int is_connected() {
- return gpio_is_connected(&gpio);
- }
-
-#ifdef MBED_OPERATORS
- /** An operator shorthand for read()
- */
- operator int() {
- return read();
- }
-#endif
-
-protected:
- gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h
deleted file mode 100644
index e30be0e63..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALINOUT_H
-#define MBED_DIGITALINOUT_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital input/output, used for setting or reading a bi-directional pin
- */
-class DigitalInOut {
-
-public:
- /** Create a DigitalInOut connected to the specified pin
- *
- * @param pin DigitalInOut pin to connect to
- */
- DigitalInOut(PinName pin) : gpio() {
- gpio_init_in(&gpio, pin);
- }
-
- /** Create a DigitalInOut connected to the specified pin
- *
- * @param pin DigitalInOut pin to connect to
- * @param direction the initial direction of the pin
- * @param mode the initial mode of the pin
- * @param value the initial value of the pin if is an output
- */
- DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
- gpio_init_inout(&gpio, pin, direction, mode, value);
- }
-
- /** Set the output, specified as 0 or 1 (int)
- *
- * @param value An integer specifying the pin output value,
- * 0 for logical 0, 1 (or any other non-zero value) for logical 1
- */
- void write(int value) {
- gpio_write(&gpio, value);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * an integer representing the output setting of the pin if it is an output,
- * or read the input if set as an input
- */
- int read() {
- return gpio_read(&gpio);
- }
-
- /** Set as an output
- */
- void output() {
- gpio_dir(&gpio, PIN_OUTPUT);
- }
-
- /** Set as an input
- */
- void input() {
- gpio_dir(&gpio, PIN_INPUT);
- }
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode pull) {
- gpio_mode(&gpio, pull);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * Non zero value if pin is connected to uc GPIO
- * 0 if gpio object was initialized with NC
- */
- int is_connected() {
- return gpio_is_connected(&gpio);
- }
-
-#ifdef MBED_OPERATORS
- /** A shorthand for write()
- */
- DigitalInOut& operator= (int value) {
- write(value);
- return *this;
- }
-
- DigitalInOut& operator= (DigitalInOut& rhs) {
- write(rhs.read());
- return *this;
- }
-
- /** A shorthand for read()
- */
- operator int() {
- return read();
- }
-#endif
-
-protected:
- gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h
deleted file mode 100644
index 0d66f907b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALOUT_H
-#define MBED_DIGITALOUT_H
-
-#include "platform.h"
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital output, used for setting the state of a pin
- *
- * Example:
- * @code
- * // Toggle a LED
- * #include "mbed.h"
- *
- * DigitalOut led(LED1);
- *
- * int main() {
- * while(1) {
- * led = !led;
- * wait(0.2);
- * }
- * }
- * @endcode
- */
-class DigitalOut {
-
-public:
- /** Create a DigitalOut connected to the specified pin
- *
- * @param pin DigitalOut pin to connect to
- */
- DigitalOut(PinName pin) : gpio() {
- gpio_init_out(&gpio, pin);
- }
-
- /** Create a DigitalOut connected to the specified pin
- *
- * @param pin DigitalOut pin to connect to
- * @param value the initial pin value
- */
- DigitalOut(PinName pin, int value) : gpio() {
- gpio_init_out_ex(&gpio, pin, value);
- }
-
- /** Set the output, specified as 0 or 1 (int)
- *
- * @param value An integer specifying the pin output value,
- * 0 for logical 0, 1 (or any other non-zero value) for logical 1
- */
- void write(int value) {
- gpio_write(&gpio, value);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * an integer representing the output setting of the pin,
- * 0 for logical 0, 1 for logical 1
- */
- int read() {
- return gpio_read(&gpio);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * Non zero value if pin is connected to uc GPIO
- * 0 if gpio object was initialized with NC
- */
- int is_connected() {
- return gpio_is_connected(&gpio);
- }
-
-#ifdef MBED_OPERATORS
- /** A shorthand for write()
- */
- DigitalOut& operator= (int value) {
- write(value);
- return *this;
- }
-
- DigitalOut& operator= (DigitalOut& rhs) {
- write(rhs.read());
- return *this;
- }
-
- /** A shorthand for read()
- */
- operator int() {
- return read();
- }
-#endif
-
-protected:
- gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h
deleted file mode 100644
index 329f4d1c7..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIRHANDLE_H
-#define MBED_DIRHANDLE_H
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-# define NAME_MAX 255
-typedef int mode_t;
-
-#else
-# include <sys/syslimits.h>
-#endif
-
-#include "FileHandle.h"
-
-struct dirent {
- char d_name[NAME_MAX+1];
-};
-
-namespace mbed {
-
-/** Represents a directory stream. Objects of this type are returned
- * by a FileSystemLike's opendir method. Implementations must define
- * at least closedir, readdir and rewinddir.
- *
- * If a FileSystemLike class defines the opendir method, then the
- * directories of an object of that type can be accessed by
- * DIR *d = opendir("/example/directory") (or opendir("/example")
- * to open the root of the filesystem), and then using readdir(d) etc.
- *
- * The root directory is considered to contain all FileLike and
- * FileSystemLike objects, so the DIR* returned by opendir("/") will
- * reflect this.
- */
-class DirHandle {
-
-public:
- /** Closes the directory.
- *
- * @returns
- * 0 on success,
- * -1 on error.
- */
- virtual int closedir()=0;
-
- /** Return the directory entry at the current position, and
- * advances the position to the next entry.
- *
- * @returns
- * A pointer to a dirent structure representing the
- * directory entry at the current position, or NULL on reaching
- * end of directory or error.
- */
- virtual struct dirent *readdir()=0;
-
- /** Resets the position to the beginning of the directory.
- */
- virtual void rewinddir()=0;
-
- /** Returns the current position of the DirHandle.
- *
- * @returns
- * the current position,
- * -1 on error.
- */
- virtual off_t telldir() { return -1; }
-
- /** Sets the position of the DirHandle.
- *
- * @param location The location to seek to. Must be a value returned by telldir.
- */
- virtual void seekdir(off_t location) { }
-
- virtual ~DirHandle() {}
-};
-
-} // namespace mbed
-
-typedef mbed::DirHandle DIR;
-
-extern "C" {
- DIR *opendir(const char*);
- struct dirent *readdir(DIR *);
- int closedir(DIR*);
- void rewinddir(DIR*);
- long telldir(DIR*);
- void seekdir(DIR*, long);
- int mkdir(const char *name, mode_t n);
-};
-
-#endif /* MBED_DIRHANDLE_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h
deleted file mode 100644
index d0e59a5cf..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_H
-#define MBED_ETHERNET_H
-
-#include "platform.h"
-
-#if DEVICE_ETHERNET
-
-namespace mbed {
-
-/** An ethernet interface, to use with the ethernet pins.
- *
- * Example:
- * @code
- * // Read destination and source from every ethernet packet
- *
- * #include "mbed.h"
- *
- * Ethernet eth;
- *
- * int main() {
- * char buf[0x600];
- *
- * while(1) {
- * int size = eth.receive();
- * if(size > 0) {
- * eth.read(buf, size);
- * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n",
- * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
- * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
- * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
- * }
- *
- * wait(1);
- * }
- * }
- * @endcode
- */
-class Ethernet {
-
-public:
-
- /** Initialise the ethernet interface.
- */
- Ethernet();
-
- /** Powers the hardware down.
- */
- virtual ~Ethernet();
-
- enum Mode {
- AutoNegotiate,
- HalfDuplex10,
- FullDuplex10,
- HalfDuplex100,
- FullDuplex100
- };
-
- /** Writes into an outgoing ethernet packet.
- *
- * It will append size bytes of data to the previously written bytes.
- *
- * @param data An array to write.
- * @param size The size of data.
- *
- * @returns
- * The number of written bytes.
- */
- int write(const char *data, int size);
-
- /** Send an outgoing ethernet packet.
- *
- * After filling in the data in an ethernet packet it must be send.
- * Send will provide a new packet to write to.
- *
- * @returns
- * 0 if the sending was failed,
- * or the size of the packet successfully sent.
- */
- int send();
-
- /** Recevies an arrived ethernet packet.
- *
- * Receiving an ethernet packet will drop the last received ethernet packet
- * and make a new ethernet packet ready to read.
- * If no ethernet packet is arrived it will return 0.
- *
- * @returns
- * 0 if no ethernet packet is arrived,
- * or the size of the arrived packet.
- */
- int receive();
-
- /** Read from an recevied ethernet packet.
- *
- * After receive returnd a number bigger than 0it is
- * possible to read bytes from this packet.
- * Read will write up to size bytes into data.
- *
- * It is possible to use read multible times.
- * Each time read will start reading after the last read byte before.
- *
- * @returns
- * The number of byte read.
- */
- int read(char *data, int size);
-
- /** Gives the ethernet address of the mbed.
- *
- * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
- */
- void address(char *mac);
-
- /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
- *
- * @returns
- * 0 if no ethernet link is pressent,
- * 1 if an ethernet link is pressent.
- *
- * Example:
- * @code
- * // Using the Ethernet link function
- * #include "mbed.h"
- *
- * Ethernet eth;
- *
- * int main() {
- * wait(1); // Needed after startup.
- * if (eth.link()) {
- * printf("online\n");
- * } else {
- * printf("offline\n");
- * }
- * }
- * @endcode
- */
- int link();
-
- /** Sets the speed and duplex parameters of an ethernet link
- *
- * - AutoNegotiate Auto negotiate speed and duplex
- * - HalfDuplex10 10 Mbit, half duplex
- * - FullDuplex10 10 Mbit, full duplex
- * - HalfDuplex100 100 Mbit, half duplex
- * - FullDuplex100 100 Mbit, full duplex
- *
- * @param mode the speed and duplex mode to set the link to:
- */
- void set_link(Mode mode);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h
deleted file mode 100644
index 88f87842c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEBASE_H
-#define MBED_FILEBASE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-# define O_RDONLY 0
-# define O_WRONLY 1
-# define O_RDWR 2
-# define O_CREAT 0x0200
-# define O_TRUNC 0x0400
-# define O_APPEND 0x0008
-
-# define NAME_MAX 255
-
-typedef int mode_t;
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-# include <sys/fcntl.h>
-# include <sys/types.h>
-# include <sys/syslimits.h>
-#endif
-
-#include "platform.h"
-
-namespace mbed {
-
-typedef enum {
- FilePathType,
- FileSystemPathType
-} PathType;
-
-class FileBase {
-public:
- FileBase(const char *name, PathType t);
-
- virtual ~FileBase();
-
- const char* getName(void);
- PathType getPathType(void);
-
- static FileBase *lookup(const char *name, unsigned int len);
-
- static FileBase *get(int n);
-
-protected:
- static FileBase *_head;
-
- FileBase *_next;
- const char *_name;
- PathType _path_type;
-
- /* disallow copy constructor and assignment operators */
-private:
- FileBase(const FileBase&);
- FileBase & operator = (const FileBase&);
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h
deleted file mode 100644
index 0a98a827c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEHANDLE_H
-#define MBED_FILEHANDLE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-# include <sys/types.h>
-#endif
-
-namespace mbed {
-
-/** An OO equivalent of the internal FILEHANDLE variable
- * and associated _sys_* functions.
- *
- * FileHandle is an abstract class, needing at least sys_write and
- * sys_read to be implmented for a simple interactive device.
- *
- * No one ever directly tals to/instanciates a FileHandle - it gets
- * created by FileSystem, and wrapped up by stdio.
- */
-class FileHandle {
-
-public:
- /** Write the contents of a buffer to the file
- *
- * @param buffer the buffer to write from
- * @param length the number of characters to write
- *
- * @returns
- * The number of characters written (possibly 0) on success, -1 on error.
- */
- virtual ssize_t write(const void* buffer, size_t length) = 0;
-
- /** Close the file
- *
- * @returns
- * Zero on success, -1 on error.
- */
- virtual int close() = 0;
-
- /** Function read
- * Reads the contents of the file into a buffer
- *
- * @param buffer the buffer to read in to
- * @param length the number of characters to read
- *
- * @returns
- * The number of characters read (zero at end of file) on success, -1 on error.
- */
- virtual ssize_t read(void* buffer, size_t length) = 0;
-
- /** Check if the handle is for a interactive terminal device.
- * If so, line buffered behaviour is used by default
- *
- * @returns
- * 1 if it is a terminal,
- * 0 otherwise
- */
- virtual int isatty() = 0;
-
- /** Move the file position to a given offset from a given location.
- *
- * @param offset The offset from whence to move to
- * @param whence SEEK_SET for the start of the file, SEEK_CUR for the
- * current file position, or SEEK_END for the end of the file.
- *
- * @returns
- * new file position on success,
- * -1 on failure or unsupported
- */
- virtual off_t lseek(off_t offset, int whence) = 0;
-
- /** Flush any buffers associated with the FileHandle, ensuring it
- * is up to date on disk
- *
- * @returns
- * 0 on success or un-needed,
- * -1 on error
- */
- virtual int fsync() = 0;
-
- virtual off_t flen() {
- /* remember our current position */
- off_t pos = lseek(0, SEEK_CUR);
- if(pos == -1) return -1;
- /* seek to the end to get the file length */
- off_t res = lseek(0, SEEK_END);
- /* return to our old position */
- lseek(pos, SEEK_SET);
- return res;
- }
-
- virtual ~FileHandle();
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h
deleted file mode 100644
index 666575c90..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILELIKE_H
-#define MBED_FILELIKE_H
-
-#include "FileBase.h"
-#include "FileHandle.h"
-
-namespace mbed {
-
-/* Class FileLike
- * A file-like object is one that can be opened with fopen by
- * fopen("/name", mode). It is intersection of the classes Base and
- * FileHandle.
- */
-class FileLike : public FileHandle, public FileBase {
-
-public:
- /* Constructor FileLike
- *
- * Variables
- * name - The name to use to open the file.
- */
- FileLike(const char *name);
-
- virtual ~FileLike();
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h
deleted file mode 100644
index 3de120504..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEPATH_H
-#define MBED_FILEPATH_H
-
-#include "platform.h"
-
-#include "FileSystemLike.h"
-#include "FileLike.h"
-
-namespace mbed {
-
-class FilePath {
-public:
- FilePath(const char* file_path);
-
- const char* fileName(void);
-
- bool isFileSystem(void);
- FileSystemLike* fileSystem(void);
-
- bool isFile(void);
- FileLike* file(void);
- bool exists(void);
-
-private:
- const char* file_name;
- FileBase* fb;
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h
deleted file mode 100644
index 6680c4cb0..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILESYSTEMLIKE_H
-#define MBED_FILESYSTEMLIKE_H
-
-#include "platform.h"
-
-#include "FileBase.h"
-#include "FileHandle.h"
-#include "DirHandle.h"
-
-namespace mbed {
-
-/** A filesystem-like object is one that can be used to open files
- * though it by fopen("/name/filename", mode)
- *
- * Implementations must define at least open (the default definitions
- * of the rest of the functions just return error values).
- */
-class FileSystemLike : public FileBase {
-
-public:
- /** FileSystemLike constructor
- *
- * @param name The name to use for the filesystem.
- */
- FileSystemLike(const char *name);
-
- virtual ~FileSystemLike();
-
- static DirHandle *opendir();
- friend class BaseDirHandle;
-
- /** Opens a file from the filesystem
- *
- * @param filename The name of the file to open.
- * @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
- * zero or more of O_CREAT, O_TRUNC, or O_APPEND.
- *
- * @returns
- * A pointer to a FileHandle object representing the
- * file on success, or NULL on failure.
- */
- virtual FileHandle *open(const char *filename, int flags) = 0;
-
- /** Remove a file from the filesystem.
- *
- * @param filename the name of the file to remove.
- * @param returns 0 on success, -1 on failure.
- */
- virtual int remove(const char *filename) { return -1; };
-
- /** Rename a file in the filesystem.
- *
- * @param oldname the name of the file to rename.
- * @param newname the name to rename it to.
- *
- * @returns
- * 0 on success,
- * -1 on failure.
- */
- virtual int rename(const char *oldname, const char *newname) { return -1; };
-
- /** Opens a directory in the filesystem and returns a DirHandle
- * representing the directory stream.
- *
- * @param name The name of the directory to open.
- *
- * @returns
- * A DirHandle representing the directory stream, or
- * NULL on failure.
- */
- virtual DirHandle *opendir(const char *name) { return NULL; };
-
- /** Creates a directory in the filesystem.
- *
- * @param name The name of the directory to create.
- * @param mode The permissions to create the directory with.
- *
- * @returns
- * 0 on success,
- * -1 on failure.
- */
- virtual int mkdir(const char *name, mode_t mode) { return -1; }
-
- // TODO other filesystem functions (mkdir, rm, rn, ls etc)
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h
deleted file mode 100644
index 1ae492283..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FUNCTIONPOINTER_H
-#define MBED_FUNCTIONPOINTER_H
-
-#include <string.h>
-
-namespace mbed {
-
-typedef void (*pvoidf_t)(void);
-
-/** A class for storing and calling a pointer to a static or member void function
- */
-class FunctionPointer {
-public:
-
- /** Create a FunctionPointer, attaching a static function
- *
- * @param function The void static function to attach (default is none)
- */
- FunctionPointer(void (*function)(void) = 0);
-
- /** Create a FunctionPointer, attaching a member function
- *
- * @param object The object pointer to invoke the member function on (i.e. the this pointer)
- * @param function The address of the void member function to attach
- */
- template<typename T>
- FunctionPointer(T *object, void (T::*member)(void)) {
- attach(object, member);
- }
-
- /** Attach a static function
- *
- * @param function The void static function to attach (default is none)
- */
- void attach(void (*function)(void) = 0);
-
- /** Attach a member function
- *
- * @param object The object pointer to invoke the member function on (i.e. the this pointer)
- * @param function The address of the void member function to attach
- */
- template<typename T>
- void attach(T *object, void (T::*member)(void)) {
- _object = static_cast<void*>(object);
- memcpy(_member, (char*)&member, sizeof(member));
- _membercaller = &FunctionPointer::membercaller<T>;
- _function = 0;
- }
-
- /** Call the attached static or member function
- */
- void call();
-
- pvoidf_t get_function() const {
- return (pvoidf_t)_function;
- }
-
-#ifdef MBED_OPERATORS
- void operator ()(void);
-#endif
-
-private:
- template<typename T>
- static void membercaller(void *object, char *member) {
- T* o = static_cast<T*>(object);
- void (T::*m)(void);
- memcpy((char*)&m, member, sizeof(m));
- (o->*m)();
- }
-
- void (*_function)(void); // static function pointer - 0 if none attached
- void *_object; // object this pointer - 0 if none attached
- char _member[16]; // raw member function pointer storage - converted back by registered _membercaller
- void (*_membercaller)(void*, char*); // registered membercaller function to convert back and call _member on _object
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h
deleted file mode 100644
index bd7cf1223..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_H
-#define MBED_I2C_H
-
-#include "platform.h"
-
-#if DEVICE_I2C
-
-#include "i2c_api.h"
-
-namespace mbed {
-
-/** An I2C Master, used for communicating with I2C slave devices
- *
- * Example:
- * @code
- * // Read from I2C slave at address 0x62
- *
- * #include "mbed.h"
- *
- * I2C i2c(p28, p27);
- *
- * int main() {
- * int address = 0x62;
- * char data[2];
- * i2c.read(address, data, 2);
- * }
- * @endcode
- */
-class I2C {
-
-public:
- enum RxStatus {
- NoData,
- MasterGeneralCall,
- MasterWrite,
- MasterRead
- };
-
- enum Acknowledge {
- NoACK = 0,
- ACK = 1
- };
-
- /** Create an I2C Master interface, connected to the specified pins
- *
- * @param sda I2C data line pin
- * @param scl I2C clock line pin
- */
- I2C(PinName sda, PinName scl);
-
- /** Set the frequency of the I2C interface
- *
- * @param hz The bus frequency in hertz
- */
- void frequency(int hz);
-
- /** Read from an I2C slave
- *
- * Performs a complete read transaction. The bottom bit of
- * the address is forced to 1 to indicate a read.
- *
- * @param address 8-bit I2C slave address [ addr | 1 ]
- * @param data Pointer to the byte-array to read data in to
- * @param length Number of bytes to read
- * @param repeated Repeated start, true - don't send stop at end
- *
- * @returns
- * 0 on success (ack),
- * non-0 on failure (nack)
- */
- int read(int address, char *data, int length, bool repeated = false);
-
- /** Read a single byte from the I2C bus
- *
- * @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
- *
- * @returns
- * the byte read
- */
- int read(int ack);
-
- /** Write to an I2C slave
- *
- * Performs a complete write transaction. The bottom bit of
- * the address is forced to 0 to indicate a write.
- *
- * @param address 8-bit I2C slave address [ addr | 0 ]
- * @param data Pointer to the byte-array data to send
- * @param length Number of bytes to send
- * @param repeated Repeated start, true - do not send stop at end
- *
- * @returns
- * 0 on success (ack),
- * non-0 on failure (nack)
- */
- int write(int address, const char *data, int length, bool repeated = false);
-
- /** Write single byte out on the I2C bus
- *
- * @param data data to write out on bus
- *
- * @returns
- * '1' if an ACK was received,
- * '0' otherwise
- */
- int write(int data);
-
- /** Creates a start condition on the I2C bus
- */
-
- void start(void);
-
- /** Creates a stop condition on the I2C bus
- */
- void stop(void);
-
-protected:
- void aquire();
-
- i2c_t _i2c;
- static I2C *_owner;
- int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h
deleted file mode 100644
index 738faea27..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_SLAVE_H
-#define MBED_I2C_SLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_I2CSLAVE
-
-#include "i2c_api.h"
-
-namespace mbed {
-
-/** An I2C Slave, used for communicating with an I2C Master device
- *
- * Example:
- * @code
- * // Simple I2C responder
- * #include <mbed.h>
- *
- * I2CSlave slave(p9, p10);
- *
- * int main() {
- * char buf[10];
- * char msg[] = "Slave!";
- *
- * slave.address(0xA0);
- * while (1) {
- * int i = slave.receive();
- * switch (i) {
- * case I2CSlave::ReadAddressed:
- * slave.write(msg, strlen(msg) + 1); // Includes null char
- * break;
- * case I2CSlave::WriteGeneral:
- * slave.read(buf, 10);
- * printf("Read G: %s\n", buf);
- * break;
- * case I2CSlave::WriteAddressed:
- * slave.read(buf, 10);
- * printf("Read A: %s\n", buf);
- * break;
- * }
- * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer
- * }
- * }
- * @endcode
- */
-class I2CSlave {
-
-public:
- enum RxStatus {
- NoData = 0,
- ReadAddressed = 1,
- WriteGeneral = 2,
- WriteAddressed = 3
- };
-
- /** Create an I2C Slave interface, connected to the specified pins.
- *
- * @param sda I2C data line pin
- * @param scl I2C clock line pin
- */
- I2CSlave(PinName sda, PinName scl);
-
- /** Set the frequency of the I2C interface
- *
- * @param hz The bus frequency in hertz
- */
- void frequency(int hz);
-
- /** Checks to see if this I2C Slave has been addressed.
- *
- * @returns
- * A status indicating if the device has been addressed, and how
- * - NoData - the slave has not been addressed
- * - ReadAddressed - the master has requested a read from this slave
- * - WriteAddressed - the master is writing to this slave
- * - WriteGeneral - the master is writing to all slave
- */
- int receive(void);
-
- /** Read from an I2C master.
- *
- * @param data pointer to the byte array to read data in to
- * @param length maximum number of bytes to read
- *
- * @returns
- * 0 on success,
- * non-0 otherwise
- */
- int read(char *data, int length);
-
- /** Read a single byte from an I2C master.
- *
- * @returns
- * the byte read
- */
- int read(void);
-
- /** Write to an I2C master.
- *
- * @param data pointer to the byte array to be transmitted
- * @param length the number of bytes to transmite
- *
- * @returns
- * 0 on success,
- * non-0 otherwise
- */
- int write(const char *data, int length);
-
- /** Write a single byte to an I2C master.
- *
- * @data the byte to write
- *
- * @returns
- * '1' if an ACK was received,
- * '0' otherwise
- */
- int write(int data);
-
- /** Sets the I2C slave address.
- *
- * @param address The address to set for the slave (ignoring the least
- * signifcant bit). If set to 0, the slave will only respond to the
- * general call address.
- */
- void address(int address);
-
- /** Reset the I2C slave back into the known ready receiving state.
- */
- void stop(void);
-
-protected:
- i2c_t _i2c;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h
deleted file mode 100644
index 88bc4308e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERRUPTIN_H
-#define MBED_INTERRUPTIN_H
-
-#include "platform.h"
-
-#if DEVICE_INTERRUPTIN
-
-#include "gpio_api.h"
-#include "gpio_irq_api.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** A digital interrupt input, used to call a function on a rising or falling edge
- *
- * Example:
- * @code
- * // Flash an LED while waiting for events
- *
- * #include "mbed.h"
- *
- * InterruptIn event(p16);
- * DigitalOut led(LED1);
- *
- * void trigger() {
- * printf("triggered!\n");
- * }
- *
- * int main() {
- * event.rise(&trigger);
- * while(1) {
- * led = !led;
- * wait(0.25);
- * }
- * }
- * @endcode
- */
-class InterruptIn {
-
-public:
-
- /** Create an InterruptIn connected to the specified pin
- *
- * @param pin InterruptIn pin to connect to
- * @param name (optional) A string to identify the object
- */
- InterruptIn(PinName pin);
- virtual ~InterruptIn();
-
- int read();
-#ifdef MBED_OPERATORS
- operator int();
-
-#endif
-
- /** Attach a function to call when a rising edge occurs on the input
- *
- * @param fptr A pointer to a void function, or 0 to set as none
- */
- void rise(void (*fptr)(void));
-
- /** Attach a member function to call when a rising edge occurs on the input
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- */
- template<typename T>
- void rise(T* tptr, void (T::*mptr)(void)) {
- _rise.attach(tptr, mptr);
- gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
- }
-
- /** Attach a function to call when a falling edge occurs on the input
- *
- * @param fptr A pointer to a void function, or 0 to set as none
- */
- void fall(void (*fptr)(void));
-
- /** Attach a member function to call when a falling edge occurs on the input
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- */
- template<typename T>
- void fall(T* tptr, void (T::*mptr)(void)) {
- _fall.attach(tptr, mptr);
- gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
- }
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone
- */
- void mode(PinMode pull);
-
- /** Enable IRQ. This method depends on hw implementation, might enable one
- * port interrupts. For further information, check gpio_irq_enable().
- */
- void enable_irq();
-
- /** Disable IRQ. This method depends on hw implementation, might disable one
- * port interrupts. For further information, check gpio_irq_disable().
- */
- void disable_irq();
-
- static void _irq_handler(uint32_t id, gpio_irq_event event);
-
-protected:
- gpio_t gpio;
- gpio_irq_t gpio_irq;
-
- FunctionPointer _rise;
- FunctionPointer _fall;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h
deleted file mode 100644
index 4959a6469..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h
+++ /dev/null
@@ -1,143 +0,0 @@
-#ifndef MBED_INTERRUPTMANAGER_H
-#define MBED_INTERRUPTMANAGER_H
-
-#include "cmsis.h"
-#include "CallChain.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Use this singleton if you need to chain interrupt handlers.
- *
- * Example (for LPC1768):
- * @code
- * #include "InterruptManager.h"
- * #include "mbed.h"
- *
- * Ticker flipper;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * void flip(void) {
- * led1 = !led1;
- * }
- *
- * void handler(void) {
- * led2 = !led1;
- * }
- *
- * int main() {
- * led1 = led2 = 0;
- * flipper.attach(&flip, 1.0);
- * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
- * }
- * @endcode
- */
-class InterruptManager {
-public:
- /** Return the only instance of this class
- */
- static InterruptManager* get();
-
- /** Destroy the current instance of the interrupt manager
- */
- static void destroy();
-
- /** Add a handler for an interrupt at the end of the handler list
- *
- * @param function the handler to add
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
- return add_common(function, irq);
- }
-
- /** Add a handler for an interrupt at the beginning of the handler list
- *
- * @param function the handler to add
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
- return add_common(function, irq, true);
- }
-
- /** Add a handler for an interrupt at the end of the handler list
- *
- * @param tptr pointer to the object that has the handler function
- * @param mptr pointer to the actual handler function
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
- return add_common(tptr, mptr, irq);
- }
-
- /** Add a handler for an interrupt at the beginning of the handler list
- *
- * @param tptr pointer to the object that has the handler function
- * @param mptr pointer to the actual handler function
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
- return add_common(tptr, mptr, irq, true);
- }
-
- /** Remove a handler from an interrupt
- *
- * @param handler the function object for the handler to remove
- * @param irq the interrupt number
- *
- * @returns
- * true if the handler was found and removed, false otherwise
- */
- bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
-
-private:
- InterruptManager();
- ~InterruptManager();
-
- // We declare the copy contructor and the assignment operator, but we don't
- // implement them. This way, if someone tries to copy/assign our instance,
- // he will get an error at compile time.
- InterruptManager(const InterruptManager&);
- InterruptManager& operator =(const InterruptManager&);
-
- template<typename T>
- pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
- int irq_pos = get_irq_index(irq);
- bool change = must_replace_vector(irq);
-
- pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
- if (change)
- NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
- return pf;
- }
-
- pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
- bool must_replace_vector(IRQn_Type irq);
- int get_irq_index(IRQn_Type irq);
- void irq_helper();
- void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
- static void static_irq_helper();
-
- CallChain* _chains[NVIC_NUM_VECTORS];
- static InterruptManager* _instance;
-};
-
-} // namespace mbed
-
-#endif
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h
deleted file mode 100644
index 9eb61a4b9..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOCALFILESYSTEM_H
-#define MBED_LOCALFILESYSTEM_H
-
-#include "platform.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "FileSystemLike.h"
-
-namespace mbed {
-
-FILEHANDLE local_file_open(const char* name, int flags);
-
-class LocalFileHandle : public FileHandle {
-
-public:
- LocalFileHandle(FILEHANDLE fh);
-
- virtual int close();
-
- virtual ssize_t write(const void *buffer, size_t length);
-
- virtual ssize_t read(void *buffer, size_t length);
-
- virtual int isatty();
-
- virtual off_t lseek(off_t position, int whence);
-
- virtual int fsync();
-
- virtual off_t flen();
-
-protected:
- FILEHANDLE _fh;
- int pos;
-};
-
-/** A filesystem for accessing the local mbed Microcontroller USB disk drive
- *
- * This allows programs to read and write files on the same disk drive that is used to program the
- * mbed Microcontroller. Once created, the standard C file access functions are used to open,
- * read and write files.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * LocalFileSystem local("local"); // Create the local filesystem under the name "local"
- *
- * int main() {
- * FILE *fp = fopen("/local/out.txt", "w"); // Open "out.txt" on the local file system for writing
- * fprintf(fp, "Hello World!");
- * fclose(fp);
- * remove("/local/out.txt"); // Removes the file "out.txt" from the local file system
- *
- * DIR *d = opendir("/local"); // Opens the root directory of the local file system
- * struct dirent *p;
- * while((p = readdir(d)) != NULL) { // Print the names of the files in the local file system
- * printf("%s\n", p->d_name); // to stdout.
- * }
- * closedir(d);
- * }
- * @endcode
- *
- * @note
- * If the microcontroller program makes an access to the local drive, it will be marked as "removed"
- * on the Host computer. This means it is no longer accessible from the Host Computer.
- *
- * The drive will only re-appear when the microcontroller program exists. Note that if the program does
- * not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
- */
-class LocalFileSystem : public FileSystemLike {
-
-public:
- LocalFileSystem(const char* n) : FileSystemLike(n) {
-
- }
-
- virtual FileHandle *open(const char* name, int flags);
- virtual int remove(const char *filename);
- virtual DirHandle *opendir(const char *name);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h
deleted file mode 100644
index 44686325c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTIN_H
-#define MBED_PORTIN_H
-
-#include "platform.h"
-
-#if DEVICE_PORTIN
-
-#include "port_api.h"
-
-namespace mbed {
-
-/** A multiple pin digital input
- *
- * Example:
- * @code
- * // Switch on an LED if any of mbed pins 21-26 is high
- *
- * #include "mbed.h"
- *
- * PortIn p(Port2, 0x0000003F); // p21-p26
- * DigitalOut ind(LED4);
- *
- * int main() {
- * while(1) {
- * int pins = p.read();
- * if(pins) {
- * ind = 1;
- * } else {
- * ind = 0;
- * }
- * }
- * }
- * @endcode
- */
-class PortIn {
-public:
-
- /** Create an PortIn, connected to the specified port
- *
- * @param port Port to connect to (Port0-Port5)
- * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
- */
- PortIn(PortName port, int mask = 0xFFFFFFFF) {
- port_init(&_port, port, mask, PIN_INPUT);
- }
-
- /** Read the value currently output on the port
- *
- * @returns
- * An integer with each bit corresponding to associated port pin setting
- */
- int read() {
- return port_read(&_port);
- }
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode mode) {
- port_mode(&_port, mode);
- }
-
- /** A shorthand for read()
- */
- operator int() {
- return read();
- }
-
-private:
- port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h
deleted file mode 100644
index cca755126..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTINOUT_H
-#define MBED_PORTINOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTINOUT
-
-#include "port_api.h"
-
-namespace mbed {
-
-/** A multiple pin digital in/out used to set/read multiple bi-directional pins
- */
-class PortInOut {
-public:
-
- /** Create an PortInOut, connected to the specified port
- *
- * @param port Port to connect to (Port0-Port5)
- * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
- */
- PortInOut(PortName port, int mask = 0xFFFFFFFF) {
- port_init(&_port, port, mask, PIN_INPUT);
- }
-
- /** Write the value to the output port
- *
- * @param value An integer specifying a bit to write for every corresponding port pin
- */
- void write(int value) {
- port_write(&_port, value);
- }
-
- /** Read the value currently output on the port
- *
- * @returns
- * An integer with each bit corresponding to associated port pin setting
- */
- int read() {
- return port_read(&_port);
- }
-
- /** Set as an output
- */
- void output() {
- port_dir(&_port, PIN_OUTPUT);
- }
-
- /** Set as an input
- */
- void input() {
- port_dir(&_port, PIN_INPUT);
- }
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode mode) {
- port_mode(&_port, mode);
- }
-
- /** A shorthand for write()
- */
- PortInOut& operator= (int value) {
- write(value);
- return *this;
- }
-
- PortInOut& operator= (PortInOut& rhs) {
- write(rhs.read());
- return *this;
- }
-
- /** A shorthand for read()
- */
- operator int() {
- return read();
- }
-
-private:
- port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h
deleted file mode 100644
index bab5fe0c6..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTOUT_H
-#define MBED_PORTOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTOUT
-
-#include "port_api.h"
-
-namespace mbed {
-/** A multiple pin digital out
- *
- * Example:
- * @code
- * // Toggle all four LEDs
- *
- * #include "mbed.h"
- *
- * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23
- * #define LED_MASK 0x00B40000
- *
- * PortOut ledport(Port1, LED_MASK);
- *
- * int main() {
- * while(1) {
- * ledport = LED_MASK;
- * wait(1);
- * ledport = 0;
- * wait(1);
- * }
- * }
- * @endcode
- */
-class PortOut {
-public:
-
- /** Create an PortOut, connected to the specified port
- *
- * @param port Port to connect to (Port0-Port5)
- * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
- */
- PortOut(PortName port, int mask = 0xFFFFFFFF) {
- port_init(&_port, port, mask, PIN_OUTPUT);
- }
-
- /** Write the value to the output port
- *
- * @param value An integer specifying a bit to write for every corresponding PortOut pin
- */
- void write(int value) {
- port_write(&_port, value);
- }
-
- /** Read the value currently output on the port
- *
- * @returns
- * An integer with each bit corresponding to associated PortOut pin setting
- */
- int read() {
- return port_read(&_port);
- }
-
- /** A shorthand for write()
- */
- PortOut& operator= (int value) {
- write(value);
- return *this;
- }
-
- PortOut& operator= (PortOut& rhs) {
- write(rhs.read());
- return *this;
- }
-
- /** A shorthand for read()
- */
- operator int() {
- return read();
- }
-
-private:
- port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h
deleted file mode 100644
index 9e8c0bdf2..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_H
-#define MBED_PWMOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PWMOUT
-#include "pwmout_api.h"
-
-namespace mbed {
-
-/** A pulse-width modulation digital output
- *
- * Example
- * @code
- * // Fade a led on.
- * #include "mbed.h"
- *
- * PwmOut led(LED1);
- *
- * int main() {
- * while(1) {
- * led = led + 0.01;
- * wait(0.2);
- * if(led == 1.0) {
- * led = 0;
- * }
- * }
- * }
- * @endcode
- *
- * @note
- * On the LPC1768 and LPC2368, the PWMs all share the same
- * period - if you change the period for one, you change it for all.
- * Although routines that change the period maintain the duty cycle
- * for its PWM, all other PWMs will require their duty cycle to be
- * refreshed.
- */
-class PwmOut {
-
-public:
-
- /** Create a PwmOut connected to the specified pin
- *
- * @param pin PwmOut pin to connect to
- */
- PwmOut(PinName pin) {
- pwmout_init(&_pwm, pin);
- }
-
- /** Set the ouput duty-cycle, specified as a percentage (float)
- *
- * @param value A floating-point value representing the output duty-cycle,
- * specified as a percentage. The value should lie between
- * 0.0f (representing on 0%) and 1.0f (representing on 100%).
- * Values outside this range will be saturated to 0.0f or 1.0f.
- */
- void write(float value) {
- pwmout_write(&_pwm, value);
- }
-
- /** Return the current output duty-cycle setting, measured as a percentage (float)
- *
- * @returns
- * A floating-point value representing the current duty-cycle being output on the pin,
- * measured as a percentage. The returned value will lie between
- * 0.0f (representing on 0%) and 1.0f (representing on 100%).
- *
- * @note
- * This value may not match exactly the value set by a previous <write>.
- */
- float read() {
- return pwmout_read(&_pwm);
- }
-
- /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
- *
- * @note
- * The resolution is currently in microseconds; periods smaller than this
- * will be set to zero.
- */
- void period(float seconds) {
- pwmout_period(&_pwm, seconds);
- }
-
- /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
- */
- void period_ms(int ms) {
- pwmout_period_ms(&_pwm, ms);
- }
-
- /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
- */
- void period_us(int us) {
- pwmout_period_us(&_pwm, us);
- }
-
- /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
- */
- void pulsewidth(float seconds) {
- pwmout_pulsewidth(&_pwm, seconds);
- }
-
- /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
- */
- void pulsewidth_ms(int ms) {
- pwmout_pulsewidth_ms(&_pwm, ms);
- }
-
- /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
- */
- void pulsewidth_us(int us) {
- pwmout_pulsewidth_us(&_pwm, us);
- }
-
-#ifdef MBED_OPERATORS
- /** A operator shorthand for write()
- */
- PwmOut& operator= (float value) {
- write(value);
- return *this;
- }
-
- PwmOut& operator= (PwmOut& rhs) {
- write(rhs.read());
- return *this;
- }
-
- /** An operator shorthand for read()
- */
- operator float() {
- return read();
- }
-#endif
-
-protected:
- pwmout_t _pwm;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h
deleted file mode 100644
index a5182bb64..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RAW_SERIAL_H
-#define MBED_RAW_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "SerialBase.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- * This is a variation of the Serial class that doesn't use streams,
- * thus making it safe to use in interrupt handlers with the RTOS.
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * Example:
- * @code
- * // Send a char to the PC
- *
- * #include "mbed.h"
- *
- * RawSerial pc(USBTX, USBRX);
- *
- * int main() {
- * pc.putc('A');
- * }
- * @endcode
- */
-class RawSerial: public SerialBase {
-
-public:
- /** Create a RawSerial port, connected to the specified transmit and receive pins
- *
- * @param tx Transmit pin
- * @param rx Receive pin
- *
- * @note
- * Either tx or rx may be specified as NC if unused
- */
- RawSerial(PinName tx, PinName rx);
-
- /** Write a char to the serial port
- *
- * @param c The char to write
- *
- * @returns The written char or -1 if an error occured
- */
- int putc(int c);
-
- /** Read a char from the serial port
- *
- * @returns The char read from the serial port
- */
- int getc();
-
- /** Write a string to the serial port
- *
- * @param str The string to write
- *
- * @returns 0 if the write succeeds, EOF for error
- */
- int puts(const char *str);
-
- int printf(const char *format, ...);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h
deleted file mode 100644
index 7fa1a6be8..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_H
-#define MBED_SPI_H
-
-#include "platform.h"
-
-#if DEVICE_SPI
-
-#include "spi_api.h"
-
-namespace mbed {
-
-/** A SPI Master, used for communicating with SPI slave devices
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * Most SPI devices will also require Chip Select and Reset signals. These
- * can be controlled using <DigitalOut> pins
- *
- * Example:
- * @code
- * // Send a byte to a SPI slave, and record the response
- *
- * #include "mbed.h"
- *
- * SPI device(p5, p6, p7); // mosi, miso, sclk
- *
- * int main() {
- * int response = device.write(0xFF);
- * }
- * @endcode
- */
-class SPI {
-
-public:
-
- /** Create a SPI master connected to the specified pins
- *
- * Pin Options:
- * (5, 6, 7) or (11, 12, 13)
- *
- * mosi or miso can be specfied as NC if not used
- *
- * @param mosi SPI Master Out, Slave In pin
- * @param miso SPI Master In, Slave Out pin
- * @param sclk SPI Clock pin
- */
- SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused=NC);
-
- /** Configure the data transmission format
- *
- * @param bits Number of bits per SPI frame (4 - 16)
- * @param mode Clock polarity and phase mode (0 - 3)
- *
- * @code
- * mode | POL PHA
- * -----+--------
- * 0 | 0 0
- * 1 | 0 1
- * 2 | 1 0
- * 3 | 1 1
- * @endcode
- */
- void format(int bits, int mode = 0);
-
- /** Set the spi bus clock frequency
- *
- * @param hz SCLK frequency in hz (default = 1MHz)
- */
- void frequency(int hz = 1000000);
-
- /** Write to the SPI Slave and return the response
- *
- * @param value Data to be sent to the SPI slave
- *
- * @returns
- * Response from the SPI slave
- */
- virtual int write(int value);
-
-public:
- virtual ~SPI() {
- }
-
-protected:
- spi_t _spi;
-
- void aquire(void);
- static SPI *_owner;
- int _bits;
- int _mode;
- int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h
deleted file mode 100644
index d06c7e1b4..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPISLAVE_H
-#define MBED_SPISLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_SPISLAVE
-
-#include "spi_api.h"
-
-namespace mbed {
-
-/** A SPI slave, used for communicating with a SPI Master device
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * Example:
- * @code
- * // Reply to a SPI master as slave
- *
- * #include "mbed.h"
- *
- * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
- *
- * int main() {
- * device.reply(0x00); // Prime SPI with first reply
- * while(1) {
- * if(device.receive()) {
- * int v = device.read(); // Read byte from master
- * v = (v + 1) % 0x100; // Add one to it, modulo 256
- * device.reply(v); // Make this the next reply
- * }
- * }
- * }
- * @endcode
- */
-class SPISlave {
-
-public:
-
- /** Create a SPI slave connected to the specified pins
- *
- * Pin Options:
- * (5, 6, 7i, 8) or (11, 12, 13, 14)
- *
- * mosi or miso can be specfied as NC if not used
- *
- * @param mosi SPI Master Out, Slave In pin
- * @param miso SPI Master In, Slave Out pin
- * @param sclk SPI Clock pin
- * @param ssel SPI chip select pin
- * @param name (optional) A string to identify the object
- */
- SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
- /** Configure the data transmission format
- *
- * @param bits Number of bits per SPI frame (4 - 16)
- * @param mode Clock polarity and phase mode (0 - 3)
- *
- * @code
- * mode | POL PHA
- * -----+--------
- * 0 | 0 0
- * 1 | 0 1
- * 2 | 1 0
- * 3 | 1 1
- * @endcode
- */
- void format(int bits, int mode = 0);
-
- /** Set the spi bus clock frequency
- *
- * @param hz SCLK frequency in hz (default = 1MHz)
- */
- void frequency(int hz = 1000000);
-
- /** Polls the SPI to see if data has been received
- *
- * @returns
- * 0 if no data,
- * 1 otherwise
- */
- int receive(void);
-
- /** Retrieve data from receive buffer as slave
- *
- * @returns
- * the data in the receive buffer
- */
- int read(void);
-
- /** Fill the transmission buffer with the value to be written out
- * as slave on the next received message from the master.
- *
- * @param value the data to be transmitted next
- */
- void reply(int value);
-
-protected:
- spi_t _spi;
-
- int _bits;
- int _mode;
- int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h
deleted file mode 100644
index edd762d01..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_H
-#define MBED_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "SerialBase.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * Example:
- * @code
- * // Print "Hello World" to the PC
- *
- * #include "mbed.h"
- *
- * Serial pc(USBTX, USBRX);
- *
- * int main() {
- * pc.printf("Hello World\n");
- * }
- * @endcode
- */
-class Serial : public SerialBase, public Stream {
-
-public:
- /** Create a Serial port, connected to the specified transmit and receive pins
- *
- * @param tx Transmit pin
- * @param rx Receive pin
- *
- * @note
- * Either tx or rx may be specified as NC if unused
- */
- Serial(PinName tx, PinName rx, const char *name=NULL);
-
-protected:
- virtual int _getc();
- virtual int _putc(int c);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h
deleted file mode 100644
index 07bc4b463..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIALBASE_H
-#define MBED_SERIALBASE_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "FunctionPointer.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A base class for serial port implementations
- * Can't be instantiated directly (use Serial or RawSerial)
- */
-class SerialBase {
-
-public:
- /** Set the baud rate of the serial port
- *
- * @param baudrate The baudrate of the serial port (default = 9600).
- */
- void baud(int baudrate);
-
- enum Parity {
- None = 0,
- Odd,
- Even,
- Forced1,
- Forced0
- };
-
- enum IrqType {
- RxIrq = 0,
- TxIrq
- };
-
- enum Flow {
- Disabled = 0,
- RTS,
- CTS,
- RTSCTS
- };
-
- /** Set the transmission format used by the serial port
- *
- * @param bits The number of bits in a word (5-8; default = 8)
- * @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
- * @param stop The number of stop bits (1 or 2; default = 1)
- */
- void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
-
- /** Determine if there is a character available to read
- *
- * @returns
- * 1 if there is a character available to read,
- * 0 otherwise
- */
- int readable();
-
- /** Determine if there is space available to write a character
- *
- * @returns
- * 1 if there is space to write a character,
- * 0 otherwise
- */
- int writeable();
-
- /** Attach a function to call whenever a serial interrupt is generated
- *
- * @param fptr A pointer to a void function, or 0 to set as none
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- */
- void attach(void (*fptr)(void), IrqType type=RxIrq);
-
- /** Attach a member function to call whenever a serial interrupt is generated
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- */
- template<typename T>
- void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
- if((mptr != NULL) && (tptr != NULL)) {
- _irq[type].attach(tptr, mptr);
- serial_irq_set(&_serial, (SerialIrq)type, 1);
- }
- }
-
- /** Generate a break condition on the serial line
- */
- void send_break();
-
-#if DEVICE_SERIAL_FC
- /** Set the flow control type on the serial port
- *
- * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
- * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
- * @param flow2 the second flow control pin (CTS for RTSCTS)
- */
- void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
-#endif
-
- static void _irq_handler(uint32_t id, SerialIrq irq_type);
-
-protected:
- SerialBase(PinName tx, PinName rx);
- virtual ~SerialBase() {
- }
-
- int _base_getc();
- int _base_putc(int c);
-
- serial_t _serial;
- FunctionPointer _irq[2];
- int _baud;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h
deleted file mode 100644
index a57053e67..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_STREAM_H
-#define MBED_STREAM_H
-
-#include "platform.h"
-#include "FileLike.h"
-
-namespace mbed {
-
-extern void mbed_set_unbuffered_stream(FILE *_file);
-extern int mbed_getc(FILE *_file);
-extern char* mbed_gets(char *s, int size, FILE *_file);
-
-class Stream : public FileLike {
-
-public:
- Stream(const char *name=NULL);
- virtual ~Stream();
-
- int putc(int c);
- int puts(const char *s);
- int getc();
- char *gets(char *s, int size);
- int printf(const char* format, ...);
- int scanf(const char* format, ...);
-
- operator std::FILE*() {return _file;}
-
-protected:
- virtual int close();
- virtual ssize_t write(const void* buffer, size_t length);
- virtual ssize_t read(void* buffer, size_t length);
- virtual off_t lseek(off_t offset, int whence);
- virtual int isatty();
- virtual int fsync();
- virtual off_t flen();
-
- virtual int _putc(int c) = 0;
- virtual int _getc() = 0;
-
- std::FILE *_file;
-
- /* disallow copy constructor and assignment operators */
-private:
- Stream(const Stream&);
- Stream & operator = (const Stream&);
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h
deleted file mode 100644
index 43b70cbfc..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_H
-#define MBED_TICKER_H
-
-#include "TimerEvent.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** A Ticker is used to call a function at a recurring interval
- *
- * You can use as many seperate Ticker objects as you require.
- *
- * Example:
- * @code
- * // Toggle the blinking led after 5 seconds
- *
- * #include "mbed.h"
- *
- * Ticker timer;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * int flip = 0;
- *
- * void attime() {
- * flip = !flip;
- * }
- *
- * int main() {
- * timer.attach(&attime, 5);
- * while(1) {
- * if(flip == 0) {
- * led1 = !led1;
- * } else {
- * led2 = !led2;
- * }
- * wait(0.2);
- * }
- * }
- * @endcode
- */
-class Ticker : public TimerEvent {
-
-public:
-
- /** Attach a function to be called by the Ticker, specifiying the interval in seconds
- *
- * @param fptr pointer to the function to be called
- * @param t the time between calls in seconds
- */
- void attach(void (*fptr)(void), float t) {
- attach_us(fptr, t * 1000000.0f);
- }
-
- /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param t the time between calls in seconds
- */
- template<typename T>
- void attach(T* tptr, void (T::*mptr)(void), float t) {
- attach_us(tptr, mptr, t * 1000000.0f);
- }
-
- /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
- *
- * @param fptr pointer to the function to be called
- * @param t the time between calls in micro-seconds
- */
- void attach_us(void (*fptr)(void), timestamp_t t) {
- _function.attach(fptr);
- setup(t);
- }
-
- /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param t the time between calls in micro-seconds
- */
- template<typename T>
- void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {
- _function.attach(tptr, mptr);
- setup(t);
- }
-
- virtual ~Ticker() {
- detach();
- }
-
- /** Detach the function
- */
- void detach();
-
-protected:
- void setup(timestamp_t t);
- virtual void handler();
-
-protected:
- timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
- FunctionPointer _function; /**< Callback. */
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h
deleted file mode 100644
index e145d9a77..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEOUT_H
-#define MBED_TIMEOUT_H
-
-#include "Ticker.h"
-
-namespace mbed {
-
-/** A Timeout is used to call a function at a point in the future
- *
- * You can use as many seperate Timeout objects as you require.
- *
- * Example:
- * @code
- * // Blink until timeout.
- *
- * #include "mbed.h"
- *
- * Timeout timeout;
- * DigitalOut led(LED1);
- *
- * int on = 1;
- *
- * void attimeout() {
- * on = 0;
- * }
- *
- * int main() {
- * timeout.attach(&attimeout, 5);
- * while(on) {
- * led = !led;
- * wait(0.2);
- * }
- * }
- * @endcode
- */
-class Timeout : public Ticker {
-
-protected:
- virtual void handler();
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h
deleted file mode 100644
index aedf0377e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMER_H
-#define MBED_TIMER_H
-
-#include "platform.h"
-
-namespace mbed {
-
-/** A general purpose timer
- *
- * Example:
- * @code
- * // Count the time to toggle a LED
- *
- * #include "mbed.h"
- *
- * Timer timer;
- * DigitalOut led(LED1);
- * int begin, end;
- *
- * int main() {
- * timer.start();
- * begin = timer.read_us();
- * led = !led;
- * end = timer.read_us();
- * printf("Toggle the led takes %d us", end - begin);
- * }
- * @endcode
- */
-class Timer {
-
-public:
- Timer();
-
- /** Start the timer
- */
- void start();
-
- /** Stop the timer
- */
- void stop();
-
- /** Reset the timer to 0.
- *
- * If it was already counting, it will continue
- */
- void reset();
-
- /** Get the time passed in seconds
- */
- float read();
-
- /** Get the time passed in mili-seconds
- */
- int read_ms();
-
- /** Get the time passed in micro-seconds
- */
- int read_us();
-
-#ifdef MBED_OPERATORS
- operator float();
-#endif
-
-protected:
- int slicetime();
- int _running; // whether the timer is running
- unsigned int _start; // the start time of the latest slice
- int _time; // any accumulated time from previous slices
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h
deleted file mode 100644
index 4ec7056a7..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEREVENT_H
-#define MBED_TIMEREVENT_H
-
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-/** Base abstraction for timer interrupts
-*/
-class TimerEvent {
-public:
- TimerEvent();
-
- /** The handler registered with the underlying timer interrupt
- */
- static void irq(uint32_t id);
-
- /** Destruction removes it...
- */
- virtual ~TimerEvent();
-
-protected:
- // The handler called to service the timer event of the derived class
- virtual void handler() = 0;
-
- // insert in to linked list
- void insert(timestamp_t timestamp);
-
- // remove from linked list, if in it
- void remove();
-
- ticker_event_t event;
-};
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h
deleted file mode 100644
index e427250e0..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_HELPER_H
-#define MBED_CAN_HELPER_H
-
-#if DEVICE_CAN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum CANFormat {
- CANStandard = 0,
- CANExtended = 1,
- CANAny = 2
-};
-typedef enum CANFormat CANFormat;
-
-enum CANType {
- CANData = 0,
- CANRemote = 1
-};
-typedef enum CANType CANType;
-
-struct CAN_Message {
- unsigned int id; // 29 bit identifier
- unsigned char data[8]; // Data field
- unsigned char len; // Length of data field in bytes
- CANFormat format; // 0 - STANDARD, 1- EXTENDED IDENTIFIER
- CANType type; // 0 - DATA FRAME, 1 - REMOTE FRAME
-};
-typedef struct CAN_Message CAN_Message;
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif
-
-#endif // MBED_CAN_HELPER_H
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h
deleted file mode 100644
index 51b044d11..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_H
-#define MBED_H
-
-#define MBED_LIBRARY_VERSION 97
-
-#include "platform.h"
-
-// Useful C libraries
-#include <math.h>
-#include <time.h>
-
-// mbed Debug libraries
-#include "mbed_error.h"
-#include "mbed_interface.h"
-
-// mbed Peripheral components
-#include "DigitalIn.h"
-#include "DigitalOut.h"
-#include "DigitalInOut.h"
-#include "BusIn.h"
-#include "BusOut.h"
-#include "BusInOut.h"
-#include "PortIn.h"
-#include "PortInOut.h"
-#include "PortOut.h"
-#include "AnalogIn.h"
-#include "AnalogOut.h"
-#include "PwmOut.h"
-#include "Serial.h"
-#include "SPI.h"
-#include "SPISlave.h"
-#include "I2C.h"
-#include "I2CSlave.h"
-#include "Ethernet.h"
-#include "CAN.h"
-#include "RawSerial.h"
-
-// mbed Internal components
-#include "Timer.h"
-#include "Ticker.h"
-#include "Timeout.h"
-#include "LocalFileSystem.h"
-#include "InterruptIn.h"
-#include "wait_api.h"
-#include "sleep_api.h"
-#include "rtc_time.h"
-
-using namespace mbed;
-using namespace std;
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h
deleted file mode 100644
index 1bcfb092b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ASSERT_H
-#define MBED_ASSERT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
- * This function is active only if NDEBUG is not defined prior to including this
- * assert header file.
- * In case of MBED_ASSERT failing condition, the assertation message is printed
- * to stderr and mbed_die() is called.
- * @param expr Expresion to be checked.
- * @param file File where assertation failed.
- * @param line Failing assertation line number.
- */
-void mbed_assert_internal(const char *expr, const char *file, int line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#ifdef NDEBUG
-#define MBED_ASSERT(expr) ((void)0)
-
-#else
-#define MBED_ASSERT(expr) \
-do { \
- if (!(expr)) { \
- mbed_assert_internal(#expr, __FILE__, __LINE__); \
- } \
-} while (0)
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h
deleted file mode 100644
index 2c8a34673..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEBUG_H
-#define MBED_DEBUG_H
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#include <stdarg.h>
-
-/** Output a debug message
- *
- * @param format printf-style format string, followed by variables
- */
-static inline void debug(const char *format, ...) {
- va_list args;
- va_start(args, format);
- vfprintf(stderr, format, args);
- va_end(args);
-}
-
-/** Conditionally output a debug message
- *
- * NOTE: If the condition is constant false (!= 1) and the compiler optimization
- * level is greater than 0, then the whole function will be compiled away.
- *
- * @param condition output only if condition is true (== 1)
- * @param format printf-style format string, followed by variables
- */
-static inline void debug_if(int condition, const char *format, ...) {
- if (condition == 1) {
- va_list args;
- va_start(args, format);
- vfprintf(stderr, format, args);
- va_end(args);
- }
-}
-
-#else
-static inline void debug(const char *format, ...) {}
-static inline void debug_if(int condition, const char *format, ...) {}
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h
deleted file mode 100644
index 3a403586d..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ERROR_H
-#define MBED_ERROR_H
-
-/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
- *
- * @code
- * #error "That shouldn't have happened!"
- * @endcode
- *
- * If the compiler evaluates this line, it will report the error and stop the compile.
- *
- * For example, you could use this to check some user-defined compile-time variables:
- *
- * @code
- * #define NUM_PORTS 7
- * #if (NUM_PORTS > 4)
- * #error "NUM_PORTS must be less than 4"
- * #endif
- * @endcode
- *
- * Reporting Run-Time Errors:
- * To generate a fatal run-time error, you can use the mbed error() function.
- *
- * @code
- * error("That shouldn't have happened!");
- * @endcode
- *
- * If the mbed running the program executes this function, it will print the
- * message via the USB serial port, and then die with the blue lights of death!
- *
- * The message can use printf-style formatting, so you can report variables in the
- * message too. For example, you could use this to check a run-time condition:
- *
- * @code
- * if(x >= 5) {
- * error("expected x to be less than 5, but got %d", x);
- * }
- * #endcode
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void error(const char* format, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h
deleted file mode 100644
index a93a4d33d..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERFACE_H
-#define MBED_INTERFACE_H
-
-#include "device.h"
-
-/* Mbed interface mac address
- * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
- * otherwise MAC_ADD_x are used.
- */
-#define MBED_MAC_ADDR_INTERFACE 0x00
-#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-/** Functions to control the mbed interface
- *
- * mbed Microcontrollers have a built-in interface to provide functionality such as
- * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
- * system. These functions provide means to control the interface suing semihost
- * calls it supports.
- */
-
-/** Determine whether the mbed interface is connected, based on whether debug is enabled
- *
- * @returns
- * 1 if interface is connected,
- * 0 otherwise
- */
-int mbed_interface_connected(void);
-
-/** Instruct the mbed interface to reset, as if the reset button had been pressed
- *
- * @returns
- * 1 if successful,
- * 0 otherwise (e.g. interface not present)
- */
-int mbed_interface_reset(void);
-
-/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
- * The interface will still support the USB serial aspect
- *
- * @returns
- * 0 if successful,
- * -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_disconnect(void);
-
-/** This will disconnect the debug aspect of the interface, and if the USB cable is not
- * connected, also power down the interface. If the USB cable is connected, the interface
- * will remain powered up and visible to the host
- *
- * @returns
- * 0 if successful,
- * -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_powerdown(void);
-
-/** This returns a string containing the 32-character UID of the mbed interface
- * This is a weak function that can be overwritten if required
- *
- * @param uid A 33-byte array to write the null terminated 32-byte string
- *
- * @returns
- * 0 if successful,
- * -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_uid(char *uid);
-
-#endif
-
-/** This returns a unique 6-byte MAC address, based on the interface UID
- * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
- *
- * This is a weak function that can be overwritten if you want to provide your own mechanism to
- * provide a MAC address.
- *
- * @param mac A 6-byte array to write the MAC address
- */
-void mbed_mac_address(char *mac);
-
-/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
- */
-void mbed_die(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h
deleted file mode 100644
index 85e44e57b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PLATFORM_H
-#define MBED_PLATFORM_H
-
-#define MBED_OPERATORS 1
-
-#include "device.h"
-#include "PinNames.h"
-#include "PeripheralNames.h"
-
-#include <cstddef>
-#include <cstdlib>
-#include <cstdio>
-#include <cstring>
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h
deleted file mode 100644
index 565897366..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Implementation of the C time.h functions
- *
- * Provides mechanisms to set and read the current time, based
- * on the microcontroller Real-Time Clock (RTC), plus some
- * standard C manipulation and formating functions.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37
- *
- * while(1) {
- * time_t seconds = time(NULL);
- *
- * printf("Time as seconds since January 1, 1970 = %d\n", seconds);
- *
- * printf("Time as a basic string = %s", ctime(&seconds));
- *
- * char buffer[32];
- * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
- * printf("Time as a custom formatted string = %s", buffer);
- *
- * wait(1);
- * }
- * }
- * @endcode
- */
-
-/** Set the current time
- *
- * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
- * to the time represented by the number of seconds since January 1, 1970
- * (the UNIX timestamp).
- *
- * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
- * }
- * @endcode
- */
-void set_time(time_t t);
-
-/** Attach an external RTC to be used for the C time functions
- *
- * Do not call this function from an interrupt while an RTC read/write operation may be occurring
- *
- * @param read_rtc pointer to function which returns current UNIX timestamp
- * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
- * @param init_rtc pointer to funtion which initializes RTC, can be NULL
- * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
- */
-void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h
deleted file mode 100644
index 279f67160..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SEMIHOST_H
-#define MBED_SEMIHOST_H
-
-#include "device.h"
-#include "toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-#ifndef __CC_ARM
-
-#if defined(__ICCARM__)
-inline int __semihost(int reason, const void *arg) {
- return __semihosting(reason, (void*)arg);
-}
-#else
-
-#ifdef __thumb__
-# define AngelSWI 0xAB
-# define AngelSWIInsn "bkpt"
-# define AngelSWIAsm bkpt
-#else
-# define AngelSWI 0x123456
-# define AngelSWIInsn "swi"
-# define AngelSWIAsm swi
-#endif
-
-static inline int __semihost(int reason, const void *arg) {
- int value;
-
- asm volatile (
- "mov r0, %1" "\n\t"
- "mov r1, %2" "\n\t"
- AngelSWIInsn " %a3" "\n\t"
- "mov %0, r0"
- : "=r" (value) /* output operands */
- : "r" (reason), "r" (arg), "i" (AngelSWI) /* input operands */
- : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */
- );
-
- return value;
-}
-#endif
-#endif
-
-#if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char* name, int openmode);
-int semihost_close (FILEHANDLE fh);
-int semihost_read (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
-int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
-int semihost_ensure(FILEHANDLE fh);
-long semihost_flen (FILEHANDLE fh);
-int semihost_seek (FILEHANDLE fh, long position);
-int semihost_istty (FILEHANDLE fh);
-
-int semihost_remove(const char *name);
-int semihost_rename(const char *old_name, const char *new_name);
-#endif
-
-int semihost_uid(char *uid);
-int semihost_reset(void);
-int semihost_vbus(void);
-int semihost_powerdown(void);
-int semihost_exit(void);
-
-int semihost_connected(void);
-int semihost_disabledebug(void);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h
deleted file mode 100644
index b140643b3..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TOOLCHAIN_H
-#define MBED_TOOLCHAIN_H
-
-#if defined(TOOLCHAIN_ARM)
-#include <rt_sys.h>
-#endif
-
-#ifndef FILEHANDLE
-typedef int FILEHANDLE;
-#endif
-
-#if defined (__ICCARM__)
-# define WEAK __weak
-# define PACKED __packed
-#else
-# define WEAK __attribute__((weak))
-# define PACKED __attribute__((packed))
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h
deleted file mode 100644
index 03c27141e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_WAIT_API_H
-#define MBED_WAIT_API_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Generic wait functions.
- *
- * These provide simple NOP type wait capabilities.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * DigitalOut heartbeat(LED1);
- *
- * int main() {
- * while (1) {
- * heartbeat = 1;
- * wait(0.5);
- * heartbeat = 0;
- * wait(0.5);
- * }
- * }
- */
-
-/** Waits for a number of seconds, with microsecond resolution (within
- * the accuracy of single precision floating point).
- *
- * @param s number of seconds to wait
- */
-void wait(float s);
-
-/** Waits a number of milliseconds.
- *
- * @param ms the whole number of milliseconds to wait
- */
-void wait_ms(int ms);
-
-/** Waits a number of microseconds.
- *
- * @param us the whole number of microseconds to wait
- */
-void wait_us(int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp
deleted file mode 100644
index ea67cbcb8..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp
+++ /dev/null
@@ -1,82 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusIn.h"
-#include "mbed_assert.h"
-
-namespace mbed {
-
-BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
- PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
- _nc_mask = 0;
- for (int i=0; i<16; i++) {
- _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
- if (pins[i] != NC) {
- _nc_mask |= (1 << i);
- }
- }
-}
-
-BusIn::BusIn(PinName pins[16]) {
- _nc_mask = 0;
- for (int i=0; i<16; i++) {
- _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
- if (pins[i] != NC) {
- _nc_mask |= (1 << i);
- }
- }
-}
-
-BusIn::~BusIn() {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- delete _pin[i];
- }
- }
-}
-
-int BusIn::read() {
- int v = 0;
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- v |= _pin[i]->read() << i;
- }
- }
- return v;
-}
-
-void BusIn::mode(PinMode pull) {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- _pin[i]->mode(pull);
- }
- }
-}
-
-#ifdef MBED_OPERATORS
-BusIn::operator int() {
- return read();
-}
-
-DigitalIn& BusIn::operator[] (int index) {
- MBED_ASSERT(index >= 0 && index <= 16);
- MBED_ASSERT(_pin[index]);
- return *_pin[index];
-}
-
-#endif
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp
deleted file mode 100644
index 5575f90d4..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp
+++ /dev/null
@@ -1,115 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusInOut.h"
-#include "mbed_assert.h"
-
-namespace mbed {
-
-BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
- PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
- _nc_mask = 0;
- for (int i=0; i<16; i++) {
- _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
- if (pins[i] != NC) {
- _nc_mask |= (1 << i);
- }
- }
-}
-
-BusInOut::BusInOut(PinName pins[16]) {
- _nc_mask = 0;
- for (int i=0; i<16; i++) {
- _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
- if (pins[i] != NC) {
- _nc_mask |= (1 << i);
- }
- }
-}
-
-BusInOut::~BusInOut() {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- delete _pin[i];
- }
- }
-}
-
-void BusInOut::write(int value) {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- _pin[i]->write((value >> i) & 1);
- }
- }
-}
-
-int BusInOut::read() {
- int v = 0;
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- v |= _pin[i]->read() << i;
- }
- }
- return v;
-}
-
-void BusInOut::output() {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- _pin[i]->output();
- }
- }
-}
-
-void BusInOut::input() {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- _pin[i]->input();
- }
- }
-}
-
-void BusInOut::mode(PinMode pull) {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- _pin[i]->mode(pull);
- }
- }
-}
-
-#ifdef MBED_OPERATORS
-BusInOut& BusInOut::operator= (int v) {
- write(v);
- return *this;
-}
-
-BusInOut& BusInOut::operator= (BusInOut& rhs) {
- write(rhs.read());
- return *this;
-}
-
-DigitalInOut& BusInOut::operator[] (int index) {
- MBED_ASSERT(index >= 0 && index <= 16);
- MBED_ASSERT(_pin[index]);
- return *_pin[index];
-}
-
-BusInOut::operator int() {
- return read();
-}
-#endif
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp
deleted file mode 100644
index 4277c5727..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp
+++ /dev/null
@@ -1,91 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusOut.h"
-#include "mbed_assert.h"
-
-namespace mbed {
-
-BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
- PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
- _nc_mask = 0;
- for (int i=0; i<16; i++) {
- _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
- if (pins[i] != NC) {
- _nc_mask |= (1 << i);
- }
- }
-}
-
-BusOut::BusOut(PinName pins[16]) {
- _nc_mask = 0;
- for (int i=0; i<16; i++) {
- _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
- if (pins[i] != NC) {
- _nc_mask |= (1 << i);
- }
- }
-}
-
-BusOut::~BusOut() {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- delete _pin[i];
- }
- }
-}
-
-void BusOut::write(int value) {
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- _pin[i]->write((value >> i) & 1);
- }
- }
-}
-
-int BusOut::read() {
- int v = 0;
- for (int i=0; i<16; i++) {
- if (_pin[i] != 0) {
- v |= _pin[i]->read() << i;
- }
- }
- return v;
-}
-
-#ifdef MBED_OPERATORS
-BusOut& BusOut::operator= (int v) {
- write(v);
- return *this;
-}
-
-BusOut& BusOut::operator= (BusOut& rhs) {
- write(rhs.read());
- return *this;
-}
-
-DigitalOut& BusOut::operator[] (int index) {
- MBED_ASSERT(index >= 0 && index <= 16);
- MBED_ASSERT(_pin[index]);
- return *_pin[index];
-}
-
-BusOut::operator int() {
- return read();
-}
-#endif
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp
deleted file mode 100644
index 407e00bf1..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp
+++ /dev/null
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "CAN.h"
-
-#if DEVICE_CAN
-
-#include "cmsis.h"
-
-namespace mbed {
-
-CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
- can_init(&_can, rd, td);
- can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
-}
-
-CAN::~CAN() {
- can_irq_free(&_can);
- can_free(&_can);
-}
-
-int CAN::frequency(int f) {
- return can_frequency(&_can, f);
-}
-
-int CAN::write(CANMessage msg) {
- return can_write(&_can, msg, 0);
-}
-
-int CAN::read(CANMessage &msg, int handle) {
- return can_read(&_can, &msg, handle);
-}
-
-void CAN::reset() {
- can_reset(&_can);
-}
-
-unsigned char CAN::rderror() {
- return can_rderror(&_can);
-}
-
-unsigned char CAN::tderror() {
- return can_tderror(&_can);
-}
-
-void CAN::monitor(bool silent) {
- can_monitor(&_can, (silent) ? 1 : 0);
-}
-
-int CAN::mode(Mode mode) {
- return can_mode(&_can, (CanMode)mode);
-}
-
-int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
- return can_filter(&_can, id, mask, format, handle);
-}
-
-void CAN::attach(void (*fptr)(void), IrqType type) {
- if (fptr) {
- _irq[(CanIrqType)type].attach(fptr);
- can_irq_set(&_can, (CanIrqType)type, 1);
- } else {
- can_irq_set(&_can, (CanIrqType)type, 0);
- }
-}
-
-void CAN::_irq_handler(uint32_t id, CanIrqType type) {
- CAN *handler = (CAN*)id;
- handler->_irq[type].call();
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp
deleted file mode 100644
index e95090305..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp
+++ /dev/null
@@ -1,90 +0,0 @@
-#include "CallChain.h"
-#include "cmsis.h"
-
-namespace mbed {
-
-CallChain::CallChain(int size) : _chain(), _size(size), _elements(0) {
- _chain = new pFunctionPointer_t[size]();
-}
-
-CallChain::~CallChain() {
- clear();
- delete _chain;
-}
-
-pFunctionPointer_t CallChain::add(void (*function)(void)) {
- return common_add(new FunctionPointer(function));
-}
-
-pFunctionPointer_t CallChain::add_front(void (*function)(void)) {
- return common_add_front(new FunctionPointer(function));
-}
-
-int CallChain::size() const {
- return _elements;
-}
-
-pFunctionPointer_t CallChain::get(int i) const {
- if (i < 0 || i >= _elements)
- return NULL;
- return _chain[i];
-}
-
-int CallChain::find(pFunctionPointer_t f) const {
- for (int i = 0; i < _elements; i++)
- if (f == _chain[i])
- return i;
- return -1;
-}
-
-void CallChain::clear() {
- for(int i = 0; i < _elements; i ++) {
- delete _chain[i];
- _chain[i] = NULL;
- }
- _elements = 0;
-}
-
-bool CallChain::remove(pFunctionPointer_t f) {
- int i;
-
- if ((i = find(f)) == -1)
- return false;
- if (i != _elements - 1)
- memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t));
- delete f;
- _elements --;
- return true;
-}
-
-void CallChain::call() {
- for(int i = 0; i < _elements; i++)
- _chain[i]->call();
-}
-
-void CallChain::_check_size() {
- if (_elements < _size)
- return;
- _size = (_size < 4) ? 4 : _size + 4;
- pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size]();
- memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t));
- delete _chain;
- _chain = new_chain;
-}
-
-pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) {
- _check_size();
- _chain[_elements] = pf;
- _elements ++;
- return pf;
-}
-
-pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) {
- _check_size();
- memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t));
- _chain[0] = pf;
- _elements ++;
- return pf;
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp
deleted file mode 100644
index 279a88b8f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp
+++ /dev/null
@@ -1,73 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Ethernet.h"
-
-#if DEVICE_ETHERNET
-
-#include "ethernet_api.h"
-
-namespace mbed {
-
-Ethernet::Ethernet() {
- ethernet_init();
-}
-
-Ethernet::~Ethernet() {
- ethernet_free();
-}
-
-int Ethernet::write(const char *data, int size) {
- return ethernet_write(data, size);
-}
-
-int Ethernet::send() {
- return ethernet_send();
-}
-
-int Ethernet::receive() {
- return ethernet_receive();
-}
-
-int Ethernet::read(char *data, int size) {
- return ethernet_read(data, size);
-}
-
-void Ethernet::address(char *mac) {
- return ethernet_address(mac);
-}
-
-int Ethernet::link() {
- return ethernet_link();
-}
-
-void Ethernet::set_link(Mode mode) {
- int speed = -1;
- int duplex = 0;
-
- switch(mode) {
- case AutoNegotiate : speed = -1; duplex = 0; break;
- case HalfDuplex10 : speed = 0; duplex = 0; break;
- case FullDuplex10 : speed = 0; duplex = 1; break;
- case HalfDuplex100 : speed = 1; duplex = 0; break;
- case FullDuplex100 : speed = 1; duplex = 1; break;
- }
-
- ethernet_set_link(speed, duplex);
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp
deleted file mode 100644
index fce113d88..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp
+++ /dev/null
@@ -1,82 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileBase.h"
-
-namespace mbed {
-
-FileBase *FileBase::_head = NULL;
-
-FileBase::FileBase(const char *name, PathType t) : _next(NULL),
- _name(name),
- _path_type(t) {
- if (name != NULL) {
- // put this object at head of the list
- _next = _head;
- _head = this;
- } else {
- _next = NULL;
- }
-}
-
-FileBase::~FileBase() {
- if (_name != NULL) {
- // remove this object from the list
- if (_head == this) { // first in the list, so just drop me
- _head = _next;
- } else { // find the object before me, then drop me
- FileBase *p = _head;
- while (p->_next != this) {
- p = p->_next;
- }
- p->_next = _next;
- }
- }
-}
-
-FileBase *FileBase::lookup(const char *name, unsigned int len) {
- FileBase *p = _head;
- while (p != NULL) {
- /* Check that p->_name matches name and is the correct length */
- if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
- return p;
- }
- p = p->_next;
- }
- return NULL;
-}
-
-FileBase *FileBase::get(int n) {
- FileBase *p = _head;
- int m = 0;
- while (p != NULL) {
- if (m == n) return p;
-
- m++;
- p = p->_next;
- }
- return NULL;
-}
-
-const char* FileBase::getName(void) {
- return _name;
-}
-
-PathType FileBase::getPathType(void) {
- return _path_type;
-}
-
-} // namespace mbed
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp
deleted file mode 100644
index da13ead14..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp
+++ /dev/null
@@ -1,28 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileLike.h"
-
-namespace mbed {
-
-FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
-
-}
-
-FileLike::~FileLike() {
-
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp
deleted file mode 100644
index 09147a269..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp
+++ /dev/null
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FilePath.h"
-
-namespace mbed {
-
-FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
- if ((file_path[0] != '/') || (file_path[1] == 0)) return;
-
- const char* file_system = &file_path[1];
- file_name = file_system;
- int len = 0;
- while (true) {
- char c = *file_name;
- if (c == '/') { // end of object name
- file_name++; // point to one char after the '/'
- break;
- }
- if (c == 0) { // end of object name, with no filename
- break;
- }
- len++;
- file_name++;
- }
-
- fb = FileBase::lookup(file_system, len);
-}
-
-const char* FilePath::fileName(void) {
- return file_name;
-}
-
-bool FilePath::isFileSystem(void) {
- if (NULL == fb)
- return false;
- return (fb->getPathType() == FileSystemPathType);
-}
-
-FileSystemLike* FilePath::fileSystem(void) {
- if (isFileSystem()) {
- return (FileSystemLike*)fb;
- }
- return NULL;
-}
-
-bool FilePath::isFile(void) {
- if (NULL == fb)
- return false;
- return (fb->getPathType() == FilePathType);
-}
-
-FileLike* FilePath::file(void) {
- if (isFile()) {
- return (FileLike*)fb;
- }
- return NULL;
-}
-
-bool FilePath::exists(void) {
- return fb != NULL;
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp
deleted file mode 100644
index df5d86da8..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp
+++ /dev/null
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileSystemLike.h"
-
-namespace mbed {
-
-class BaseDirHandle : public DirHandle {
-public:
- /*
- We keep track of our current location as the n'th object in the
- FileSystemLike list. Using a Base* instead would cause problems if that
- object were to be destroyed between readdirs.
- Using this method does mean though that destroying/creating objects can
- give unusual results from readdir.
- */
- off_t n;
- struct dirent cur_entry;
-
- BaseDirHandle() : n(0), cur_entry() {
- }
-
- virtual int closedir() {
- delete this;
- return 0;
- }
-
- virtual struct dirent *readdir() {
- FileBase *ptr = FileBase::get(n);
- if (ptr == NULL) return NULL;
-
- /* Increment n, so next readdir gets the next item */
- n++;
-
- /* Setup cur entry and return a pointer to it */
- std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
- return &cur_entry;
- }
-
- virtual off_t telldir() {
- return n;
- }
-
- virtual void seekdir(off_t offset) {
- n = offset;
- }
-
- virtual void rewinddir() {
- n = 0;
- }
-};
-
-FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
-
-}
-
-FileSystemLike::~FileSystemLike() {
-
-}
-
-DirHandle *FileSystemLike::opendir() {
- return new BaseDirHandle();
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp
deleted file mode 100644
index 7c43916c7..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp
+++ /dev/null
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-FunctionPointer::FunctionPointer(void (*function)(void)): _function(),
- _object(),
- _membercaller() {
- attach(function);
-}
-
-void FunctionPointer::attach(void (*function)(void)) {
- _function = function;
- _object = 0;
-}
-
-void FunctionPointer::call(void) {
- if (_function) {
- _function();
- } else if (_object) {
- _membercaller(_object, _member);
- }
-}
-
-#ifdef MBED_OPERATORS
-void FunctionPointer::operator ()(void) {
- call();
-}
-#endif
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp
deleted file mode 100644
index fb1d03048..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp
+++ /dev/null
@@ -1,91 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "I2C.h"
-
-#if DEVICE_I2C
-
-namespace mbed {
-
-I2C *I2C::_owner = NULL;
-
-I2C::I2C(PinName sda, PinName scl) : _i2c(), _hz(100000) {
- // The init function also set the frequency to 100000
- i2c_init(&_i2c, sda, scl);
-
- // Used to avoid unnecessary frequency updates
- _owner = this;
-}
-
-void I2C::frequency(int hz) {
- _hz = hz;
-
- // We want to update the frequency even if we are already the bus owners
- i2c_frequency(&_i2c, _hz);
-
- // Updating the frequency of the bus we become the owners of it
- _owner = this;
-}
-
-void I2C::aquire() {
- if (_owner != this) {
- i2c_frequency(&_i2c, _hz);
- _owner = this;
- }
-}
-
-// write - Master Transmitter Mode
-int I2C::write(int address, const char* data, int length, bool repeated) {
- aquire();
-
- int stop = (repeated) ? 0 : 1;
- int written = i2c_write(&_i2c, address, data, length, stop);
-
- return length != written;
-}
-
-int I2C::write(int data) {
- return i2c_byte_write(&_i2c, data);
-}
-
-// read - Master Reciever Mode
-int I2C::read(int address, char* data, int length, bool repeated) {
- aquire();
-
- int stop = (repeated) ? 0 : 1;
- int read = i2c_read(&_i2c, address, data, length, stop);
-
- return length != read;
-}
-
-int I2C::read(int ack) {
- if (ack) {
- return i2c_byte_read(&_i2c, 0);
- } else {
- return i2c_byte_read(&_i2c, 1);
- }
-}
-
-void I2C::start(void) {
- i2c_start(&_i2c);
-}
-
-void I2C::stop(void) {
- i2c_stop(&_i2c);
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp
deleted file mode 100644
index 43940939c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp
+++ /dev/null
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "I2CSlave.h"
-
-#if DEVICE_I2CSLAVE
-
-namespace mbed {
-
-I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
- i2c_init(&_i2c, sda, scl);
- i2c_frequency(&_i2c, 100000);
- i2c_slave_mode(&_i2c, 1);
-}
-
-void I2CSlave::frequency(int hz) {
- i2c_frequency(&_i2c, hz);
-}
-
-void I2CSlave::address(int address) {
- int addr = (address & 0xFF) | 1;
- i2c_slave_address(&_i2c, 0, addr, 0);
-}
-
-int I2CSlave::receive(void) {
- return i2c_slave_receive(&_i2c);
-}
-
-int I2CSlave::read(char *data, int length) {
- return i2c_slave_read(&_i2c, data, length) != length;
-}
-
-int I2CSlave::read(void) {
- return i2c_byte_read(&_i2c, 0);
-}
-
-int I2CSlave::write(const char *data, int length) {
- return i2c_slave_write(&_i2c, data, length) != length;
-}
-
-int I2CSlave::write(int data) {
- return i2c_byte_write(&_i2c, data);
-}
-
-void I2CSlave::stop(void) {
- i2c_stop(&_i2c);
-}
-
-}
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp
deleted file mode 100644
index 8692124c1..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp
+++ /dev/null
@@ -1,85 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "InterruptIn.h"
-
-#if DEVICE_INTERRUPTIN
-
-namespace mbed {
-
-InterruptIn::InterruptIn(PinName pin) : gpio(),
- gpio_irq(),
- _rise(),
- _fall() {
- gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
- gpio_init_in(&gpio, pin);
-}
-
-InterruptIn::~InterruptIn() {
- gpio_irq_free(&gpio_irq);
-}
-
-int InterruptIn::read() {
- return gpio_read(&gpio);
-}
-
-void InterruptIn::mode(PinMode pull) {
- gpio_mode(&gpio, pull);
-}
-
-void InterruptIn::rise(void (*fptr)(void)) {
- if (fptr) {
- _rise.attach(fptr);
- gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
- } else {
- gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
- }
-}
-
-void InterruptIn::fall(void (*fptr)(void)) {
- if (fptr) {
- _fall.attach(fptr);
- gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
- } else {
- gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
- }
-}
-
-void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
- InterruptIn *handler = (InterruptIn*)id;
- switch (event) {
- case IRQ_RISE: handler->_rise.call(); break;
- case IRQ_FALL: handler->_fall.call(); break;
- case IRQ_NONE: break;
- }
-}
-
-void InterruptIn::enable_irq() {
- gpio_irq_enable(&gpio_irq);
-}
-
-void InterruptIn::disable_irq() {
- gpio_irq_disable(&gpio_irq);
-}
-
-#ifdef MBED_OPERATORS
-InterruptIn::operator int() {
- return read();
-}
-#endif
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp
deleted file mode 100644
index e92fb68d4..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp
+++ /dev/null
@@ -1,93 +0,0 @@
-#include "cmsis.h"
-#if defined(NVIC_NUM_VECTORS)
-
-#include "InterruptManager.h"
-#include <string.h>
-
-#define CHAIN_INITIAL_SIZE 4
-
-namespace mbed {
-
-typedef void (*pvoidf)(void);
-
-InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
-
-InterruptManager* InterruptManager::get() {
- if (NULL == _instance)
- _instance = new InterruptManager();
- return _instance;
-}
-
-InterruptManager::InterruptManager() {
- memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
-}
-
-void InterruptManager::destroy() {
- // Not a good idea to call this unless NO interrupt at all
- // is under the control of the handler; otherwise, a system crash
- // is very likely to occur
- if (NULL != _instance) {
- delete _instance;
- _instance = (InterruptManager*)NULL;
- }
-}
-
-InterruptManager::~InterruptManager() {
- for(int i = 0; i < NVIC_NUM_VECTORS; i++)
- if (NULL != _chains[i])
- delete _chains[i];
-}
-
-bool InterruptManager::must_replace_vector(IRQn_Type irq) {
- int irq_pos = get_irq_index(irq);
-
- if (NULL == _chains[irq_pos]) {
- _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
- _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
- return true;
- }
- return false;
-}
-
-pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
- int irq_pos = get_irq_index(irq);
- bool change = must_replace_vector(irq);
-
- pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
- if (change)
- NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
- return pf;
-}
-
-bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
- int irq_pos = get_irq_index(irq);
-
- if (NULL == _chains[irq_pos])
- return false;
- if (!_chains[irq_pos]->remove(handler))
- return false;
- // If there's a single function left in the chain, swith the interrupt vector
- // to call that function directly. This way we save both time and space.
- if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) {
- NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function());
- delete _chains[irq_pos];
- _chains[irq_pos] = (CallChain*) NULL;
- }
- return true;
-}
-
-void InterruptManager::irq_helper() {
- _chains[__get_IPSR()]->call();
-}
-
-int InterruptManager::get_irq_index(IRQn_Type irq) {
- return (int)irq + NVIC_USER_IRQ_OFFSET;
-}
-
-void InterruptManager::static_irq_helper() {
- InterruptManager::get()->irq_helper();
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp
deleted file mode 100644
index 9505d91a9..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp
+++ /dev/null
@@ -1,223 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "LocalFileSystem.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "semihost_api.h"
-#include <string.h>
-#include <stdio.h>
-
-namespace mbed {
-
-/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
-typedef struct {
- unsigned char hr; /* Hours [0..23] */
- unsigned char min; /* Minutes [0..59] */
- unsigned char sec; /* Seconds [0..59] */
- unsigned char day; /* Day [1..31] */
- unsigned char mon; /* Month [1..12] */
- unsigned short year; /* Year [1980..2107] */
-} FTIME;
-
-typedef struct { /* File Search info record */
- char name[32]; /* File name */
- long size; /* File size in bytes */
- int fileID; /* System File Identification */
- FTIME create_time; /* Date & time file was created */
- FTIME write_time; /* Date & time of last write */
-} XFINFO;
-
-#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
-#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
-
-static int xffind (const char *pattern, XFINFO *info) {
- unsigned param[4];
-
- param[0] = (unsigned long)pattern;
- param[1] = (unsigned long)strlen(pattern);
- param[2] = (unsigned long)info;
- param[3] = (unsigned long)sizeof(XFINFO);
-
- return __semihost(USR_XFFIND, param);
-}
-
-#define OPEN_R 0
-#define OPEN_B 1
-#define OPEN_PLUS 2
-#define OPEN_W 4
-#define OPEN_A 8
-#define OPEN_INVALID -1
-
-int posix_to_semihost_open_flags(int flags) {
- /* POSIX flags -> semihosting open mode */
- int openmode;
- if (flags & O_RDWR) {
- /* a plus mode */
- openmode = OPEN_PLUS;
- if (flags & O_APPEND) {
- openmode |= OPEN_A;
- } else if (flags & O_TRUNC) {
- openmode |= OPEN_W;
- } else {
- openmode |= OPEN_R;
- }
- } else if (flags & O_WRONLY) {
- /* write or append */
- if (flags & O_APPEND) {
- openmode = OPEN_A;
- } else {
- openmode = OPEN_W;
- }
- } else if (flags == O_RDONLY) {
- /* read mode */
- openmode = OPEN_R;
- } else {
- /* invalid flags */
- openmode = OPEN_INVALID;
- }
-
- return openmode;
-}
-
-FILEHANDLE local_file_open(const char* name, int flags) {
- int openmode = posix_to_semihost_open_flags(flags);
- if (openmode == OPEN_INVALID) {
- return (FILEHANDLE)NULL;
- }
-
- FILEHANDLE fh = semihost_open(name, openmode);
- if (fh == -1) {
- return (FILEHANDLE)NULL;
- }
-
- return fh;
-}
-
-LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
-}
-
-int LocalFileHandle::close() {
- int retval = semihost_close(_fh);
- delete this;
- return retval;
-}
-
-ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
- ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
- n = length - n; // number of characters written
- pos += n;
- return n;
-}
-
-ssize_t LocalFileHandle::read(void *buffer, size_t length) {
- ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
- n = length - n; // number of characters read
- pos += n;
- return n;
-}
-
-int LocalFileHandle::isatty() {
- return semihost_istty(_fh);
-}
-
-off_t LocalFileHandle::lseek(off_t position, int whence) {
- if (whence == SEEK_CUR) {
- position += pos;
- } else if (whence == SEEK_END) {
- position += semihost_flen(_fh);
- } /* otherwise SEEK_SET, so position is fine */
-
- /* Always seems to return -1, so just ignore for now. */
- semihost_seek(_fh, position);
- pos = position;
- return position;
-}
-
-int LocalFileHandle::fsync() {
- return semihost_ensure(_fh);
-}
-
-off_t LocalFileHandle::flen() {
- return semihost_flen(_fh);
-}
-
-class LocalDirHandle : public DirHandle {
-
-public:
- struct dirent cur_entry;
- XFINFO info;
-
- LocalDirHandle() : cur_entry(), info() {
- }
-
- virtual int closedir() {
- delete this;
- return 0;
- }
-
- virtual struct dirent *readdir() {
- if (xffind("*", &info)!=0) {
- return NULL;
- }
- memcpy(cur_entry.d_name, info.name, sizeof(info.name));
- return &cur_entry;
- }
-
- virtual void rewinddir() {
- info.fileID = 0;
- }
-
- virtual off_t telldir() {
- return info.fileID;
- }
-
- virtual void seekdir(off_t offset) {
- info.fileID = offset;
- }
-};
-
-FileHandle *LocalFileSystem::open(const char* name, int flags) {
- /* reject filenames with / in them */
- for (const char *tmp = name; *tmp; tmp++) {
- if (*tmp == '/') {
- return NULL;
- }
- }
-
- int openmode = posix_to_semihost_open_flags(flags);
- if (openmode == OPEN_INVALID) {
- return NULL;
- }
-
- FILEHANDLE fh = semihost_open(name, openmode);
- if (fh == -1) {
- return NULL;
- }
- return new LocalFileHandle(fh);
-}
-
-int LocalFileSystem::remove(const char *filename) {
- return semihost_remove(filename);
-}
-
-DirHandle *LocalFileSystem::opendir(const char *name) {
- return new LocalDirHandle();
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp
deleted file mode 100644
index dc5db7a3f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp
+++ /dev/null
@@ -1,67 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "RawSerial.h"
-#include "wait_api.h"
-#include <cstdarg>
-
-#if DEVICE_SERIAL
-
-#define STRING_STACK_LIMIT 120
-
-namespace mbed {
-
-RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
-}
-
-int RawSerial::getc() {
- return _base_getc();
-}
-
-int RawSerial::putc(int c) {
- return _base_putc(c);
-}
-
-int RawSerial::puts(const char *str) {
- while (*str)
- putc(*str ++);
- return 0;
-}
-
-// Experimental support for printf in RawSerial. No Stream inheritance
-// means we can't call printf() directly, so we use sprintf() instead.
-// We only call malloc() for the sprintf() buffer if the buffer
-// length is above a certain threshold, otherwise we use just the stack.
-int RawSerial::printf(const char *format, ...) {
- std::va_list arg;
- va_start(arg, format);
- int len = vsnprintf(NULL, 0, format, arg);
- if (len < STRING_STACK_LIMIT) {
- char temp[STRING_STACK_LIMIT];
- vsprintf(temp, format, arg);
- puts(temp);
- } else {
- char *temp = new char[len + 1];
- vsprintf(temp, format, arg);
- puts(temp);
- delete[] temp;
- }
- va_end(arg);
- return len;
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp
deleted file mode 100644
index 4bca2b69c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp
+++ /dev/null
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SPI.h"
-
-#if DEVICE_SPI
-
-namespace mbed {
-
-SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) :
- _spi(),
- _bits(8),
- _mode(0),
- _hz(1000000) {
- spi_init(&_spi, mosi, miso, sclk, NC);
- spi_format(&_spi, _bits, _mode, 0);
- spi_frequency(&_spi, _hz);
-}
-
-void SPI::format(int bits, int mode) {
- _bits = bits;
- _mode = mode;
- SPI::_owner = NULL; // Not that elegant, but works. rmeyer
- aquire();
-}
-
-void SPI::frequency(int hz) {
- _hz = hz;
- SPI::_owner = NULL; // Not that elegant, but works. rmeyer
- aquire();
-}
-
-SPI* SPI::_owner = NULL;
-
-// ignore the fact there are multiple physical spis, and always update if it wasnt us last
-void SPI::aquire() {
- if (_owner != this) {
- spi_format(&_spi, _bits, _mode, 0);
- spi_frequency(&_spi, _hz);
- _owner = this;
- }
-}
-
-int SPI::write(int value) {
- aquire();
- return spi_master_write(&_spi, value);
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp
deleted file mode 100644
index 5e503165b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp
+++ /dev/null
@@ -1,58 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SPISlave.h"
-
-#if DEVICE_SPISLAVE
-
-namespace mbed {
-
-SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
- _spi(),
- _bits(8),
- _mode(0),
- _hz(1000000)
- {
- spi_init(&_spi, mosi, miso, sclk, ssel);
- spi_format(&_spi, _bits, _mode, 1);
- spi_frequency(&_spi, _hz);
-}
-
-void SPISlave::format(int bits, int mode) {
- _bits = bits;
- _mode = mode;
- spi_format(&_spi, _bits, _mode, 1);
-}
-
-void SPISlave::frequency(int hz) {
- _hz = hz;
- spi_frequency(&_spi, _hz);
-}
-
-int SPISlave::receive(void) {
- return(spi_slave_receive(&_spi));
-}
-
-int SPISlave::read(void) {
- return(spi_slave_read(&_spi));
-}
-
-void SPISlave::reply(int value) {
- spi_slave_write(&_spi, value);
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp
deleted file mode 100644
index 602c87a0a..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp
+++ /dev/null
@@ -1,36 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Serial.h"
-#include "wait_api.h"
-
-#if DEVICE_SERIAL
-
-namespace mbed {
-
-Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) {
-}
-
-int Serial::_getc() {
- return _base_getc();
-}
-
-int Serial::_putc(int c) {
- return _base_putc(c);
-}
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp
deleted file mode 100644
index 68cf7c381..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp
+++ /dev/null
@@ -1,108 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SerialBase.h"
-#include "wait_api.h"
-
-#if DEVICE_SERIAL
-
-namespace mbed {
-
-SerialBase::SerialBase(PinName tx, PinName rx) : _serial(), _baud(9600) {
- serial_init(&_serial, tx, rx);
- serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
-}
-
-void SerialBase::baud(int baudrate) {
- serial_baud(&_serial, baudrate);
- _baud = baudrate;
-}
-
-void SerialBase::format(int bits, Parity parity, int stop_bits) {
- serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
-}
-
-int SerialBase::readable() {
- return serial_readable(&_serial);
-}
-
-
-int SerialBase::writeable() {
- return serial_writable(&_serial);
-}
-
-void SerialBase::attach(void (*fptr)(void), IrqType type) {
- if (fptr) {
- _irq[type].attach(fptr);
- serial_irq_set(&_serial, (SerialIrq)type, 1);
- } else {
- serial_irq_set(&_serial, (SerialIrq)type, 0);
- }
-}
-
-void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
- SerialBase *handler = (SerialBase*)id;
- handler->_irq[irq_type].call();
-}
-
-int SerialBase::_base_getc() {
- return serial_getc(&_serial);
-}
-
-int SerialBase::_base_putc(int c) {
- serial_putc(&_serial, c);
- return c;
-}
-
-void SerialBase::send_break() {
- // Wait for 1.5 frames before clearing the break condition
- // This will have different effects on our platforms, but should
- // ensure that we keep the break active for at least one frame.
- // We consider a full frame (1 start bit + 8 data bits bits +
- // 1 parity bit + 2 stop bits = 12 bits) for computation.
- // One bit time (in us) = 1000000/_baud
- // Twelve bits: 12000000/baud delay
- // 1.5 frames: 18000000/baud delay
- serial_break_set(&_serial);
- wait_us(18000000/_baud);
- serial_break_clear(&_serial);
-}
-
-#if DEVICE_SERIAL_FC
-void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
- FlowControl flow_type = (FlowControl)type;
- switch(type) {
- case RTS:
- serial_set_flow_control(&_serial, flow_type, flow1, NC);
- break;
-
- case CTS:
- serial_set_flow_control(&_serial, flow_type, NC, flow1);
- break;
-
- case RTSCTS:
- case Disabled:
- serial_set_flow_control(&_serial, flow_type, flow1, flow2);
- break;
-
- default:
- break;
- }
-}
-#endif
-
-} // namespace mbed
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp
deleted file mode 100644
index 6d3a33526..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp
+++ /dev/null
@@ -1,111 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Stream.h"
-
-#include <cstdarg>
-
-namespace mbed {
-
-Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
- /* open ourselves */
- char buf[12]; /* :0x12345678 + null byte */
- std::sprintf(buf, ":%p", this);
- _file = std::fopen(buf, "w+");
- mbed_set_unbuffered_stream(_file);
-}
-
-Stream::~Stream() {
- fclose(_file);
-}
-
-int Stream::putc(int c) {
- fflush(_file);
- return std::fputc(c, _file);
-}
-int Stream::puts(const char *s) {
- fflush(_file);
- return std::fputs(s, _file);
-}
-int Stream::getc() {
- fflush(_file);
- return mbed_getc(_file);
-}
-char* Stream::gets(char *s, int size) {
- fflush(_file);
- return mbed_gets(s,size,_file);
-}
-
-int Stream::close() {
- return 0;
-}
-
-ssize_t Stream::write(const void* buffer, size_t length) {
- const char* ptr = (const char*)buffer;
- const char* end = ptr + length;
- while (ptr != end) {
- if (_putc(*ptr++) == EOF) {
- break;
- }
- }
- return ptr - (const char*)buffer;
-}
-
-ssize_t Stream::read(void* buffer, size_t length) {
- char* ptr = (char*)buffer;
- char* end = ptr + length;
- while (ptr != end) {
- int c = _getc();
- if (c==EOF) break;
- *ptr++ = c;
- }
- return ptr - (const char*)buffer;
-}
-
-off_t Stream::lseek(off_t offset, int whence) {
- return 0;
-}
-
-int Stream::isatty() {
- return 0;
-}
-
-int Stream::fsync() {
- return 0;
-}
-
-off_t Stream::flen() {
- return 0;
-}
-
-int Stream::printf(const char* format, ...) {
- std::va_list arg;
- va_start(arg, format);
- fflush(_file);
- int r = vfprintf(_file, format, arg);
- va_end(arg);
- return r;
-}
-
-int Stream::scanf(const char* format, ...) {
- std::va_list arg;
- va_start(arg, format);
- fflush(_file);
- int r = vfscanf(_file, format, arg);
- va_end(arg);
- return r;
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp
deleted file mode 100644
index 577950b85..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp
+++ /dev/null
@@ -1,39 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Ticker.h"
-
-#include "TimerEvent.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-void Ticker::detach() {
- remove();
- _function.attach(0);
-}
-
-void Ticker::setup(timestamp_t t) {
- remove();
- _delay = t;
- insert(_delay + us_ticker_read());
-}
-
-void Ticker::handler() {
- insert(event.timestamp + _delay);
- _function.call();
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp
deleted file mode 100644
index ed7950212..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp
+++ /dev/null
@@ -1,24 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Timeout.h"
-
-namespace mbed {
-
-void Timeout::handler() {
- _function.call();
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp
deleted file mode 100644
index e00eaaf54..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp
+++ /dev/null
@@ -1,68 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Timer.h"
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-Timer::Timer() : _running(), _start(), _time() {
- reset();
-}
-
-void Timer::start() {
- if (!_running) {
- _start = us_ticker_read();
- _running = 1;
- }
-}
-
-void Timer::stop() {
- _time += slicetime();
- _running = 0;
-}
-
-int Timer::read_us() {
- return _time + slicetime();
-}
-
-float Timer::read() {
- return (float)read_us() / 1000000.0f;
-}
-
-int Timer::read_ms() {
- return read_us() / 1000;
-}
-
-int Timer::slicetime() {
- if (_running) {
- return us_ticker_read() - _start;
- } else {
- return 0;
- }
-}
-
-void Timer::reset() {
- _start = us_ticker_read();
- _time = 0;
-}
-
-#ifdef MBED_OPERATORS
-Timer::operator float() {
- return read();
-}
-#endif
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp
deleted file mode 100644
index 272adf51f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp
+++ /dev/null
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "TimerEvent.h"
-#include "cmsis.h"
-
-#include <stddef.h>
-
-namespace mbed {
-
-TimerEvent::TimerEvent() : event() {
- us_ticker_set_handler((&TimerEvent::irq));
-}
-
-void TimerEvent::irq(uint32_t id) {
- TimerEvent *timer_event = (TimerEvent*)id;
- timer_event->handler();
-}
-
-TimerEvent::~TimerEvent() {
- remove();
-}
-
-// insert in to linked list
-void TimerEvent::insert(timestamp_t timestamp) {
- us_ticker_insert_event(&event, timestamp, (uint32_t)this);
-}
-
-void TimerEvent::remove() {
- us_ticker_remove_event(&event);
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c
deleted file mode 100644
index 51394707b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "mbed_assert.h"
-#include "device.h"
-
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#endif
-
-#include <stdlib.h>
-#include "mbed_interface.h"
-
-void mbed_assert_internal(const char *expr, const char *file, int line)
-{
-#if DEVICE_STDIO_MESSAGES
- fprintf(stderr, "mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
-#endif
- mbed_die();
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/board.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/board.c
deleted file mode 100644
index 910323645..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/board.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "wait_api.h"
-#include "toolchain.h"
-#include "mbed_interface.h"
-
-WEAK void mbed_die(void) {
-#ifndef NRF51_H
- __disable_irq(); // dont allow interrupts to disturb the flash pattern
-#endif
-#if (DEVICE_ERROR_RED == 1)
- gpio_t led_red; gpio_init_out(&led_red, LED_RED);
-#elif (DEVICE_ERROR_PATTERN == 1)
- gpio_t led_1; gpio_init_out(&led_1, LED1);
- gpio_t led_2; gpio_init_out(&led_2, LED2);
- gpio_t led_3; gpio_init_out(&led_3, LED3);
- gpio_t led_4; gpio_init_out(&led_4, LED4);
-#endif
-
- while (1) {
-#if (DEVICE_ERROR_RED == 1)
- gpio_write(&led_red, 1);
-
-#elif (DEVICE_ERROR_PATTERN == 1)
- gpio_write(&led_1, 1);
- gpio_write(&led_2, 0);
- gpio_write(&led_3, 0);
- gpio_write(&led_4, 1);
-#endif
-
- wait_ms(150);
-
-#if (DEVICE_ERROR_RED == 1)
- gpio_write(&led_red, 0);
-
-#elif (DEVICE_ERROR_PATTERN == 1)
- gpio_write(&led_1, 0);
- gpio_write(&led_2, 1);
- gpio_write(&led_3, 1);
- gpio_write(&led_4, 0);
-#endif
-
- wait_ms(150);
- }
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/error.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/error.c
deleted file mode 100644
index b307d8756..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/error.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stdlib.h>
-#include <stdarg.h>
-#include "device.h"
-#include "toolchain.h"
-#include "mbed_error.h"
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#endif
-
-WEAK void error(const char* format, ...) {
-#if DEVICE_STDIO_MESSAGES
- va_list arg;
- va_start(arg, format);
- vfprintf(stderr, format, arg);
- va_end(arg);
-#endif
- exit(1);
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c
deleted file mode 100644
index 3839e8bb2..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-
-static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
-{
- gpio_init(gpio, pin);
- if (pin != NC) {
- gpio_dir(gpio, PIN_INPUT);
- gpio_mode(gpio, mode);
- }
-}
-
-static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
-{
- gpio_init(gpio, pin);
- if (pin != NC) {
- gpio_write(gpio, value);
- gpio_dir(gpio, PIN_OUTPUT);
- gpio_mode(gpio, mode);
- }
-}
-
-void gpio_init_in(gpio_t* gpio, PinName pin) {
- gpio_init_in_ex(gpio, pin, PullDefault);
-}
-
-void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
- _gpio_init_in(gpio, pin, mode);
-}
-
-void gpio_init_out(gpio_t* gpio, PinName pin) {
- gpio_init_out_ex(gpio, pin, 0);
-}
-
-void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
- _gpio_init_out(gpio, pin, PullNone, value);
-}
-
-void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
- if (direction == PIN_INPUT) {
- _gpio_init_in(gpio, pin, mode);
- if (pin != NC)
- gpio_write(gpio, value); // we prepare the value in case it is switched later
- } else {
- _gpio_init_out(gpio, pin, mode, value);
- }
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c
deleted file mode 100644
index 5b27b3087..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stdio.h>
-#include "mbed_interface.h"
-
-#include "gpio_api.h"
-#include "wait_api.h"
-#include "semihost_api.h"
-#include "mbed_error.h"
-#include "toolchain.h"
-
-#if DEVICE_SEMIHOST
-
-// return true if a debugger is attached, indicating mbed interface is connected
-int mbed_interface_connected(void) {
- return semihost_connected();
-}
-
-int mbed_interface_reset(void) {
- if (mbed_interface_connected()) {
- semihost_reset();
- return 0;
- } else {
- return -1;
- }
-}
-
-WEAK int mbed_interface_uid(char *uid) {
- if (mbed_interface_connected()) {
- return semihost_uid(uid); // Returns 0 if successful, -1 on failure
- } else {
- uid[0] = 0;
- return -1;
- }
-}
-
-int mbed_interface_disconnect(void) {
- int res;
- if (mbed_interface_connected()) {
- if ((res = semihost_disabledebug()) != 0)
- return res;
- while (mbed_interface_connected());
- return 0;
- } else {
- return -1;
- }
-}
-
-int mbed_interface_powerdown(void) {
- int res;
- if (mbed_interface_connected()) {
- if ((res = semihost_powerdown()) != 0)
- return res;
- while (mbed_interface_connected());
- return 0;
- } else {
- return -1;
- }
-}
-
-// for backward compatibility
-void mbed_reset(void) {
- mbed_interface_reset();
-}
-
-WEAK int mbed_uid(char *uid) {
- return mbed_interface_uid(uid);
-}
-#endif
-
-WEAK void mbed_mac_address(char *mac) {
-#if DEVICE_SEMIHOST
- char uid[DEVICE_ID_LENGTH + 1];
- int i;
-
- // if we have a UID, extract the MAC
- if (mbed_interface_uid(uid) == 0) {
- char *p = uid;
-#if defined(DEVICE_MAC_OFFSET)
- p += DEVICE_MAC_OFFSET;
-#endif
- for (i=0; i<6; i++) {
- int byte;
- sscanf(p, "%2x", &byte);
- mac[i] = byte;
- p += 2;
- }
- mac[0] &= ~0x01; // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
- } else { // else return a default MAC
-#endif
- mac[0] = 0x00;
- mac[1] = 0x02;
- mac[2] = 0xF7;
- mac[3] = 0xF0;
- mac[4] = 0x00;
- mac[5] = 0x00;
-#if DEVICE_SEMIHOST
- }
-#endif
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c
deleted file mode 100644
index 5aab0e617..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "mbed_error.h"
-
-void pinmap_pinout(PinName pin, const PinMap *map) {
- if (pin == NC)
- return;
-
- while (map->pin != NC) {
- if (map->pin == pin) {
- pin_function(pin, map->function);
-
- pin_mode(pin, PullNone);
- return;
- }
- map++;
- }
- error("could not pinout");
-}
-
-uint32_t pinmap_merge(uint32_t a, uint32_t b) {
- // both are the same (inc both NC)
- if (a == b)
- return a;
-
- // one (or both) is not connected
- if (a == (uint32_t)NC)
- return b;
- if (b == (uint32_t)NC)
- return a;
-
- // mis-match error case
- error("pinmap mis-match");
- return (uint32_t)NC;
-}
-
-uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
- while (map->pin != NC) {
- if (map->pin == pin)
- return map->peripheral;
- map++;
- }
- return (uint32_t)NC;
-}
-
-uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
- uint32_t peripheral = (uint32_t)NC;
-
- if (pin == (PinName)NC)
- return (uint32_t)NC;
- peripheral = pinmap_find_peripheral(pin, map);
- if ((uint32_t)NC == peripheral) // no mapping available
- error("pinmap not found for peripheral");
- return peripheral;
-}
-
-uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
- while (map->pin != NC) {
- if (map->pin == pin)
- return map->function;
- map++;
- }
- return (uint32_t)NC;
-}
-
-uint32_t pinmap_function(PinName pin, const PinMap* map) {
- uint32_t function = (uint32_t)NC;
-
- if (pin == (PinName)NC)
- return (uint32_t)NC;
- function = pinmap_find_function(pin, map);
- if ((uint32_t)NC == function) // no mapping available
- error("pinmap not found for function");
- return function;
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp
deleted file mode 100644
index 82411abd2..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp
+++ /dev/null
@@ -1,569 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "platform.h"
-#include "FileHandle.h"
-#include "FileSystemLike.h"
-#include "FilePath.h"
-#include "serial_api.h"
-#include "toolchain.h"
-#include "semihost_api.h"
-#include "mbed_interface.h"
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#endif
-#include <errno.h>
-
-#if defined(__ARMCC_VERSION)
-# include <rt_sys.h>
-# define PREFIX(x) _sys##x
-# define OPEN_MAX _SYS_OPEN
-# ifdef __MICROLIB
-# pragma import(__use_full_stdio)
-# endif
-
-#elif defined(__ICCARM__)
-# include <yfuns.h>
-# define PREFIX(x) _##x
-# define OPEN_MAX 16
-
-# define STDIN_FILENO 0
-# define STDOUT_FILENO 1
-# define STDERR_FILENO 2
-
-#else
-# include <sys/stat.h>
-# include <sys/unistd.h>
-# include <sys/syslimits.h>
-# define PREFIX(x) x
-#endif
-
-using namespace mbed;
-
-#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
-// Before version 5.03, we were using a patched version of microlib with proper names
-extern const char __stdin_name[] = ":tt";
-extern const char __stdout_name[] = ":tt";
-extern const char __stderr_name[] = ":tt";
-
-#else
-extern const char __stdin_name[] = "/stdin";
-extern const char __stdout_name[] = "/stdout";
-extern const char __stderr_name[] = "/stderr";
-#endif
-
-/* newlib has the filehandle field in the FILE struct as a short, so
- * we can't just return a Filehandle* from _open and instead have to
- * put it in a filehandles array and return the index into that array
- * (or rather index+3, as filehandles 0-2 are stdin/out/err).
- */
-static FileHandle *filehandles[OPEN_MAX];
-
-FileHandle::~FileHandle() {
- /* Remove all open filehandles for this */
- for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
- if (filehandles[fh_i] == this) {
- filehandles[fh_i] = NULL;
- }
- }
-}
-
-#if DEVICE_SERIAL
-extern int stdio_uart_inited;
-extern serial_t stdio_uart;
-#endif
-
-static void init_serial() {
-#if DEVICE_SERIAL
- if (stdio_uart_inited) return;
- serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
-#endif
-}
-
-static inline int openmode_to_posix(int openmode) {
- int posix = openmode;
-#ifdef __ARMCC_VERSION
- if (openmode & OPEN_PLUS) {
- posix = O_RDWR;
- } else if(openmode & OPEN_W) {
- posix = O_WRONLY;
- } else if(openmode & OPEN_A) {
- posix = O_WRONLY|O_APPEND;
- } else {
- posix = O_RDONLY;
- }
- /* a, w, a+, w+ all create if file does not already exist */
- if (openmode & (OPEN_A|OPEN_W)) {
- posix |= O_CREAT;
- }
- /* w and w+ truncate */
- if (openmode & OPEN_W) {
- posix |= O_TRUNC;
- }
-#elif defined(__ICCARM__)
- switch (openmode & _LLIO_RDWRMASK) {
- case _LLIO_RDONLY: posix = O_RDONLY; break;
- case _LLIO_WRONLY: posix = O_WRONLY; break;
- case _LLIO_RDWR : posix = O_RDWR ; break;
- }
- if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
- if (openmode & _LLIO_APPEND) posix |= O_APPEND;
- if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
-#endif
- return posix;
-}
-
-extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
- #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
- // Before version 5.03, we were using a patched version of microlib with proper names
- // This is the workaround that the microlib author suggested us
- static int n = 0;
- if (!std::strcmp(name, ":tt")) return n++;
-
- #else
- /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
- */
- if (std::strcmp(name, __stdin_name) == 0) {
- init_serial();
- return 0;
- } else if (std::strcmp(name, __stdout_name) == 0) {
- init_serial();
- return 1;
- } else if (std::strcmp(name, __stderr_name) == 0) {
- init_serial();
- return 2;
- }
- #endif
-
- // find the first empty slot in filehandles
- unsigned int fh_i;
- for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
- if (filehandles[fh_i] == NULL) break;
- }
- if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
- return -1;
- }
-
- FileHandle *res;
-
- /* FILENAME: ":0x12345678" describes a FileLike* */
- if (name[0] == ':') {
- void *p;
- sscanf(name, ":%p", &p);
- res = (FileHandle*)p;
-
- /* FILENAME: "/file_system/file_name" */
- } else {
- FilePath path(name);
-
- if (!path.exists())
- return -1;
- else if (path.isFile()) {
- res = path.file();
- } else {
- FileSystemLike *fs = path.fileSystem();
- if (fs == NULL) return -1;
- int posix_mode = openmode_to_posix(openmode);
- res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
- }
- }
-
- if (res == NULL) return -1;
- filehandles[fh_i] = res;
-
- return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
-}
-
-extern "C" int PREFIX(_close)(FILEHANDLE fh) {
- if (fh < 3) return 0;
-
- FileHandle* fhc = filehandles[fh-3];
- filehandles[fh-3] = NULL;
- if (fhc == NULL) return -1;
-
- return fhc->close();
-}
-
-#if defined(__ICCARM__)
-extern "C" size_t __write (int fh, const unsigned char *buffer, size_t length) {
-#else
-extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
-#endif
- int n; // n is the number of bytes written
- if (fh < 3) {
-#if DEVICE_SERIAL
- if (!stdio_uart_inited) init_serial();
- for (unsigned int i = 0; i < length; i++) {
- serial_putc(&stdio_uart, buffer[i]);
- }
-#endif
- n = length;
- } else {
- FileHandle* fhc = filehandles[fh-3];
- if (fhc == NULL) return -1;
-
- n = fhc->write(buffer, length);
- }
-#ifdef __ARMCC_VERSION
- return length-n;
-#else
- return n;
-#endif
-}
-
-#if defined(__ICCARM__)
-extern "C" size_t __read (int fh, unsigned char *buffer, size_t length) {
-#else
-extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
-#endif
- int n; // n is the number of bytes read
- if (fh < 3) {
- // only read a character at a time from stdin
-#if DEVICE_SERIAL
- if (!stdio_uart_inited) init_serial();
- *buffer = serial_getc(&stdio_uart);
-#endif
- n = 1;
- } else {
- FileHandle* fhc = filehandles[fh-3];
- if (fhc == NULL) return -1;
-
- n = fhc->read(buffer, length);
- }
-#ifdef __ARMCC_VERSION
- return length-n;
-#else
- return n;
-#endif
-}
-
-#ifdef __ARMCC_VERSION
-extern "C" int PREFIX(_istty)(FILEHANDLE fh)
-#else
-extern "C" int _isatty(FILEHANDLE fh)
-#endif
-{
- /* stdin, stdout and stderr should be tty */
- if (fh < 3) return 1;
-
- FileHandle* fhc = filehandles[fh-3];
- if (fhc == NULL) return -1;
-
- return fhc->isatty();
-}
-
-extern "C"
-#if defined(__ARMCC_VERSION)
-int _sys_seek(FILEHANDLE fh, long position)
-#elif defined(__ICCARM__)
-long __lseek(int fh, long offset, int whence)
-#else
-int _lseek(FILEHANDLE fh, int offset, int whence)
-#endif
-{
- if (fh < 3) return 0;
-
- FileHandle* fhc = filehandles[fh-3];
- if (fhc == NULL) return -1;
-
-#if defined(__ARMCC_VERSION)
- return fhc->lseek(position, SEEK_SET);
-#else
- return fhc->lseek(offset, whence);
-#endif
-}
-
-#ifdef __ARMCC_VERSION
-extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
- if (fh < 3) return 0;
-
- FileHandle* fhc = filehandles[fh-3];
- if (fhc == NULL) return -1;
-
- return fhc->fsync();
-}
-
-extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
- if (fh < 3) return 0;
-
- FileHandle* fhc = filehandles[fh-3];
- if (fhc == NULL) return -1;
-
- return fhc->flen();
-}
-#endif
-
-
-#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
-extern "C" int _fstat(int fd, struct stat *st) {
- if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
- st->st_mode = S_IFCHR;
- return 0;
- }
-
- errno = EBADF;
- return -1;
-}
-#endif
-
-namespace std {
-extern "C" int remove(const char *path) {
- FilePath fp(path);
- FileSystemLike *fs = fp.fileSystem();
- if (fs == NULL) return -1;
-
- return fs->remove(fp.fileName());
-}
-
-extern "C" int rename(const char *oldname, const char *newname) {
- FilePath fpOld(oldname);
- FilePath fpNew(newname);
- FileSystemLike *fsOld = fpOld.fileSystem();
- FileSystemLike *fsNew = fpNew.fileSystem();
-
- /* rename only if both files are on the same FS */
- if (fsOld != fsNew || fsOld == NULL) return -1;
-
- return fsOld->rename(fpOld.fileName(), fpNew.fileName());
-}
-
-extern "C" char *tmpnam(char *s) {
- return NULL;
-}
-
-extern "C" FILE *tmpfile() {
- return NULL;
-}
-} // namespace std
-
-#ifdef __ARMCC_VERSION
-extern "C" char *_sys_command_string(char *cmd, int len) {
- return NULL;
-}
-#endif
-
-extern "C" DIR *opendir(const char *path) {
- /* root dir is FileSystemLike */
- if (path[0] == '/' && path[1] == 0) {
- return FileSystemLike::opendir();
- }
-
- FilePath fp(path);
- FileSystemLike* fs = fp.fileSystem();
- if (fs == NULL) return NULL;
-
- return fs->opendir(fp.fileName());
-}
-
-extern "C" struct dirent *readdir(DIR *dir) {
- return dir->readdir();
-}
-
-extern "C" int closedir(DIR *dir) {
- return dir->closedir();
-}
-
-extern "C" void rewinddir(DIR *dir) {
- dir->rewinddir();
-}
-
-extern "C" off_t telldir(DIR *dir) {
- return dir->telldir();
-}
-
-extern "C" void seekdir(DIR *dir, off_t off) {
- dir->seekdir(off);
-}
-
-extern "C" int mkdir(const char *path, mode_t mode) {
- FilePath fp(path);
- FileSystemLike *fs = fp.fileSystem();
- if (fs == NULL) return -1;
-
- return fs->mkdir(fp.fileName(), mode);
-}
-
-#if defined(TOOLCHAIN_GCC)
-/* prevents the exception handling name demangling code getting pulled in */
-#include "mbed_error.h"
-namespace __gnu_cxx {
- void __verbose_terminate_handler() {
- error("Exception");
- }
-}
-extern "C" WEAK void __cxa_pure_virtual(void);
-extern "C" WEAK void __cxa_pure_virtual(void) {
- exit(1);
-}
-
-#endif
-
-// ****************************************************************************
-// mbed_main is a function that is called before main()
-// mbed_sdk_init() is also a function that is called before main(), but unlike
-// mbed_main(), it is not meant for user code, but for the SDK itself to perform
-// initializations before main() is called.
-
-extern "C" WEAK void mbed_main(void);
-extern "C" WEAK void mbed_main(void) {
-}
-
-extern "C" WEAK void mbed_sdk_init(void);
-extern "C" WEAK void mbed_sdk_init(void) {
-}
-
-#if defined(TOOLCHAIN_ARM)
-extern "C" int $Super$$main(void);
-
-extern "C" int $Sub$$main(void) {
- mbed_sdk_init();
- mbed_main();
- return $Super$$main();
-}
-#elif defined(TOOLCHAIN_GCC)
-extern "C" int __real_main(void);
-
-extern "C" int __wrap_main(void) {
- mbed_sdk_init();
- mbed_main();
- return __real_main();
-}
-#elif defined(TOOLCHAIN_IAR)
-// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
-// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
-// 'main' to another symbol looses the original 'main' symbol. However, its startup
-// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
-// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
-extern "C" void __iar_argc_argv() {
- mbed_sdk_init();
- mbed_main();
-}
-#endif
-
-// Provide implementation of _sbrk (low-level dynamic memory allocation
-// routine) for GCC_ARM which compares new heap pointer with MSP instead of
-// SP. This make it compatible with RTX RTOS thread stacks.
-#if defined(TOOLCHAIN_GCC_ARM)
-// Linker defined symbol used by _sbrk to indicate where heap should start.
-extern "C" int __end__;
-
-#if defined(TARGET_CORTEX_A)
-extern "C" uint32_t __HeapLimit;
-#endif
-
-// Turn off the errno macro and use actual global variable instead.
-#undef errno
-extern "C" int errno;
-
-// For ARM7 only
-register unsigned char * stack_ptr __asm ("sp");
-
-// Dynamic memory allocation related syscall.
-extern "C" caddr_t _sbrk(int incr) {
- static unsigned char* heap = (unsigned char*)&__end__;
- unsigned char* prev_heap = heap;
- unsigned char* new_heap = heap + incr;
-
-#if defined(TARGET_ARM7)
- if (new_heap >= stack_ptr) {
-#elif defined(TARGET_CORTEX_A)
- if (new_heap >= (unsigned char*)&__HeapLimit) { /* __HeapLimit is end of heap section */
-#else
- if (new_heap >= (unsigned char*)__get_MSP()) {
-#endif
- errno = ENOMEM;
- return (caddr_t)-1;
- }
-
- heap = new_heap;
- return (caddr_t) prev_heap;
-}
-#endif
-
-
-#ifdef TOOLCHAIN_GCC_CW
-// TODO: Ideally, we would like to define directly "_ExitProcess"
-extern "C" void mbed_exit(int return_code) {
-#elif defined TOOLCHAIN_GCC_ARM
-extern "C" void _exit(int return_code) {
-#else
-namespace std {
-extern "C" void exit(int return_code) {
-#endif
-
-#if DEVICE_STDIO_MESSAGES
- fflush(stdout);
- fflush(stderr);
-#endif
-
-#if DEVICE_SEMIHOST
- if (mbed_interface_connected()) {
- semihost_exit();
- }
-#endif
- if (return_code) {
- mbed_die();
- }
-
- while (1);
-}
-
-#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW)
-} //namespace std
-#endif
-
-
-namespace mbed {
-
-void mbed_set_unbuffered_stream(FILE *_file) {
-#if defined (__ICCARM__)
- char buf[2];
- std::setvbuf(_file,buf,_IONBF,NULL);
-#else
- setbuf(_file, NULL);
-#endif
-}
-
-int mbed_getc(FILE *_file){
-#if defined (__ICCARM__)
- /*This is only valid for unbuffered streams*/
- int res = std::fgetc(_file);
- if (res>=0){
- _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
- _file->_Rend = _file->_Wend;
- _file->_Next = _file->_Wend;
- }
- return res;
-#else
- return std::fgetc(_file);
-#endif
-}
-
-char* mbed_gets(char*s, int size, FILE *_file){
-#if defined (__ICCARM__)
- /*This is only valid for unbuffered streams*/
- char *str = fgets(s,size,_file);
- if (str!=NULL){
- _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
- _file->_Rend = _file->_Wend;
- _file->_Next = _file->_Wend;
- }
- return str;
-#else
- return std::fgets(s,size,_file);
-#endif
-}
-
-} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c
deleted file mode 100644
index 982279746..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-
-#include <time.h>
-#include "rtc_time.h"
-#include "us_ticker_api.h"
-
-#if DEVICE_RTC
-static void (*_rtc_init)(void) = rtc_init;
-static int (*_rtc_isenabled)(void) = rtc_isenabled;
-static time_t (*_rtc_read)(void) = rtc_read;
-static void (*_rtc_write)(time_t t) = rtc_write;
-#else
-static void (*_rtc_init)(void) = NULL;
-static int (*_rtc_isenabled)(void) = NULL;
-static time_t (*_rtc_read)(void) = NULL;
-static void (*_rtc_write)(time_t t) = NULL;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if defined (__ICCARM__)
-time_t __time32(time_t *timer)
-#else
-time_t time(time_t *timer)
-#endif
-
-{
- if (_rtc_isenabled != NULL) {
- if (!(_rtc_isenabled())) {
- set_time(0);
- }
- }
-
- time_t t = 0;
- if (_rtc_read != NULL) {
- t = _rtc_read();
- }
-
- if (timer != NULL) {
- *timer = t;
- }
- return t;
-}
-
-void set_time(time_t t) {
- if (_rtc_init != NULL) {
- _rtc_init();
- }
- if (_rtc_write != NULL) {
- _rtc_write(t);
- }
-}
-
-clock_t clock() {
- clock_t t = us_ticker_read();
- t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
- return t;
-}
-
-void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
- __disable_irq();
- _rtc_read = read_rtc;
- _rtc_write = write_rtc;
- _rtc_init = init_rtc;
- _rtc_isenabled = isenabled_rtc;
- __enable_irq();
-}
-
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c
deleted file mode 100644
index e4e136eca..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "cmsis.h"
-#include "semihost_api.h"
-
-#include <stdint.h>
-#include <string.h>
-
-#if DEVICE_SEMIHOST
-
-// ARM Semihosting Commands
-#define SYS_OPEN (0x1)
-#define SYS_CLOSE (0x2)
-#define SYS_WRITE (0x5)
-#define SYS_READ (0x6)
-#define SYS_ISTTY (0x9)
-#define SYS_SEEK (0xa)
-#define SYS_ENSURE (0xb)
-#define SYS_FLEN (0xc)
-#define SYS_REMOVE (0xe)
-#define SYS_RENAME (0xf)
-#define SYS_EXIT (0x18)
-
-// mbed Semihosting Commands
-#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
-#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
-#define USR_UID (RESERVED_FOR_USER_APPLICATIONS + 1)
-#define USR_RESET (RESERVED_FOR_USER_APPLICATIONS + 2)
-#define USR_VBUS (RESERVED_FOR_USER_APPLICATIONS + 3)
-#define USR_POWERDOWN (RESERVED_FOR_USER_APPLICATIONS + 4)
-#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
-
-#if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char* name, int openmode) {
- uint32_t args[3];
- args[0] = (uint32_t)name;
- args[1] = (uint32_t)openmode;
- args[2] = (uint32_t)strlen(name);
- return __semihost(SYS_OPEN, args);
-}
-
-int semihost_close(FILEHANDLE fh) {
- return __semihost(SYS_CLOSE, &fh);
-}
-
-int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
- if (length == 0) return 0;
-
- uint32_t args[3];
- args[0] = (uint32_t)fh;
- args[1] = (uint32_t)buffer;
- args[2] = (uint32_t)length;
- return __semihost(SYS_WRITE, args);
-}
-
-int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
- uint32_t args[3];
- args[0] = (uint32_t)fh;
- args[1] = (uint32_t)buffer;
- args[2] = (uint32_t)length;
- return __semihost(SYS_READ, args);
-}
-
-int semihost_istty(FILEHANDLE fh) {
- return __semihost(SYS_ISTTY, &fh);
-}
-
-int semihost_seek(FILEHANDLE fh, long position) {
- uint32_t args[2];
- args[0] = (uint32_t)fh;
- args[1] = (uint32_t)position;
- return __semihost(SYS_SEEK, args);
-}
-
-int semihost_ensure(FILEHANDLE fh) {
- return __semihost(SYS_ENSURE, &fh);
-}
-
-long semihost_flen(FILEHANDLE fh) {
- return __semihost(SYS_FLEN, &fh);
-}
-
-int semihost_remove(const char *name) {
- uint32_t args[2];
- args[0] = (uint32_t)name;
- args[1] = (uint32_t)strlen(name);
- return __semihost(SYS_REMOVE, args);
-}
-
-int semihost_rename(const char *old_name, const char *new_name) {
- uint32_t args[4];
- args[0] = (uint32_t)old_name;
- args[1] = (uint32_t)strlen(old_name);
- args[0] = (uint32_t)new_name;
- args[1] = (uint32_t)strlen(new_name);
- return __semihost(SYS_RENAME, args);
-}
-#endif
-
-int semihost_exit(void) {
- uint32_t args[4];
- return __semihost(SYS_EXIT, args);
-}
-
-int semihost_uid(char *uid) {
- uint32_t args[2];
- args[0] = (uint32_t)uid;
- args[1] = DEVICE_ID_LENGTH + 1;
- return __semihost(USR_UID, &args);
-}
-
-int semihost_reset(void) {
- // Does not normally return, however if used with older firmware versions
- // that do not support this call it will return -1.
- return __semihost(USR_RESET, NULL);
-}
-
-int semihost_vbus(void) {
- return __semihost(USR_VBUS, NULL);
-}
-
-int semihost_powerdown(void) {
- return __semihost(USR_POWERDOWN, NULL);
-}
-
-#if DEVICE_DEBUG_AWARENESS
-
-int semihost_connected(void) {
- return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
-}
-
-#else
-// These processors cannot know if the interface is connect, assume so:
-static int is_debugger_attached = 1;
-
-int semihost_connected(void) {
- return is_debugger_attached;
-}
-#endif
-
-int semihost_disabledebug(void) {
-#if !(DEVICE_DEBUG_AWARENESS)
- is_debugger_attached = 0;
-#endif
- return __semihost(USR_DISABLEDEBUG, NULL);
-}
-
-#endif
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c
deleted file mode 100644
index 659a04f48..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "cmsis.h"
-
-static ticker_event_handler event_handler;
-static ticker_event_t *head = NULL;
-
-void us_ticker_set_handler(ticker_event_handler handler) {
- us_ticker_init();
-
- event_handler = handler;
-}
-
-void us_ticker_irq_handler(void) {
- us_ticker_clear_interrupt();
-
- /* Go through all the pending TimerEvents */
- while (1) {
- if (head == NULL) {
- // There are no more TimerEvents left, so disable matches.
- us_ticker_disable_interrupt();
- return;
- }
-
- if ((int)(head->timestamp - us_ticker_read()) <= 0) {
- // This event was in the past:
- // point to the following one and execute its handler
- ticker_event_t *p = head;
- head = head->next;
- if (event_handler != NULL) {
- event_handler(p->id); // NOTE: the handler can set new events
- }
- /* Note: We continue back to examining the head because calling the
- * event handler may have altered the chain of pending events. */
- } else {
- // This event and the following ones in the list are in the future:
- // set it as next interrupt and return
- us_ticker_set_interrupt(head->timestamp);
- return;
- }
- }
-}
-
-void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id) {
- /* disable interrupts for the duration of the function */
- __disable_irq();
-
- // initialise our data
- obj->timestamp = timestamp;
- obj->id = id;
-
- /* Go through the list until we either reach the end, or find
- an element this should come before (which is possibly the
- head). */
- ticker_event_t *prev = NULL, *p = head;
- while (p != NULL) {
- /* check if we come before p */
- if ((int)(timestamp - p->timestamp) < 0) {
- break;
- }
- /* go to the next element */
- prev = p;
- p = p->next;
- }
-
- /* if we're at the end p will be NULL, which is correct */
- obj->next = p;
-
- /* if prev is NULL we're at the head */
- if (prev == NULL) {
- head = obj;
- us_ticker_set_interrupt(timestamp);
- } else {
- prev->next = obj;
- }
-
- __enable_irq();
-}
-
-void us_ticker_remove_event(ticker_event_t *obj) {
- __disable_irq();
-
- // remove this object from the list
- if (head == obj) {
- // first in the list, so just drop me
- head = obj->next;
- if (head == NULL) {
- us_ticker_disable_interrupt();
- } else {
- us_ticker_set_interrupt(head->timestamp);
- }
- } else {
- // find the object before me, then drop me
- ticker_event_t* p = head;
- while (p != NULL) {
- if (p->next == obj) {
- p->next = obj->next;
- break;
- }
- p = p->next;
- }
- }
-
- __enable_irq();
-}
-
-int us_ticker_get_next_timestamp(timestamp_t *timestamp) {
- int ret = 0;
-
- /* if head is NULL, there are no pending events */
- __disable_irq();
- if (head != NULL) {
- *timestamp = head->timestamp;
- ret = 1;
- }
- __enable_irq();
-
- return ret;
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c
deleted file mode 100644
index b276614ca..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "wait_api.h"
-#include "us_ticker_api.h"
-
-void wait(float s) {
- wait_us(s * 1000000.0f);
-}
-
-void wait_ms(int ms) {
- wait_us(ms * 1000);
-}
-
-void wait_us(int us) {
- uint32_t start = us_ticker_read();
- while ((us_ticker_read() - start) < (uint32_t)us);
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h
deleted file mode 100644
index 98d02c1b8..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_API_H
-#define MBED_ANALOGIN_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct analogin_s analogin_t;
-
-void analogin_init (analogin_t *obj, PinName pin);
-float analogin_read (analogin_t *obj);
-uint16_t analogin_read_u16(analogin_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h
deleted file mode 100644
index 97a201376..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_API_H
-#define MBED_ANALOGOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct dac_s dac_t;
-
-void analogout_init (dac_t *obj, PinName pin);
-void analogout_free (dac_t *obj);
-void analogout_write (dac_t *obj, float value);
-void analogout_write_u16(dac_t *obj, uint16_t value);
-float analogout_read (dac_t *obj);
-uint16_t analogout_read_u16 (dac_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h
deleted file mode 100644
index 48bc10469..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_API_H
-#define MBED_CAN_API_H
-
-#include "device.h"
-
-#if DEVICE_CAN
-
-#include "PinNames.h"
-#include "PeripheralNames.h"
-#include "can_helper.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- IRQ_RX,
- IRQ_TX,
- IRQ_ERROR,
- IRQ_OVERRUN,
- IRQ_WAKEUP,
- IRQ_PASSIVE,
- IRQ_ARB,
- IRQ_BUS,
- IRQ_READY
-} CanIrqType;
-
-
-typedef enum {
- MODE_RESET,
- MODE_NORMAL,
- MODE_SILENT,
- MODE_TEST_GLOBAL,
- MODE_TEST_LOCAL,
- MODE_TEST_SILENT
-} CanMode;
-
-typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
-
-typedef struct can_s can_t;
-
-void can_init (can_t *obj, PinName rd, PinName td);
-void can_free (can_t *obj);
-int can_frequency(can_t *obj, int hz);
-
-void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
-void can_irq_free (can_t *obj);
-void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable);
-
-int can_write (can_t *obj, CAN_Message, int cc);
-int can_read (can_t *obj, CAN_Message *msg, int handle);
-int can_mode (can_t *obj, CanMode mode);
-int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
-void can_reset (can_t *obj);
-unsigned char can_rderror (can_t *obj);
-unsigned char can_tderror (can_t *obj);
-void can_monitor (can_t *obj, int silent);
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif // MBED_CAN_API_H
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h
deleted file mode 100644
index 4cae77e13..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_API_H
-#define MBED_ETHERNET_API_H
-
-#include "device.h"
-
-#if DEVICE_ETHERNET
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Connection constants
-
-int ethernet_init(void);
-void ethernet_free(void);
-
-// write size bytes from data to ethernet buffer
-// return num bytes written
-// or -1 if size is too big
-int ethernet_write(const char *data, int size);
-
-// send ethernet write buffer, returning the packet size sent
-int ethernet_send(void);
-
-// recieve from ethernet buffer, returning packet size, or 0 if no packet
-int ethernet_receive(void);
-
-// read size bytes in to data, return actual num bytes read (0..size)
-// if data == NULL, throw the bytes away
-int ethernet_read(char *data, int size);
-
-// get the ethernet address
-void ethernet_address(char *mac);
-
-// see if the link is up
-int ethernet_link(void);
-
-// force link settings
-void ethernet_set_link(int speed, int duplex);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h
deleted file mode 100644
index 872b547ea..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_API_H
-#define MBED_GPIO_API_H
-
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Set the given pin as GPIO
- * @param pin The pin to be set as GPIO
- * @return The GPIO port mask for this pin
- **/
-uint32_t gpio_set(PinName pin);
-
-/* Checks if gpio object is connected (pin was not initialized with NC)
- * @param pin The pin to be set as GPIO
- * @return 0 if port is initialized with NC
- **/
-int gpio_is_connected(const gpio_t *obj);
-
-/* GPIO object */
-void gpio_init(gpio_t *obj, PinName pin);
-
-void gpio_mode (gpio_t *obj, PinMode mode);
-void gpio_dir (gpio_t *obj, PinDirection direction);
-
-void gpio_write(gpio_t *obj, int value);
-int gpio_read (gpio_t *obj);
-
-// the following set of functions are generic and are implemented in the common gpio.c file
-void gpio_init_in(gpio_t* gpio, PinName pin);
-void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
-void gpio_init_out(gpio_t* gpio, PinName pin);
-void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
-void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h
deleted file mode 100644
index 76c7e927e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_IRQ_API_H
-#define MBED_GPIO_IRQ_API_H
-
-#include "device.h"
-
-#if DEVICE_INTERRUPTIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- IRQ_NONE,
- IRQ_RISE,
- IRQ_FALL
-} gpio_irq_event;
-
-typedef struct gpio_irq_s gpio_irq_t;
-
-typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
-void gpio_irq_free(gpio_irq_t *obj);
-void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
-void gpio_irq_enable(gpio_irq_t *obj);
-void gpio_irq_disable(gpio_irq_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h
deleted file mode 100644
index c4da824e7..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_API_H
-#define MBED_I2C_API_H
-
-#include "device.h"
-
-#if DEVICE_I2C
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct i2c_s i2c_t;
-
-enum {
- I2C_ERROR_NO_SLAVE = -1,
- I2C_ERROR_BUS_BUSY = -2
-};
-
-void i2c_init (i2c_t *obj, PinName sda, PinName scl);
-void i2c_frequency (i2c_t *obj, int hz);
-int i2c_start (i2c_t *obj);
-int i2c_stop (i2c_t *obj);
-int i2c_read (i2c_t *obj, int address, char *data, int length, int stop);
-int i2c_write (i2c_t *obj, int address, const char *data, int length, int stop);
-void i2c_reset (i2c_t *obj);
-int i2c_byte_read (i2c_t *obj, int last);
-int i2c_byte_write (i2c_t *obj, int data);
-
-#if DEVICE_I2CSLAVE
-void i2c_slave_mode (i2c_t *obj, int enable_slave);
-int i2c_slave_receive(i2c_t *obj);
-int i2c_slave_read (i2c_t *obj, char *data, int length);
-int i2c_slave_write (i2c_t *obj, const char *data, int length);
-int i2c_slave_byte_read(i2c_t *obj, int last);
-int i2c_slave_byte_write(i2c_t *obj, int data);
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h
deleted file mode 100644
index a9cc92186..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINMAP_H
-#define MBED_PINMAP_H
-
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- int peripheral;
- int function;
-} PinMap;
-
-void pin_function(PinName pin, int function);
-void pin_mode (PinName pin, PinMode mode);
-
-uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
-uint32_t pinmap_function(PinName pin, const PinMap* map);
-uint32_t pinmap_merge (uint32_t a, uint32_t b);
-void pinmap_pinout (PinName pin, const PinMap *map);
-uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
-uint32_t pinmap_find_function(PinName pin, const PinMap* map);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h
deleted file mode 100644
index f687cfe89..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTMAP_H
-#define MBED_PORTMAP_H
-
-#include "device.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct port_s port_t;
-
-PinName port_pin(PortName port, int pin_n);
-
-void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
-void port_mode (port_t *obj, PinMode mode);
-void port_dir (port_t *obj, PinDirection dir);
-void port_write(port_t *obj, int value);
-int port_read (port_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h
deleted file mode 100644
index 6557fcdc4..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_API_H
-#define MBED_PWMOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_PWMOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct pwmout_s pwmout_t;
-
-void pwmout_init (pwmout_t* obj, PinName pin);
-void pwmout_free (pwmout_t* obj);
-
-void pwmout_write (pwmout_t* obj, float percent);
-float pwmout_read (pwmout_t* obj);
-
-void pwmout_period (pwmout_t* obj, float seconds);
-void pwmout_period_ms (pwmout_t* obj, int ms);
-void pwmout_period_us (pwmout_t* obj, int us);
-
-void pwmout_pulsewidth (pwmout_t* obj, float seconds);
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
-void pwmout_pulsewidth_us(pwmout_t* obj, int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h
deleted file mode 100644
index 663f8884f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RTC_API_H
-#define MBED_RTC_API_H
-
-#include "device.h"
-
-#if DEVICE_RTC
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void rtc_init(void);
-void rtc_free(void);
-int rtc_isenabled(void);
-
-time_t rtc_read(void);
-void rtc_write(time_t t);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h
deleted file mode 100644
index 2b0f0c4ab..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_API_H
-#define MBED_SERIAL_API_H
-
-#include "device.h"
-
-#if DEVICE_SERIAL
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- ParityNone = 0,
- ParityOdd = 1,
- ParityEven = 2,
- ParityForced1 = 3,
- ParityForced0 = 4
-} SerialParity;
-
-typedef enum {
- RxIrq,
- TxIrq
-} SerialIrq;
-
-typedef enum {
- FlowControlNone,
- FlowControlRTS,
- FlowControlCTS,
- FlowControlRTSCTS
-} FlowControl;
-
-typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
-
-typedef struct serial_s serial_t;
-
-void serial_init (serial_t *obj, PinName tx, PinName rx);
-void serial_free (serial_t *obj);
-void serial_baud (serial_t *obj, int baudrate);
-void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
-void serial_irq_set (serial_t *obj, SerialIrq irq, uint32_t enable);
-
-int serial_getc (serial_t *obj);
-void serial_putc (serial_t *obj, int c);
-int serial_readable (serial_t *obj);
-int serial_writable (serial_t *obj);
-void serial_clear (serial_t *obj);
-
-void serial_break_set (serial_t *obj);
-void serial_break_clear(serial_t *obj);
-
-void serial_pinout_tx(PinName tx);
-
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h
deleted file mode 100644
index c8cf3b6f8..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SLEEP_API_H
-#define MBED_SLEEP_API_H
-
-#include "device.h"
-
-#if DEVICE_SLEEP
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Send the microcontroller to sleep
- *
- * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
- * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
- * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
- * memory state are maintained, and the peripherals continue to work and can generate interrupts.
- *
- * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
- *
- * @note
- * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void sleep(void);
-
-/** Send the microcontroller to deep sleep
- *
- * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
- * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
- * is still maintained.
- *
- * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
- *
- * @note
- * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void deepsleep(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h
deleted file mode 100644
index 7553dc1e3..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_API_H
-#define MBED_SPI_API_H
-
-#include "device.h"
-
-#if DEVICE_SPI
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct spi_s spi_t;
-
-void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
-void spi_free (spi_t *obj);
-void spi_format (spi_t *obj, int bits, int mode, int slave);
-void spi_frequency (spi_t *obj, int hz);
-int spi_master_write (spi_t *obj, int value);
-int spi_slave_receive(spi_t *obj);
-int spi_slave_read (spi_t *obj);
-void spi_slave_write (spi_t *obj, int value);
-int spi_busy (spi_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h
deleted file mode 100644
index 1fa93170e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_US_TICKER_API_H
-#define MBED_US_TICKER_API_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef uint32_t timestamp_t;
-
-uint32_t us_ticker_read(void);
-
-typedef void (*ticker_event_handler)(uint32_t id);
-void us_ticker_set_handler(ticker_event_handler handler);
-
-typedef struct ticker_event_s {
- timestamp_t timestamp;
- uint32_t id;
- struct ticker_event_s *next;
-} ticker_event_t;
-
-void us_ticker_init(void);
-void us_ticker_set_interrupt(timestamp_t timestamp);
-void us_ticker_disable_interrupt(void);
-void us_ticker_clear_interrupt(void);
-void us_ticker_irq_handler(void);
-
-void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
-void us_ticker_remove_event(ticker_event_t *obj);
-int us_ticker_get_next_timestamp(timestamp_t *timestamp);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h
deleted file mode 100644
index b979eb7db..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h
+++ /dev/null
@@ -1,5836 +0,0 @@
-/*
-** ###################################################################
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
-** K20P32M50SF0RM Rev. 1, Oct 2011
-** K20P48M50SF0RM Rev. 1, Oct 2011
-**
-** Version: rev. 2.0, 2012-03-19
-**
-** Abstract:
-** CMSIS Peripheral Access Layer for MK20D5
-**
-** Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2011-12-15)
-** Initial version
-** - rev. 2.0 (2012-03-19)
-** PDB Peripheral register structure updated.
-** DMA Registers and bits for unsupported DMA channels removed.
-**
-** ###################################################################
-*/
-
-/**
- * @file MK20D5.h
- * @version 2.0
- * @date 2012-03-19
- * @brief CMSIS Peripheral Access Layer for MK20D5
- *
- * CMSIS Peripheral Access Layer for MK20D5
- */
-
-#if !defined(MK20D5_H_)
-#define MK20D5_H_ /**< Symbol preventing repeated inclusion */
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0200u
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
-
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
-
-/* ----------------------------------------------------------------------------
- -- Interrupt vector numbers
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-typedef enum IRQn {
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
-
- /* Device specific interrupts */
- DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
- DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
- DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
- DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
- DMA_Error_IRQn = 4, /**< DMA error interrupt */
- Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
- FTFL_IRQn = 6, /**< FTFL interrupt */
- Read_Collision_IRQn = 7, /**< Read collision interrupt */
- LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */
- LLW_IRQn = 9, /**< Low Leakage Wakeup */
- Watchdog_IRQn = 10, /**< WDOG interrupt */
- I2C0_IRQn = 11, /**< I2C0 interrupt */
- SPI0_IRQn = 12, /**< SPI0 interrupt */
- I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */
- I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */
- UART0_LON_IRQn = 15, /**< UART0 LON interrupt */
- UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */
- UART0_ERR_IRQn = 17, /**< UART0 error interrupt */
- UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */
- UART1_ERR_IRQn = 19, /**< UART1 error interrupt */
- UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */
- UART2_ERR_IRQn = 21, /**< UART2 error interrupt */
- ADC0_IRQn = 22, /**< ADC0 interrupt */
- CMP0_IRQn = 23, /**< CMP0 interrupt */
- CMP1_IRQn = 24, /**< CMP1 interrupt */
- FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */
- FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */
- CMT_IRQn = 27, /**< CMT interrupt */
- RTC_IRQn = 28, /**< RTC interrupt */
- RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */
- PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */
- PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */
- PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */
- PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */
- PDB0_IRQn = 34, /**< PDB0 interrupt */
- USB0_IRQn = 35, /**< USB0 interrupt */
- USBDCD_IRQn = 36, /**< USBDCD interrupt */
- TSI0_IRQn = 37, /**< TSI0 interrupt */
- MCG_IRQn = 38, /**< MCG interrupt */
- LPTimer_IRQn = 39, /**< LPTimer interrupt */
- PORTA_IRQn = 40, /**< Port A interrupt */
- PORTB_IRQn = 41, /**< Port B interrupt */
- PORTC_IRQn = 42, /**< Port C interrupt */
- PORTD_IRQn = 43, /**< Port D interrupt */
- PORTE_IRQn = 44, /**< Port E interrupt */
- SWI_IRQn = 45 /**< Software interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
- -- Cortex M4 Core Configuration
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
- * @{
- */
-
-#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-
-#include "core_cm4.h" /* Core Peripheral Access Layer */
-#include "system_MK20D5.h" /* Device specific configuration file */
-
-/**
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
- -- Device Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
- -- ADC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
- __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
- __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
- __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
- __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
- __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
- __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
- __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
- __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
- __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
- __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
- __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
- __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
- __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
- __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
- __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
- __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
- __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
- __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
- __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
- __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
- __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
- __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
- __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
-} ADC_Type;
-
-/* ----------------------------------------------------------------------------
- -- ADC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
-
-/**
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x4003B000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-
-/**
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
- * @{
- */
-
-/** CMP - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
- __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
- __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
- __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
- __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
- __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type;
-
-/* ----------------------------------------------------------------------------
- -- CMP Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Register_Masks CMP Register Masks
- * @{
- */
-
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-
-/**
- * @}
- */ /* end of group CMP_Register_Masks */
-
-
-/* CMP - Peripheral instance base addresses */
-/** Peripheral CMP0 base address */
-#define CMP0_BASE (0x40073000u)
-/** Peripheral CMP0 base pointer */
-#define CMP0 ((CMP_Type *)CMP0_BASE)
-/** Peripheral CMP1 base address */
-#define CMP1_BASE (0x40073008u)
-/** Peripheral CMP1 base pointer */
-#define CMP1 ((CMP_Type *)CMP1_BASE)
-
-/**
- * @}
- */ /* end of group CMP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
- * @{
- */
-
-/** CMT - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
- __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
- __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
- __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
- __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
- __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
- __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
- __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
- __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
- __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
- __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
- __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
-} CMT_Type;
-
-/* ----------------------------------------------------------------------------
- -- CMT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMT_Register_Masks CMT Register Masks
- * @{
- */
-
-/* CGH1 Bit Fields */
-#define CMT_CGH1_PH_MASK 0xFFu
-#define CMT_CGH1_PH_SHIFT 0
-#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
-/* CGL1 Bit Fields */
-#define CMT_CGL1_PL_MASK 0xFFu
-#define CMT_CGL1_PL_SHIFT 0
-#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
-/* CGH2 Bit Fields */
-#define CMT_CGH2_SH_MASK 0xFFu
-#define CMT_CGH2_SH_SHIFT 0
-#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
-/* CGL2 Bit Fields */
-#define CMT_CGL2_SL_MASK 0xFFu
-#define CMT_CGL2_SL_SHIFT 0
-#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
-/* OC Bit Fields */
-#define CMT_OC_IROPEN_MASK 0x20u
-#define CMT_OC_IROPEN_SHIFT 5
-#define CMT_OC_CMTPOL_MASK 0x40u
-#define CMT_OC_CMTPOL_SHIFT 6
-#define CMT_OC_IROL_MASK 0x80u
-#define CMT_OC_IROL_SHIFT 7
-/* MSC Bit Fields */
-#define CMT_MSC_MCGEN_MASK 0x1u
-#define CMT_MSC_MCGEN_SHIFT 0
-#define CMT_MSC_EOCIE_MASK 0x2u
-#define CMT_MSC_EOCIE_SHIFT 1
-#define CMT_MSC_FSK_MASK 0x4u
-#define CMT_MSC_FSK_SHIFT 2
-#define CMT_MSC_BASE_MASK 0x8u
-#define CMT_MSC_BASE_SHIFT 3
-#define CMT_MSC_EXSPC_MASK 0x10u
-#define CMT_MSC_EXSPC_SHIFT 4
-#define CMT_MSC_CMTDIV_MASK 0x60u
-#define CMT_MSC_CMTDIV_SHIFT 5
-#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
-#define CMT_MSC_EOCF_MASK 0x80u
-#define CMT_MSC_EOCF_SHIFT 7
-/* CMD1 Bit Fields */
-#define CMT_CMD1_MB_MASK 0xFFu
-#define CMT_CMD1_MB_SHIFT 0
-#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
-/* CMD2 Bit Fields */
-#define CMT_CMD2_MB_MASK 0xFFu
-#define CMT_CMD2_MB_SHIFT 0
-#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
-/* CMD3 Bit Fields */
-#define CMT_CMD3_SB_MASK 0xFFu
-#define CMT_CMD3_SB_SHIFT 0
-#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
-/* CMD4 Bit Fields */
-#define CMT_CMD4_SB_MASK 0xFFu
-#define CMT_CMD4_SB_SHIFT 0
-#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
-/* PPS Bit Fields */
-#define CMT_PPS_PPSDIV_MASK 0xFu
-#define CMT_PPS_PPSDIV_SHIFT 0
-#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
-/* DMA Bit Fields */
-#define CMT_DMA_DMA_MASK 0x1u
-#define CMT_DMA_DMA_SHIFT 0
-
-/**
- * @}
- */ /* end of group CMT_Register_Masks */
-
-
-/* CMT - Peripheral instance base addresses */
-/** Peripheral CMT base address */
-#define CMT_BASE (0x40062000u)
-/** Peripheral CMT base pointer */
-#define CMT ((CMT_Type *)CMT_BASE)
-
-/**
- * @}
- */ /* end of group CMT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CRC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
- * @{
- */
-
-/** CRC - Register Layout Typedef */
-typedef struct {
- union { /* offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
- __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
- } ACCESS16BIT;
- __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
- __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
- __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
- __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
- } ACCESS8BIT;
- };
- union { /* offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
- __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
- } GPOLY_ACCESS16BIT;
- __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
- __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
- __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
- __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
- } GPOLY_ACCESS8BIT;
- };
- union { /* offset: 0x8 */
- __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
- struct { /* offset: 0x8 */
- uint8_t RESERVED_0[3];
- __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
- } CTRL_ACCESS8BIT;
- };
-} CRC_Type;
-
-/* ----------------------------------------------------------------------------
- -- CRC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CRC_Register_Masks CRC Register Masks
- * @{
- */
-
-/* CRCL Bit Fields */
-#define CRC_CRCL_CRCL_MASK 0xFFFFu
-#define CRC_CRCL_CRCL_SHIFT 0
-#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
-/* CRCH Bit Fields */
-#define CRC_CRCH_CRCH_MASK 0xFFFFu
-#define CRC_CRCH_CRCH_SHIFT 0
-#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
-/* CRC Bit Fields */
-#define CRC_CRC_LL_MASK 0xFFu
-#define CRC_CRC_LL_SHIFT 0
-#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
-#define CRC_CRC_LU_MASK 0xFF00u
-#define CRC_CRC_LU_SHIFT 8
-#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
-#define CRC_CRC_HL_MASK 0xFF0000u
-#define CRC_CRC_HL_SHIFT 16
-#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
-#define CRC_CRC_HU_MASK 0xFF000000u
-#define CRC_CRC_HU_SHIFT 24
-#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
-/* CRCLL Bit Fields */
-#define CRC_CRCLL_CRCLL_MASK 0xFFu
-#define CRC_CRCLL_CRCLL_SHIFT 0
-#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
-/* CRCLU Bit Fields */
-#define CRC_CRCLU_CRCLU_MASK 0xFFu
-#define CRC_CRCLU_CRCLU_SHIFT 0
-#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
-/* CRCHL Bit Fields */
-#define CRC_CRCHL_CRCHL_MASK 0xFFu
-#define CRC_CRCHL_CRCHL_SHIFT 0
-#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
-/* CRCHU Bit Fields */
-#define CRC_CRCHU_CRCHU_MASK 0xFFu
-#define CRC_CRCHU_CRCHU_SHIFT 0
-#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT 0
-#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT 0
-#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK 0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT 0
-#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT 16
-#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
-#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
-#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
-#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
-#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK 0x1000000u
-#define CRC_CTRL_TCRC_SHIFT 24
-#define CRC_CTRL_WAS_MASK 0x2000000u
-#define CRC_CTRL_WAS_SHIFT 25
-#define CRC_CTRL_FXOR_MASK 0x4000000u
-#define CRC_CTRL_FXOR_SHIFT 26
-#define CRC_CTRL_TOTR_MASK 0x30000000u
-#define CRC_CTRL_TOTR_SHIFT 28
-#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK 0xC0000000u
-#define CRC_CTRL_TOT_SHIFT 30
-#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK 0x1u
-#define CRC_CTRLHU_TCRC_SHIFT 0
-#define CRC_CTRLHU_WAS_MASK 0x2u
-#define CRC_CTRLHU_WAS_SHIFT 1
-#define CRC_CTRLHU_FXOR_MASK 0x4u
-#define CRC_CTRLHU_FXOR_SHIFT 2
-#define CRC_CTRLHU_TOTR_MASK 0x30u
-#define CRC_CTRLHU_TOTR_SHIFT 4
-#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK 0xC0u
-#define CRC_CTRLHU_TOT_SHIFT 6
-#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
-
-/**
- * @}
- */ /* end of group CRC_Register_Masks */
-
-
-/* CRC - Peripheral instance base addresses */
-/** Peripheral CRC base address */
-#define CRC_BASE (0x40032000u)
-/** Peripheral CRC base pointer */
-#define CRC0 ((CRC_Type *)CRC_BASE)
-
-/**
- * @}
- */ /* end of group CRC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CR; /**< Control Register, offset: 0x0 */
- __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
- uint8_t RESERVED_0[4];
- __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
- uint8_t RESERVED_1[4];
- __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
- __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
- __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
- __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
- __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
- __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
- __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
- __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
- __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
- uint8_t RESERVED_2[4];
- __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
- uint8_t RESERVED_3[4];
- __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
- uint8_t RESERVED_4[4];
- __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
- uint8_t RESERVED_5[200];
- __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
- __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
- __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
- __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
- uint8_t RESERVED_6[3836];
- struct { /* offset: 0x1000, array step: 0x20 */
- __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
- __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
- __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
- union { /* offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
- };
- __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
- __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
- __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
- union { /* offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
- };
- __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
- __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
- union { /* offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
- };
- } TCD[4];
-} DMA_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK 0x2u
-#define DMA_CR_EDBG_SHIFT 1
-#define DMA_CR_ERCA_MASK 0x4u
-#define DMA_CR_ERCA_SHIFT 2
-#define DMA_CR_HOE_MASK 0x10u
-#define DMA_CR_HOE_SHIFT 4
-#define DMA_CR_HALT_MASK 0x20u
-#define DMA_CR_HALT_SHIFT 5
-#define DMA_CR_CLM_MASK 0x40u
-#define DMA_CR_CLM_SHIFT 6
-#define DMA_CR_EMLM_MASK 0x80u
-#define DMA_CR_EMLM_SHIFT 7
-#define DMA_CR_ECX_MASK 0x10000u
-#define DMA_CR_ECX_SHIFT 16
-#define DMA_CR_CX_MASK 0x20000u
-#define DMA_CR_CX_SHIFT 17
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK 0x1u
-#define DMA_ES_DBE_SHIFT 0
-#define DMA_ES_SBE_MASK 0x2u
-#define DMA_ES_SBE_SHIFT 1
-#define DMA_ES_SGE_MASK 0x4u
-#define DMA_ES_SGE_SHIFT 2
-#define DMA_ES_NCE_MASK 0x8u
-#define DMA_ES_NCE_SHIFT 3
-#define DMA_ES_DOE_MASK 0x10u
-#define DMA_ES_DOE_SHIFT 4
-#define DMA_ES_DAE_MASK 0x20u
-#define DMA_ES_DAE_SHIFT 5
-#define DMA_ES_SOE_MASK 0x40u
-#define DMA_ES_SOE_SHIFT 6
-#define DMA_ES_SAE_MASK 0x80u
-#define DMA_ES_SAE_SHIFT 7
-#define DMA_ES_ERRCHN_MASK 0xF00u
-#define DMA_ES_ERRCHN_SHIFT 8
-#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK 0x4000u
-#define DMA_ES_CPE_SHIFT 14
-#define DMA_ES_ECX_MASK 0x10000u
-#define DMA_ES_ECX_SHIFT 16
-#define DMA_ES_VLD_MASK 0x80000000u
-#define DMA_ES_VLD_SHIFT 31
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK 0x1u
-#define DMA_ERQ_ERQ0_SHIFT 0
-#define DMA_ERQ_ERQ1_MASK 0x2u
-#define DMA_ERQ_ERQ1_SHIFT 1
-#define DMA_ERQ_ERQ2_MASK 0x4u
-#define DMA_ERQ_ERQ2_SHIFT 2
-#define DMA_ERQ_ERQ3_MASK 0x8u
-#define DMA_ERQ_ERQ3_SHIFT 3
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK 0x1u
-#define DMA_EEI_EEI0_SHIFT 0
-#define DMA_EEI_EEI1_MASK 0x2u
-#define DMA_EEI_EEI1_SHIFT 1
-#define DMA_EEI_EEI2_MASK 0x4u
-#define DMA_EEI_EEI2_SHIFT 2
-#define DMA_EEI_EEI3_MASK 0x8u
-#define DMA_EEI_EEI3_SHIFT 3
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK 0xFu
-#define DMA_CEEI_CEEI_SHIFT 0
-#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK 0x40u
-#define DMA_CEEI_CAEE_SHIFT 6
-#define DMA_CEEI_NOP_MASK 0x80u
-#define DMA_CEEI_NOP_SHIFT 7
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK 0xFu
-#define DMA_SEEI_SEEI_SHIFT 0
-#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK 0x40u
-#define DMA_SEEI_SAEE_SHIFT 6
-#define DMA_SEEI_NOP_MASK 0x80u
-#define DMA_SEEI_NOP_SHIFT 7
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK 0xFu
-#define DMA_CERQ_CERQ_SHIFT 0
-#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK 0x40u
-#define DMA_CERQ_CAER_SHIFT 6
-#define DMA_CERQ_NOP_MASK 0x80u
-#define DMA_CERQ_NOP_SHIFT 7
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK 0xFu
-#define DMA_SERQ_SERQ_SHIFT 0
-#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK 0x40u
-#define DMA_SERQ_SAER_SHIFT 6
-#define DMA_SERQ_NOP_MASK 0x80u
-#define DMA_SERQ_NOP_SHIFT 7
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK 0xFu
-#define DMA_CDNE_CDNE_SHIFT 0
-#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK 0x40u
-#define DMA_CDNE_CADN_SHIFT 6
-#define DMA_CDNE_NOP_MASK 0x80u
-#define DMA_CDNE_NOP_SHIFT 7
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK 0xFu
-#define DMA_SSRT_SSRT_SHIFT 0
-#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK 0x40u
-#define DMA_SSRT_SAST_SHIFT 6
-#define DMA_SSRT_NOP_MASK 0x80u
-#define DMA_SSRT_NOP_SHIFT 7
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK 0xFu
-#define DMA_CERR_CERR_SHIFT 0
-#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK 0x40u
-#define DMA_CERR_CAEI_SHIFT 6
-#define DMA_CERR_NOP_MASK 0x80u
-#define DMA_CERR_NOP_SHIFT 7
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK 0xFu
-#define DMA_CINT_CINT_SHIFT 0
-#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK 0x40u
-#define DMA_CINT_CAIR_SHIFT 6
-#define DMA_CINT_NOP_MASK 0x80u
-#define DMA_CINT_NOP_SHIFT 7
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK 0x1u
-#define DMA_INT_INT0_SHIFT 0
-#define DMA_INT_INT1_MASK 0x2u
-#define DMA_INT_INT1_SHIFT 1
-#define DMA_INT_INT2_MASK 0x4u
-#define DMA_INT_INT2_SHIFT 2
-#define DMA_INT_INT3_MASK 0x8u
-#define DMA_INT_INT3_SHIFT 3
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK 0x1u
-#define DMA_ERR_ERR0_SHIFT 0
-#define DMA_ERR_ERR1_MASK 0x2u
-#define DMA_ERR_ERR1_SHIFT 1
-#define DMA_ERR_ERR2_MASK 0x4u
-#define DMA_ERR_ERR2_SHIFT 2
-#define DMA_ERR_ERR3_MASK 0x8u
-#define DMA_ERR_ERR3_SHIFT 3
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK 0x1u
-#define DMA_HRS_HRS0_SHIFT 0
-#define DMA_HRS_HRS1_MASK 0x2u
-#define DMA_HRS_HRS1_SHIFT 1
-#define DMA_HRS_HRS2_MASK 0x4u
-#define DMA_HRS_HRS2_SHIFT 2
-#define DMA_HRS_HRS3_MASK 0x8u
-#define DMA_HRS_HRS3_SHIFT 3
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK 0xFu
-#define DMA_DCHPRI3_CHPRI_SHIFT 0
-#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK 0x40u
-#define DMA_DCHPRI3_DPA_SHIFT 6
-#define DMA_DCHPRI3_ECP_MASK 0x80u
-#define DMA_DCHPRI3_ECP_SHIFT 7
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK 0xFu
-#define DMA_DCHPRI2_CHPRI_SHIFT 0
-#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK 0x40u
-#define DMA_DCHPRI2_DPA_SHIFT 6
-#define DMA_DCHPRI2_ECP_MASK 0x80u
-#define DMA_DCHPRI2_ECP_SHIFT 7
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK 0xFu
-#define DMA_DCHPRI1_CHPRI_SHIFT 0
-#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK 0x40u
-#define DMA_DCHPRI1_DPA_SHIFT 6
-#define DMA_DCHPRI1_ECP_MASK 0x80u
-#define DMA_DCHPRI1_ECP_SHIFT 7
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK 0xFu
-#define DMA_DCHPRI0_CHPRI_SHIFT 0
-#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK 0x40u
-#define DMA_DCHPRI0_DPA_SHIFT 6
-#define DMA_DCHPRI0_ECP_MASK 0x80u
-#define DMA_DCHPRI0_ECP_SHIFT 7
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT 0
-#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK 0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT 0
-#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK 0x7u
-#define DMA_ATTR_DSIZE_SHIFT 0
-#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK 0xF8u
-#define DMA_ATTR_DMOD_SHIFT 3
-#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK 0x700u
-#define DMA_ATTR_SSIZE_SHIFT 8
-#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK 0xF800u
-#define DMA_ATTR_SMOD_SHIFT 11
-#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
-#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT 0
-#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT 0
-#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK 0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT 0
-#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT 0
-#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT 0
-#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
-#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK 0x1u
-#define DMA_CSR_START_SHIFT 0
-#define DMA_CSR_INTMAJOR_MASK 0x2u
-#define DMA_CSR_INTMAJOR_SHIFT 1
-#define DMA_CSR_INTHALF_MASK 0x4u
-#define DMA_CSR_INTHALF_SHIFT 2
-#define DMA_CSR_DREQ_MASK 0x8u
-#define DMA_CSR_DREQ_SHIFT 3
-#define DMA_CSR_ESG_MASK 0x10u
-#define DMA_CSR_ESG_SHIFT 4
-#define DMA_CSR_MAJORELINK_MASK 0x20u
-#define DMA_CSR_MAJORELINK_SHIFT 5
-#define DMA_CSR_ACTIVE_MASK 0x40u
-#define DMA_CSR_ACTIVE_SHIFT 6
-#define DMA_CSR_DONE_MASK 0x80u
-#define DMA_CSR_DONE_SHIFT 7
-#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
-#define DMA_CSR_MAJORLINKCH_SHIFT 8
-#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK 0xC000u
-#define DMA_CSR_BWC_SHIFT 14
-#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT 0
-#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT 0
-#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
-
-/**
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA base address */
-#define DMA_BASE (0x40008000u)
-/** Peripheral DMA base pointer */
-#define DMA0 ((DMA_Type *)DMA_BASE)
-
-/**
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
- * @{
- */
-
-/** DMAMUX - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
- * @{
- */
-
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-
-/**
- * @}
- */ /* end of group DMAMUX_Register_Masks */
-
-
-/* DMAMUX - Peripheral instance base addresses */
-/** Peripheral DMAMUX base address */
-#define DMAMUX_BASE (0x40021000u)
-/** Peripheral DMAMUX base pointer */
-#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
-
-/**
- * @}
- */ /* end of group DMAMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- EWM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
- * @{
- */
-
-/** EWM - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
- __O uint8_t SERV; /**< Service Register, offset: 0x1 */
- __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
- __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
-} EWM_Type;
-
-/* ----------------------------------------------------------------------------
- -- EWM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
-
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK 0x1u
-#define EWM_CTRL_EWMEN_SHIFT 0
-#define EWM_CTRL_ASSIN_MASK 0x2u
-#define EWM_CTRL_ASSIN_SHIFT 1
-#define EWM_CTRL_INEN_MASK 0x4u
-#define EWM_CTRL_INEN_SHIFT 2
-#define EWM_CTRL_INTEN_MASK 0x8u
-#define EWM_CTRL_INTEN_SHIFT 3
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK 0xFFu
-#define EWM_SERV_SERVICE_SHIFT 0
-#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK 0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT 0
-#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK 0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT 0
-#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
-
-/**
- * @}
- */ /* end of group EWM_Register_Masks */
-
-
-/* EWM - Peripheral instance base addresses */
-/** Peripheral EWM base address */
-#define EWM_BASE (0x40061000u)
-/** Peripheral EWM base pointer */
-#define EWM ((EWM_Type *)EWM_BASE)
-
-/**
- * @}
- */ /* end of group EWM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
- * @{
- */
-
-/** FMC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
- __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
- uint8_t RESERVED_0[248];
- struct { /* offset: 0x100, array step: 0x20 */
- __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
- uint8_t RESERVED_0[24];
- } TAG_WAY[4];
- uint8_t RESERVED_1[132];
- struct { /* offset: 0x204, array step: 0x8 */
- __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW0S[2];
- uint8_t RESERVED_2[48];
- struct { /* offset: 0x244, array step: 0x8 */
- __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW1S[2];
- uint8_t RESERVED_3[48];
- struct { /* offset: 0x284, array step: 0x8 */
- __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW2S[2];
- uint8_t RESERVED_4[48];
- struct { /* offset: 0x2C4, array step: 0x8 */
- __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW3S[2];
-} FMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- FMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FMC_Register_Masks FMC Register Masks
- * @{
- */
-
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK 0x3u
-#define FMC_PFAPR_M0AP_SHIFT 0
-#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK 0xCu
-#define FMC_PFAPR_M1AP_SHIFT 2
-#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK 0x30u
-#define FMC_PFAPR_M2AP_SHIFT 4
-#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK 0xC0u
-#define FMC_PFAPR_M3AP_SHIFT 6
-#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK 0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT 16
-#define FMC_PFAPR_M1PFD_MASK 0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT 17
-#define FMC_PFAPR_M2PFD_MASK 0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT 18
-#define FMC_PFAPR_M3PFD_MASK 0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT 19
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK 0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT 0
-#define FMC_PFB0CR_B0IPE_MASK 0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT 1
-#define FMC_PFB0CR_B0DPE_MASK 0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT 2
-#define FMC_PFB0CR_B0ICE_MASK 0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT 3
-#define FMC_PFB0CR_B0DCE_MASK 0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT 4
-#define FMC_PFB0CR_CRC_MASK 0xE0u
-#define FMC_PFB0CR_CRC_SHIFT 5
-#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK 0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT 17
-#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT 19
-#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT 20
-#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
-#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT 28
-#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* TAGVD Bit Fields */
-#define FMC_TAGVD_valid_MASK 0x1u
-#define FMC_TAGVD_valid_SHIFT 0
-#define FMC_TAGVD_tag_MASK 0x7FFC0u
-#define FMC_TAGVD_tag_SHIFT 6
-#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
-/* DATAW0S Bit Fields */
-#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW0S_data_SHIFT 0
-#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
-/* DATAW1S Bit Fields */
-#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW1S_data_SHIFT 0
-#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
-/* DATAW2S Bit Fields */
-#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW2S_data_SHIFT 0
-#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
-/* DATAW3S Bit Fields */
-#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW3S_data_SHIFT 0
-#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
-
-/**
- * @}
- */ /* end of group FMC_Register_Masks */
-
-
-/* FMC - Peripheral instance base addresses */
-/** Peripheral FMC base address */
-#define FMC_BASE (0x4001F000u)
-/** Peripheral FMC base pointer */
-#define FMC ((FMC_Type *)FMC_BASE)
-
-/**
- * @}
- */ /* end of group FMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFL Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
- * @{
- */
-
-/** FTFL - Register Layout Typedef */
-typedef struct {
- __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
- __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
- __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
- __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
- __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
- __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
- __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
- __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
- __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
- __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
- __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
- __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
- __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
- __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
- __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
- __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
- __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
- __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
- __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
- __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
- uint8_t RESERVED_0[2];
- __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
- __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
-} FTFL_Type;
-
-/* ----------------------------------------------------------------------------
- -- FTFL Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFL_Register_Masks FTFL Register Masks
- * @{
- */
-
-/* FSTAT Bit Fields */
-#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFL_FSTAT_MGSTAT0_SHIFT 0
-#define FTFL_FSTAT_FPVIOL_MASK 0x10u
-#define FTFL_FSTAT_FPVIOL_SHIFT 4
-#define FTFL_FSTAT_ACCERR_MASK 0x20u
-#define FTFL_FSTAT_ACCERR_SHIFT 5
-#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFL_FSTAT_RDCOLERR_SHIFT 6
-#define FTFL_FSTAT_CCIF_MASK 0x80u
-#define FTFL_FSTAT_CCIF_SHIFT 7
-/* FCNFG Bit Fields */
-#define FTFL_FCNFG_EEERDY_MASK 0x1u
-#define FTFL_FCNFG_EEERDY_SHIFT 0
-#define FTFL_FCNFG_RAMRDY_MASK 0x2u
-#define FTFL_FCNFG_RAMRDY_SHIFT 1
-#define FTFL_FCNFG_PFLSH_MASK 0x4u
-#define FTFL_FCNFG_PFLSH_SHIFT 2
-#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFL_FCNFG_ERSSUSP_SHIFT 4
-#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFL_FCNFG_ERSAREQ_SHIFT 5
-#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFL_FCNFG_CCIE_MASK 0x80u
-#define FTFL_FCNFG_CCIE_SHIFT 7
-/* FSEC Bit Fields */
-#define FTFL_FSEC_SEC_MASK 0x3u
-#define FTFL_FSEC_SEC_SHIFT 0
-#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
-#define FTFL_FSEC_FSLACC_MASK 0xCu
-#define FTFL_FSEC_FSLACC_SHIFT 2
-#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
-#define FTFL_FSEC_MEEN_MASK 0x30u
-#define FTFL_FSEC_MEEN_SHIFT 4
-#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
-#define FTFL_FSEC_KEYEN_MASK 0xC0u
-#define FTFL_FSEC_KEYEN_SHIFT 6
-#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFL_FOPT_OPT_MASK 0xFFu
-#define FTFL_FOPT_OPT_SHIFT 0
-#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB3_CCOBn_SHIFT 0
-#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB2_CCOBn_SHIFT 0
-#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB1_CCOBn_SHIFT 0
-#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB0_CCOBn_SHIFT 0
-#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB7_CCOBn_SHIFT 0
-#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB6_CCOBn_SHIFT 0
-#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB5_CCOBn_SHIFT 0
-#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB4_CCOBn_SHIFT 0
-#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFL_FCCOBB_CCOBn_SHIFT 0
-#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFL_FCCOBA_CCOBn_SHIFT 0
-#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB9_CCOBn_SHIFT 0
-#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB8_CCOBn_SHIFT 0
-#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFL_FPROT3_PROT_MASK 0xFFu
-#define FTFL_FPROT3_PROT_SHIFT 0
-#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFL_FPROT2_PROT_MASK 0xFFu
-#define FTFL_FPROT2_PROT_SHIFT 0
-#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFL_FPROT1_PROT_MASK 0xFFu
-#define FTFL_FPROT1_PROT_SHIFT 0
-#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFL_FPROT0_PROT_MASK 0xFFu
-#define FTFL_FPROT0_PROT_SHIFT 0
-#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
-/* FEPROT Bit Fields */
-#define FTFL_FEPROT_EPROT_MASK 0xFFu
-#define FTFL_FEPROT_EPROT_SHIFT 0
-#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define FTFL_FDPROT_DPROT_MASK 0xFFu
-#define FTFL_FDPROT_DPROT_SHIFT 0
-#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
-
-/**
- * @}
- */ /* end of group FTFL_Register_Masks */
-
-
-/* FTFL - Peripheral instance base addresses */
-/** Peripheral FTFL base address */
-#define FTFL_BASE (0x40020000u)
-/** Peripheral FTFL base pointer */
-#define FTFL ((FTFL_Type *)FTFL_BASE)
-
-/**
- * @}
- */ /* end of group FTFL_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
- * @{
- */
-
-/** FTM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
- __IO uint32_t CNT; /**< Counter, offset: 0x4 */
- __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
- struct { /* offset: 0xC, array step: 0x8 */
- __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
- __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
- } CONTROLS[8];
- __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
- __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
- __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
- __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
- __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
- __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
- __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
- __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
- __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
- __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
- __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
- __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
- __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
- __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
- __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
- __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
- __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
- __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
- __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
- __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type;
-
-/* ----------------------------------------------------------------------------
- -- FTM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTM_Register_Masks FTM Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK 0x7u
-#define FTM_SC_PS_SHIFT 0
-#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK 0x18u
-#define FTM_SC_CLKS_SHIFT 3
-#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK 0x20u
-#define FTM_SC_CPWMS_SHIFT 5
-#define FTM_SC_TOIE_MASK 0x40u
-#define FTM_SC_TOIE_SHIFT 6
-#define FTM_SC_TOF_MASK 0x80u
-#define FTM_SC_TOF_SHIFT 7
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK 0xFFFFu
-#define FTM_CNT_COUNT_SHIFT 0
-#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK 0xFFFFu
-#define FTM_MOD_MOD_SHIFT 0
-#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK 0x1u
-#define FTM_CnSC_DMA_SHIFT 0
-#define FTM_CnSC_ELSA_MASK 0x4u
-#define FTM_CnSC_ELSA_SHIFT 2
-#define FTM_CnSC_ELSB_MASK 0x8u
-#define FTM_CnSC_ELSB_SHIFT 3
-#define FTM_CnSC_MSA_MASK 0x10u
-#define FTM_CnSC_MSA_SHIFT 4
-#define FTM_CnSC_MSB_MASK 0x20u
-#define FTM_CnSC_MSB_SHIFT 5
-#define FTM_CnSC_CHIE_MASK 0x40u
-#define FTM_CnSC_CHIE_SHIFT 6
-#define FTM_CnSC_CHF_MASK 0x80u
-#define FTM_CnSC_CHF_SHIFT 7
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK 0xFFFFu
-#define FTM_CnV_VAL_SHIFT 0
-#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK 0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT 0
-#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK 0x1u
-#define FTM_STATUS_CH0F_SHIFT 0
-#define FTM_STATUS_CH1F_MASK 0x2u
-#define FTM_STATUS_CH1F_SHIFT 1
-#define FTM_STATUS_CH2F_MASK 0x4u
-#define FTM_STATUS_CH2F_SHIFT 2
-#define FTM_STATUS_CH3F_MASK 0x8u
-#define FTM_STATUS_CH3F_SHIFT 3
-#define FTM_STATUS_CH4F_MASK 0x10u
-#define FTM_STATUS_CH4F_SHIFT 4
-#define FTM_STATUS_CH5F_MASK 0x20u
-#define FTM_STATUS_CH5F_SHIFT 5
-#define FTM_STATUS_CH6F_MASK 0x40u
-#define FTM_STATUS_CH6F_SHIFT 6
-#define FTM_STATUS_CH7F_MASK 0x80u
-#define FTM_STATUS_CH7F_SHIFT 7
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK 0x1u
-#define FTM_MODE_FTMEN_SHIFT 0
-#define FTM_MODE_INIT_MASK 0x2u
-#define FTM_MODE_INIT_SHIFT 1
-#define FTM_MODE_WPDIS_MASK 0x4u
-#define FTM_MODE_WPDIS_SHIFT 2
-#define FTM_MODE_PWMSYNC_MASK 0x8u
-#define FTM_MODE_PWMSYNC_SHIFT 3
-#define FTM_MODE_CAPTEST_MASK 0x10u
-#define FTM_MODE_CAPTEST_SHIFT 4
-#define FTM_MODE_FAULTM_MASK 0x60u
-#define FTM_MODE_FAULTM_SHIFT 5
-#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK 0x80u
-#define FTM_MODE_FAULTIE_SHIFT 7
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK 0x1u
-#define FTM_SYNC_CNTMIN_SHIFT 0
-#define FTM_SYNC_CNTMAX_MASK 0x2u
-#define FTM_SYNC_CNTMAX_SHIFT 1
-#define FTM_SYNC_REINIT_MASK 0x4u
-#define FTM_SYNC_REINIT_SHIFT 2
-#define FTM_SYNC_SYNCHOM_MASK 0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT 3
-#define FTM_SYNC_TRIG0_MASK 0x10u
-#define FTM_SYNC_TRIG0_SHIFT 4
-#define FTM_SYNC_TRIG1_MASK 0x20u
-#define FTM_SYNC_TRIG1_SHIFT 5
-#define FTM_SYNC_TRIG2_MASK 0x40u
-#define FTM_SYNC_TRIG2_SHIFT 6
-#define FTM_SYNC_SWSYNC_MASK 0x80u
-#define FTM_SYNC_SWSYNC_SHIFT 7
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK 0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT 0
-#define FTM_OUTINIT_CH1OI_MASK 0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT 1
-#define FTM_OUTINIT_CH2OI_MASK 0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT 2
-#define FTM_OUTINIT_CH3OI_MASK 0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT 3
-#define FTM_OUTINIT_CH4OI_MASK 0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT 4
-#define FTM_OUTINIT_CH5OI_MASK 0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT 5
-#define FTM_OUTINIT_CH6OI_MASK 0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT 6
-#define FTM_OUTINIT_CH7OI_MASK 0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT 7
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK 0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT 0
-#define FTM_OUTMASK_CH1OM_MASK 0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT 1
-#define FTM_OUTMASK_CH2OM_MASK 0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT 2
-#define FTM_OUTMASK_CH3OM_MASK 0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT 3
-#define FTM_OUTMASK_CH4OM_MASK 0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT 4
-#define FTM_OUTMASK_CH5OM_MASK 0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT 5
-#define FTM_OUTMASK_CH6OM_MASK 0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT 6
-#define FTM_OUTMASK_CH7OM_MASK 0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT 7
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK 0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT 0
-#define FTM_COMBINE_COMP0_MASK 0x2u
-#define FTM_COMBINE_COMP0_SHIFT 1
-#define FTM_COMBINE_DECAPEN0_MASK 0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT 2
-#define FTM_COMBINE_DECAP0_MASK 0x8u
-#define FTM_COMBINE_DECAP0_SHIFT 3
-#define FTM_COMBINE_DTEN0_MASK 0x10u
-#define FTM_COMBINE_DTEN0_SHIFT 4
-#define FTM_COMBINE_SYNCEN0_MASK 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT 5
-#define FTM_COMBINE_FAULTEN0_MASK 0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT 6
-#define FTM_COMBINE_COMBINE1_MASK 0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT 8
-#define FTM_COMBINE_COMP1_MASK 0x200u
-#define FTM_COMBINE_COMP1_SHIFT 9
-#define FTM_COMBINE_DECAPEN1_MASK 0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT 10
-#define FTM_COMBINE_DECAP1_MASK 0x800u
-#define FTM_COMBINE_DECAP1_SHIFT 11
-#define FTM_COMBINE_DTEN1_MASK 0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT 12
-#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT 13
-#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT 14
-#define FTM_COMBINE_COMBINE2_MASK 0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT 16
-#define FTM_COMBINE_COMP2_MASK 0x20000u
-#define FTM_COMBINE_COMP2_SHIFT 17
-#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT 18
-#define FTM_COMBINE_DECAP2_MASK 0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT 19
-#define FTM_COMBINE_DTEN2_MASK 0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT 20
-#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT 21
-#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT 22
-#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT 24
-#define FTM_COMBINE_COMP3_MASK 0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT 25
-#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT 26
-#define FTM_COMBINE_DECAP3_MASK 0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT 27
-#define FTM_COMBINE_DTEN3_MASK 0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT 28
-#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT 29
-#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT 30
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT 0
-#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK 0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT 6
-#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
-#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
-#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
-#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
-#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
-#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
-#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
-#define FTM_EXTTRIG_TRIGF_MASK 0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT 7
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK 0x1u
-#define FTM_POL_POL0_SHIFT 0
-#define FTM_POL_POL1_MASK 0x2u
-#define FTM_POL_POL1_SHIFT 1
-#define FTM_POL_POL2_MASK 0x4u
-#define FTM_POL_POL2_SHIFT 2
-#define FTM_POL_POL3_MASK 0x8u
-#define FTM_POL_POL3_SHIFT 3
-#define FTM_POL_POL4_MASK 0x10u
-#define FTM_POL_POL4_SHIFT 4
-#define FTM_POL_POL5_MASK 0x20u
-#define FTM_POL_POL5_SHIFT 5
-#define FTM_POL_POL6_MASK 0x40u
-#define FTM_POL_POL6_SHIFT 6
-#define FTM_POL_POL7_MASK 0x80u
-#define FTM_POL_POL7_SHIFT 7
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK 0x1u
-#define FTM_FMS_FAULTF0_SHIFT 0
-#define FTM_FMS_FAULTF1_MASK 0x2u
-#define FTM_FMS_FAULTF1_SHIFT 1
-#define FTM_FMS_FAULTF2_MASK 0x4u
-#define FTM_FMS_FAULTF2_SHIFT 2
-#define FTM_FMS_FAULTF3_MASK 0x8u
-#define FTM_FMS_FAULTF3_SHIFT 3
-#define FTM_FMS_FAULTIN_MASK 0x20u
-#define FTM_FMS_FAULTIN_SHIFT 5
-#define FTM_FMS_WPEN_MASK 0x40u
-#define FTM_FMS_WPEN_SHIFT 6
-#define FTM_FMS_FAULTF_MASK 0x80u
-#define FTM_FMS_FAULTF_SHIFT 7
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK 0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT 0
-#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK 0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT 4
-#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK 0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT 8
-#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK 0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT 12
-#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
-#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
-#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
-#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
-#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
-#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
-#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
-#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
-#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT 8
-#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK 0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT 0
-#define FTM_QDCTRL_TOFDIR_MASK 0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT 1
-#define FTM_QDCTRL_QUADIR_MASK 0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT 2
-#define FTM_QDCTRL_QUADMODE_MASK 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT 3
-#define FTM_QDCTRL_PHBPOL_MASK 0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT 4
-#define FTM_QDCTRL_PHAPOL_MASK 0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT 5
-#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
-#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK 0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT 0
-#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK 0xC0u
-#define FTM_CONF_BDMMODE_SHIFT 6
-#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK 0x200u
-#define FTM_CONF_GTBEEN_SHIFT 9
-#define FTM_CONF_GTBEOUT_MASK 0x400u
-#define FTM_CONF_GTBEOUT_SHIFT 10
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK 0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT 0
-#define FTM_FLTPOL_FLT1POL_MASK 0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT 1
-#define FTM_FLTPOL_FLT2POL_MASK 0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT 2
-#define FTM_FLTPOL_FLT3POL_MASK 0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT 3
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
-#define FTM_SYNCONF_CNTINC_MASK 0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT 2
-#define FTM_SYNCONF_INVC_MASK 0x10u
-#define FTM_SYNCONF_INVC_SHIFT 4
-#define FTM_SYNCONF_SWOC_MASK 0x20u
-#define FTM_SYNCONF_SWOC_SHIFT 5
-#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT 7
-#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
-#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT 9
-#define FTM_SYNCONF_SWOM_MASK 0x400u
-#define FTM_SYNCONF_SWOM_SHIFT 10
-#define FTM_SYNCONF_SWINVC_MASK 0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT 11
-#define FTM_SYNCONF_SWSOC_MASK 0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT 12
-#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
-#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT 17
-#define FTM_SYNCONF_HWOM_MASK 0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT 18
-#define FTM_SYNCONF_HWINVC_MASK 0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT 19
-#define FTM_SYNCONF_HWSOC_MASK 0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT 20
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK 0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT 0
-#define FTM_INVCTRL_INV1EN_MASK 0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT 1
-#define FTM_INVCTRL_INV2EN_MASK 0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT 2
-#define FTM_INVCTRL_INV3EN_MASK 0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT 3
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK 0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT 0
-#define FTM_SWOCTRL_CH1OC_MASK 0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT 1
-#define FTM_SWOCTRL_CH2OC_MASK 0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT 2
-#define FTM_SWOCTRL_CH3OC_MASK 0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT 3
-#define FTM_SWOCTRL_CH4OC_MASK 0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT 4
-#define FTM_SWOCTRL_CH5OC_MASK 0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT 5
-#define FTM_SWOCTRL_CH6OC_MASK 0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT 6
-#define FTM_SWOCTRL_CH7OC_MASK 0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT 7
-#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT 8
-#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT 9
-#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT 10
-#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT 11
-#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT 12
-#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT 13
-#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT 14
-#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT 15
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT 0
-#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT 1
-#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT 2
-#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT 3
-#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT 4
-#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT 5
-#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT 6
-#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT 7
-#define FTM_PWMLOAD_LDOK_MASK 0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT 9
-
-/**
- * @}
- */ /* end of group FTM_Register_Masks */
-
-
-/* FTM - Peripheral instance base addresses */
-/** Peripheral FTM0 base address */
-#define FTM0_BASE (0x40038000u)
-/** Peripheral FTM0 base pointer */
-#define FTM0 ((FTM_Type *)FTM0_BASE)
-/** Peripheral FTM1 base address */
-#define FTM1_BASE (0x40039000u)
-/** Peripheral FTM1 base pointer */
-#define FTM1 ((FTM_Type *)FTM1_BASE)
-
-/**
- * @}
- */ /* end of group FTM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type;
-
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-/** Peripheral PTC base address */
-#define PTC_BASE (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC ((GPIO_Type *)PTC_BASE)
-/** Peripheral PTD base address */
-#define PTD_BASE (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD ((GPIO_Type *)PTD_BASE)
-/** Peripheral PTE base address */
-#define PTE_BASE (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE ((GPIO_Type *)PTE_BASE)
-
-/**
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
- __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
- __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
- __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
- __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
- __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
- __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
- __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
- __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
- __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
- __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
- __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
- __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2C Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0x1Fu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-
-/**
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40066000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-
-/**
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2S Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
- * @{
- */
-
-/** I2S - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
- __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
- __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
- __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
- __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
- __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
- uint8_t RESERVED_0[8];
- __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[24];
- __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_2[24];
- __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
- uint8_t RESERVED_3[28];
- __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
- __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
- __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
- __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
- __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
- __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
- uint8_t RESERVED_4[8];
- __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
- uint8_t RESERVED_5[24];
- __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_6[24];
- __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
- uint8_t RESERVED_7[28];
- __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
- __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
-} I2S_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2S Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2S_Register_Masks I2S Register Masks
- * @{
- */
-
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK 0x1u
-#define I2S_TCSR_FRDE_SHIFT 0
-#define I2S_TCSR_FWDE_MASK 0x2u
-#define I2S_TCSR_FWDE_SHIFT 1
-#define I2S_TCSR_FRIE_MASK 0x100u
-#define I2S_TCSR_FRIE_SHIFT 8
-#define I2S_TCSR_FWIE_MASK 0x200u
-#define I2S_TCSR_FWIE_SHIFT 9
-#define I2S_TCSR_FEIE_MASK 0x400u
-#define I2S_TCSR_FEIE_SHIFT 10
-#define I2S_TCSR_SEIE_MASK 0x800u
-#define I2S_TCSR_SEIE_SHIFT 11
-#define I2S_TCSR_WSIE_MASK 0x1000u
-#define I2S_TCSR_WSIE_SHIFT 12
-#define I2S_TCSR_FRF_MASK 0x10000u
-#define I2S_TCSR_FRF_SHIFT 16
-#define I2S_TCSR_FWF_MASK 0x20000u
-#define I2S_TCSR_FWF_SHIFT 17
-#define I2S_TCSR_FEF_MASK 0x40000u
-#define I2S_TCSR_FEF_SHIFT 18
-#define I2S_TCSR_SEF_MASK 0x80000u
-#define I2S_TCSR_SEF_SHIFT 19
-#define I2S_TCSR_WSF_MASK 0x100000u
-#define I2S_TCSR_WSF_SHIFT 20
-#define I2S_TCSR_SR_MASK 0x1000000u
-#define I2S_TCSR_SR_SHIFT 24
-#define I2S_TCSR_FR_MASK 0x2000000u
-#define I2S_TCSR_FR_SHIFT 25
-#define I2S_TCSR_BCE_MASK 0x10000000u
-#define I2S_TCSR_BCE_SHIFT 28
-#define I2S_TCSR_DBGE_MASK 0x20000000u
-#define I2S_TCSR_DBGE_SHIFT 29
-#define I2S_TCSR_STOPE_MASK 0x40000000u
-#define I2S_TCSR_STOPE_SHIFT 30
-#define I2S_TCSR_TE_MASK 0x80000000u
-#define I2S_TCSR_TE_SHIFT 31
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK 0x7u
-#define I2S_TCR1_TFW_SHIFT 0
-#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK 0xFFu
-#define I2S_TCR2_DIV_SHIFT 0
-#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK 0x1000000u
-#define I2S_TCR2_BCD_SHIFT 24
-#define I2S_TCR2_BCP_MASK 0x2000000u
-#define I2S_TCR2_BCP_SHIFT 25
-#define I2S_TCR2_MSEL_MASK 0xC000000u
-#define I2S_TCR2_MSEL_SHIFT 26
-#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK 0x10000000u
-#define I2S_TCR2_BCI_SHIFT 28
-#define I2S_TCR2_BCS_MASK 0x20000000u
-#define I2S_TCR2_BCS_SHIFT 29
-#define I2S_TCR2_SYNC_MASK 0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT 30
-#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK 0x1Fu
-#define I2S_TCR3_WDFL_SHIFT 0
-#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK 0x30000u
-#define I2S_TCR3_TCE_SHIFT 16
-#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK 0x1u
-#define I2S_TCR4_FSD_SHIFT 0
-#define I2S_TCR4_FSP_MASK 0x2u
-#define I2S_TCR4_FSP_SHIFT 1
-#define I2S_TCR4_FSE_MASK 0x8u
-#define I2S_TCR4_FSE_SHIFT 3
-#define I2S_TCR4_MF_MASK 0x10u
-#define I2S_TCR4_MF_SHIFT 4
-#define I2S_TCR4_SYWD_MASK 0x1F00u
-#define I2S_TCR4_SYWD_SHIFT 8
-#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK 0x1F0000u
-#define I2S_TCR4_FRSZ_SHIFT 16
-#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK 0x1F00u
-#define I2S_TCR5_FBT_SHIFT 8
-#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK 0x1F0000u
-#define I2S_TCR5_W0W_SHIFT 16
-#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK 0x1F000000u
-#define I2S_TCR5_WNW_SHIFT 24
-#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT 0
-#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK 0xFu
-#define I2S_TFR_RFP_SHIFT 0
-#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK 0xF0000u
-#define I2S_TFR_WFP_SHIFT 16
-#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
-#define I2S_TMR_TWM_SHIFT 0
-#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK 0x1u
-#define I2S_RCSR_FRDE_SHIFT 0
-#define I2S_RCSR_FWDE_MASK 0x2u
-#define I2S_RCSR_FWDE_SHIFT 1
-#define I2S_RCSR_FRIE_MASK 0x100u
-#define I2S_RCSR_FRIE_SHIFT 8
-#define I2S_RCSR_FWIE_MASK 0x200u
-#define I2S_RCSR_FWIE_SHIFT 9
-#define I2S_RCSR_FEIE_MASK 0x400u
-#define I2S_RCSR_FEIE_SHIFT 10
-#define I2S_RCSR_SEIE_MASK 0x800u
-#define I2S_RCSR_SEIE_SHIFT 11
-#define I2S_RCSR_WSIE_MASK 0x1000u
-#define I2S_RCSR_WSIE_SHIFT 12
-#define I2S_RCSR_FRF_MASK 0x10000u
-#define I2S_RCSR_FRF_SHIFT 16
-#define I2S_RCSR_FWF_MASK 0x20000u
-#define I2S_RCSR_FWF_SHIFT 17
-#define I2S_RCSR_FEF_MASK 0x40000u
-#define I2S_RCSR_FEF_SHIFT 18
-#define I2S_RCSR_SEF_MASK 0x80000u
-#define I2S_RCSR_SEF_SHIFT 19
-#define I2S_RCSR_WSF_MASK 0x100000u
-#define I2S_RCSR_WSF_SHIFT 20
-#define I2S_RCSR_SR_MASK 0x1000000u
-#define I2S_RCSR_SR_SHIFT 24
-#define I2S_RCSR_FR_MASK 0x2000000u
-#define I2S_RCSR_FR_SHIFT 25
-#define I2S_RCSR_BCE_MASK 0x10000000u
-#define I2S_RCSR_BCE_SHIFT 28
-#define I2S_RCSR_DBGE_MASK 0x20000000u
-#define I2S_RCSR_DBGE_SHIFT 29
-#define I2S_RCSR_STOPE_MASK 0x40000000u
-#define I2S_RCSR_STOPE_SHIFT 30
-#define I2S_RCSR_RE_MASK 0x80000000u
-#define I2S_RCSR_RE_SHIFT 31
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK 0x7u
-#define I2S_RCR1_RFW_SHIFT 0
-#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK 0xFFu
-#define I2S_RCR2_DIV_SHIFT 0
-#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK 0x1000000u
-#define I2S_RCR2_BCD_SHIFT 24
-#define I2S_RCR2_BCP_MASK 0x2000000u
-#define I2S_RCR2_BCP_SHIFT 25
-#define I2S_RCR2_MSEL_MASK 0xC000000u
-#define I2S_RCR2_MSEL_SHIFT 26
-#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK 0x10000000u
-#define I2S_RCR2_BCI_SHIFT 28
-#define I2S_RCR2_BCS_MASK 0x20000000u
-#define I2S_RCR2_BCS_SHIFT 29
-#define I2S_RCR2_SYNC_MASK 0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT 30
-#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK 0x1Fu
-#define I2S_RCR3_WDFL_SHIFT 0
-#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK 0x30000u
-#define I2S_RCR3_RCE_SHIFT 16
-#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK 0x1u
-#define I2S_RCR4_FSD_SHIFT 0
-#define I2S_RCR4_FSP_MASK 0x2u
-#define I2S_RCR4_FSP_SHIFT 1
-#define I2S_RCR4_FSE_MASK 0x8u
-#define I2S_RCR4_FSE_SHIFT 3
-#define I2S_RCR4_MF_MASK 0x10u
-#define I2S_RCR4_MF_SHIFT 4
-#define I2S_RCR4_SYWD_MASK 0x1F00u
-#define I2S_RCR4_SYWD_SHIFT 8
-#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK 0x1F0000u
-#define I2S_RCR4_FRSZ_SHIFT 16
-#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK 0x1F00u
-#define I2S_RCR5_FBT_SHIFT 8
-#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK 0x1F0000u
-#define I2S_RCR5_W0W_SHIFT 16
-#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK 0x1F000000u
-#define I2S_RCR5_WNW_SHIFT 24
-#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT 0
-#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK 0xFu
-#define I2S_RFR_RFP_SHIFT 0
-#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK 0xF0000u
-#define I2S_RFR_WFP_SHIFT 16
-#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
-#define I2S_RMR_RWM_SHIFT 0
-#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK 0x3000000u
-#define I2S_MCR_MICS_SHIFT 24
-#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK 0x40000000u
-#define I2S_MCR_MOE_SHIFT 30
-#define I2S_MCR_DUF_MASK 0x80000000u
-#define I2S_MCR_DUF_SHIFT 31
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK 0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT 0
-#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK 0xFF000u
-#define I2S_MDR_FRACT_SHIFT 12
-#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
-
-/**
- * @}
- */ /* end of group I2S_Register_Masks */
-
-
-/* I2S - Peripheral instance base addresses */
-/** Peripheral I2S0 base address */
-#define I2S0_BASE (0x4002F000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0 ((I2S_Type *)I2S0_BASE)
-
-/**
- * @}
- */ /* end of group I2S_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
- * @{
- */
-
-/** LLWU - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
- __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
- __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
- __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
- __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
- __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
- __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
- __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
- __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
- __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
- __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
-} LLWU_Type;
-
-/* ----------------------------------------------------------------------------
- -- LLWU Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Register_Masks LLWU Register Masks
- * @{
- */
-
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-/* RST Bit Fields */
-#define LLWU_RST_RSTFILT_MASK 0x1u
-#define LLWU_RST_RSTFILT_SHIFT 0
-#define LLWU_RST_LLRSTE_MASK 0x2u
-#define LLWU_RST_LLRSTE_SHIFT 1
-
-/**
- * @}
- */ /* end of group LLWU_Register_Masks */
-
-
-/* LLWU - Peripheral instance base addresses */
-/** Peripheral LLWU base address */
-#define LLWU_BASE (0x4007C000u)
-/** Peripheral LLWU base pointer */
-#define LLWU ((LLWU_Type *)LLWU_BASE)
-
-/**
- * @}
- */ /* end of group LLWU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
- * @{
- */
-
-/** LPTMR - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
- __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
- __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
- __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
- * @{
- */
-
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-
-/**
- * @}
- */ /* end of group LPTMR_Register_Masks */
-
-
-/* LPTMR - Peripheral instance base addresses */
-/** Peripheral LPTMR0 base address */
-#define LPTMR0_BASE (0x40040000u)
-/** Peripheral LPTMR0 base pointer */
-#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-
-/**
- * @}
- */ /* end of group LPTMR_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
- * @{
- */
-
-/** MCG - Register Layout Typedef */
-typedef struct {
- __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
- __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
- __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
- __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
- __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
- __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
- __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
- uint8_t RESERVED_0[1];
- __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
- uint8_t RESERVED_1[1];
- __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
- __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
- __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
- __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
-} MCG_Type;
-
-/* ----------------------------------------------------------------------------
- -- MCG Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Register_Masks MCG Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_EREFS0_MASK 0x4u
-#define MCG_C2_EREFS0_SHIFT 2
-#define MCG_C2_HGO0_MASK 0x8u
-#define MCG_C2_HGO0_SHIFT 3
-#define MCG_C2_RANGE0_MASK 0x30u
-#define MCG_C2_RANGE0_SHIFT 4
-#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK 0x1Fu
-#define MCG_C5_PRDIV0_SHIFT 0
-#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK 0x20u
-#define MCG_C5_PLLSTEN0_SHIFT 5
-#define MCG_C5_PLLCLKEN0_MASK 0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT 6
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK 0x1Fu
-#define MCG_C6_VDIV0_SHIFT 0
-#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK 0x20u
-#define MCG_C6_CME0_SHIFT 5
-#define MCG_C6_PLLS_MASK 0x40u
-#define MCG_C6_PLLS_SHIFT 6
-#define MCG_C6_LOLIE0_MASK 0x80u
-#define MCG_C6_LOLIE0_SHIFT 7
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_PLLST_MASK 0x20u
-#define MCG_S_PLLST_SHIFT 5
-#define MCG_S_LOCK0_MASK 0x40u
-#define MCG_S_LOCK0_SHIFT 6
-#define MCG_S_LOLS0_MASK 0x80u
-#define MCG_S_LOLS0_SHIFT 7
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK 0x1u
-#define MCG_C7_OSCSEL_SHIFT 0
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK 0x1u
-#define MCG_C8_LOCS1_SHIFT 0
-#define MCG_C8_CME1_MASK 0x20u
-#define MCG_C8_CME1_SHIFT 5
-#define MCG_C8_LOLRE_MASK 0x40u
-#define MCG_C8_LOLRE_SHIFT 6
-#define MCG_C8_LOCRE1_MASK 0x80u
-#define MCG_C8_LOCRE1_SHIFT 7
-
-/**
- * @}
- */ /* end of group MCG_Register_Masks */
-
-
-/* MCG - Peripheral instance base addresses */
-/** Peripheral MCG base address */
-#define MCG_BASE (0x40064000u)
-/** Peripheral MCG base pointer */
-#define MCG ((MCG_Type *)MCG_BASE)
-
-/**
- * @}
- */ /* end of group MCG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
- * @{
- */
-
-/** NV - Register Layout Typedef */
-typedef struct {
- __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
- __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
- __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
- __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
- __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
- __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
- __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
- __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
- __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
- __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
- __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
- __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
- __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
- __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
- __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
- __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
-} NV_Type;
-
-/* ----------------------------------------------------------------------------
- -- NV Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Register_Masks NV Register Masks
- * @{
- */
-
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK 0x1u
-#define NV_FOPT_LPBOOT_SHIFT 0
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-/* FEPROT Bit Fields */
-#define NV_FEPROT_EPROT_MASK 0xFFu
-#define NV_FEPROT_EPROT_SHIFT 0
-#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define NV_FDPROT_DPROT_MASK 0xFFu
-#define NV_FDPROT_DPROT_SHIFT 0
-#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
-
-/**
- * @}
- */ /* end of group NV_Register_Masks */
-
-
-/* NV - Peripheral instance base addresses */
-/** Peripheral FTFL_FlashConfig base address */
-#define FTFL_FlashConfig_BASE (0x400u)
-/** Peripheral FTFL_FlashConfig base pointer */
-#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
-
-/**
- * @}
- */ /* end of group NV_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
- * @{
- */
-
-/** OSC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
-} OSC_Type;
-
-/* ----------------------------------------------------------------------------
- -- OSC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Register_Masks OSC Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-
-/**
- * @}
- */ /* end of group OSC_Register_Masks */
-
-
-/* OSC - Peripheral instance base addresses */
-/** Peripheral OSC0 base address */
-#define OSC0_BASE (0x40065000u)
-/** Peripheral OSC0 base pointer */
-#define OSC0 ((OSC_Type *)OSC0_BASE)
-
-/**
- * @}
- */ /* end of group OSC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PDB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
- * @{
- */
-
-/** PDB - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
- __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
- __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
- __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
- struct { /* offset: 0x10, array step: 0x10 */
- __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
- __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
- __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
- } CH[1];
- uint8_t RESERVED_0[368];
- __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
- __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
-} PDB_Type;
-
-/* ----------------------------------------------------------------------------
- -- PDB Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PDB_Register_Masks PDB Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK 0x1u
-#define PDB_SC_LDOK_SHIFT 0
-#define PDB_SC_CONT_MASK 0x2u
-#define PDB_SC_CONT_SHIFT 1
-#define PDB_SC_MULT_MASK 0xCu
-#define PDB_SC_MULT_SHIFT 2
-#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK 0x20u
-#define PDB_SC_PDBIE_SHIFT 5
-#define PDB_SC_PDBIF_MASK 0x40u
-#define PDB_SC_PDBIF_SHIFT 6
-#define PDB_SC_PDBEN_MASK 0x80u
-#define PDB_SC_PDBEN_SHIFT 7
-#define PDB_SC_TRGSEL_MASK 0xF00u
-#define PDB_SC_TRGSEL_SHIFT 8
-#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK 0x7000u
-#define PDB_SC_PRESCALER_SHIFT 12
-#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK 0x8000u
-#define PDB_SC_DMAEN_SHIFT 15
-#define PDB_SC_SWTRIG_MASK 0x10000u
-#define PDB_SC_SWTRIG_SHIFT 16
-#define PDB_SC_PDBEIE_MASK 0x20000u
-#define PDB_SC_PDBEIE_SHIFT 17
-#define PDB_SC_LDMOD_MASK 0xC0000u
-#define PDB_SC_LDMOD_SHIFT 18
-#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK 0xFFFFu
-#define PDB_MOD_MOD_SHIFT 0
-#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK 0xFFFFu
-#define PDB_CNT_CNT_SHIFT 0
-#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK 0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT 0
-#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK 0xFFu
-#define PDB_C1_EN_SHIFT 0
-#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK 0xFF00u
-#define PDB_C1_TOS_SHIFT 8
-#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK 0xFF0000u
-#define PDB_C1_BB_SHIFT 16
-#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK 0xFFu
-#define PDB_S_ERR_SHIFT 0
-#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK 0xFF0000u
-#define PDB_S_CF_SHIFT 16
-#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK 0xFFFFu
-#define PDB_DLY_DLY_SHIFT 0
-#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK 0xFFu
-#define PDB_POEN_POEN_SHIFT 0
-#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK 0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT 0
-#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT 16
-#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
-
-/**
- * @}
- */ /* end of group PDB_Register_Masks */
-
-
-/* PDB - Peripheral instance base addresses */
-/** Peripheral PDB0 base address */
-#define PDB0_BASE (0x40036000u)
-/** Peripheral PDB0 base pointer */
-#define PDB0 ((PDB_Type *)PDB0_BASE)
-
-/**
- * @}
- */ /* end of group PDB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
- * @{
- */
-
-/** PIT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
- uint8_t RESERVED_0[252];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
- __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
- __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
- __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
- } CHANNEL[4];
-} PIT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-
-/**
- * @}
- */ /* end of group PIT_Register_Masks */
-
-
-/* PIT - Peripheral instance base addresses */
-/** Peripheral PIT base address */
-#define PIT_BASE (0x40037000u)
-/** Peripheral PIT base pointer */
-#define PIT ((PIT_Type *)PIT_BASE)
-
-/**
- * @}
- */ /* end of group PIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
- * @{
- */
-
-/** PMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
- __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
- __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
-} PMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- PMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Register_Masks PMC Register Masks
- * @{
- */
-
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-
-/**
- * @}
- */ /* end of group PMC_Register_Masks */
-
-
-/* PMC - Peripheral instance base addresses */
-/** Peripheral PMC base address */
-#define PMC_BASE (0x4007D000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-
-/**
- * @}
- */ /* end of group PMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
- * @{
- */
-
-/** PORT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
- __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
- __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
- uint8_t RESERVED_0[24];
- __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
- uint8_t RESERVED_1[28];
- __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
- __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
- __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PORT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Register_Masks PORT Register Masks
- * @{
- */
-
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_ODE_MASK 0x20u
-#define PORT_PCR_ODE_SHIFT 5
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK 0x8000u
-#define PORT_PCR_LK_SHIFT 15
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT 0
-#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK 0x1u
-#define PORT_DFCR_CS_SHIFT 0
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK 0x1Fu
-#define PORT_DFWR_FILT_SHIFT 0
-#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
-
-/**
- * @}
- */ /* end of group PORT_Register_Masks */
-
-
-/* PORT - Peripheral instance base addresses */
-/** Peripheral PORTA base address */
-#define PORTA_BASE (0x40049000u)
-/** Peripheral PORTA base pointer */
-#define PORTA ((PORT_Type *)PORTA_BASE)
-/** Peripheral PORTB base address */
-#define PORTB_BASE (0x4004A000u)
-/** Peripheral PORTB base pointer */
-#define PORTB ((PORT_Type *)PORTB_BASE)
-/** Peripheral PORTC base address */
-#define PORTC_BASE (0x4004B000u)
-/** Peripheral PORTC base pointer */
-#define PORTC ((PORT_Type *)PORTC_BASE)
-/** Peripheral PORTD base address */
-#define PORTD_BASE (0x4004C000u)
-/** Peripheral PORTD base pointer */
-#define PORTD ((PORT_Type *)PORTD_BASE)
-/** Peripheral PORTE base address */
-#define PORTE_BASE (0x4004D000u)
-/** Peripheral PORTE base pointer */
-#define PORTE ((PORT_Type *)PORTE_BASE)
-
-/**
- * @}
- */ /* end of group PORT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
- * @{
- */
-
-/** RCM - Register Layout Typedef */
-typedef struct {
- __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
- __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
- uint8_t RESERVED_0[2];
- __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
- __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
- uint8_t RESERVED_1[1];
- __I uint8_t MR; /**< Mode Register, offset: 0x7 */
-} RCM_Type;
-
-/* ----------------------------------------------------------------------------
- -- RCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Register_Masks RCM Register Masks
- * @{
- */
-
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOL_MASK 0x8u
-#define RCM_SRS0_LOL_SHIFT 3
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK 0x1u
-#define RCM_SRS1_JTAG_SHIFT 0
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_EZPT_MASK 0x10u
-#define RCM_SRS1_EZPT_SHIFT 4
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK 0x2u
-#define RCM_MR_EZP_MS_SHIFT 1
-
-/**
- * @}
- */ /* end of group RCM_Register_Masks */
-
-
-/* RCM - Peripheral instance base addresses */
-/** Peripheral RCM base address */
-#define RCM_BASE (0x4007F000u)
-/** Peripheral RCM base pointer */
-#define RCM ((RCM_Type *)RCM_BASE)
-
-/**
- * @}
- */ /* end of group RCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
- * @{
- */
-
-/** RFSYS - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type;
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK 0xFFu
-#define RFSYS_REG_LL_SHIFT 0
-#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK 0xFF00u
-#define RFSYS_REG_LH_SHIFT 8
-#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK 0xFF0000u
-#define RFSYS_REG_HL_SHIFT 16
-#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK 0xFF000000u
-#define RFSYS_REG_HH_SHIFT 24
-#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
-
-/**
- * @}
- */ /* end of group RFSYS_Register_Masks */
-
-
-/* RFSYS - Peripheral instance base addresses */
-/** Peripheral RFSYS base address */
-#define RFSYS_BASE (0x40041000u)
-/** Peripheral RFSYS base pointer */
-#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
-
-/**
- * @}
- */ /* end of group RFSYS_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
- * @{
- */
-
-/** RFVBAT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type;
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK 0xFFu
-#define RFVBAT_REG_LL_SHIFT 0
-#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK 0xFF00u
-#define RFVBAT_REG_LH_SHIFT 8
-#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK 0xFF0000u
-#define RFVBAT_REG_HL_SHIFT 16
-#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK 0xFF000000u
-#define RFVBAT_REG_HH_SHIFT 24
-#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
-
-/**
- * @}
- */ /* end of group RFVBAT_Register_Masks */
-
-
-/* RFVBAT - Peripheral instance base addresses */
-/** Peripheral RFVBAT base address */
-#define RFVBAT_BASE (0x4003E000u)
-/** Peripheral RFVBAT base pointer */
-#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
-
-/**
- * @}
- */ /* end of group RFVBAT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
- __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
- __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
- __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
- __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
- __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
- __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
- __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
- uint8_t RESERVED_0[2016];
- __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
- __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type;
-
-/* ----------------------------------------------------------------------------
- -- RTC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK 0x1u
-#define RTC_WAR_TSRW_SHIFT 0
-#define RTC_WAR_TPRW_MASK 0x2u
-#define RTC_WAR_TPRW_SHIFT 1
-#define RTC_WAR_TARW_MASK 0x4u
-#define RTC_WAR_TARW_SHIFT 2
-#define RTC_WAR_TCRW_MASK 0x8u
-#define RTC_WAR_TCRW_SHIFT 3
-#define RTC_WAR_CRW_MASK 0x10u
-#define RTC_WAR_CRW_SHIFT 4
-#define RTC_WAR_SRW_MASK 0x20u
-#define RTC_WAR_SRW_SHIFT 5
-#define RTC_WAR_LRW_MASK 0x40u
-#define RTC_WAR_LRW_SHIFT 6
-#define RTC_WAR_IERW_MASK 0x80u
-#define RTC_WAR_IERW_SHIFT 7
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK 0x1u
-#define RTC_RAR_TSRR_SHIFT 0
-#define RTC_RAR_TPRR_MASK 0x2u
-#define RTC_RAR_TPRR_SHIFT 1
-#define RTC_RAR_TARR_MASK 0x4u
-#define RTC_RAR_TARR_SHIFT 2
-#define RTC_RAR_TCRR_MASK 0x8u
-#define RTC_RAR_TCRR_SHIFT 3
-#define RTC_RAR_CRR_MASK 0x10u
-#define RTC_RAR_CRR_SHIFT 4
-#define RTC_RAR_SRR_MASK 0x20u
-#define RTC_RAR_SRR_SHIFT 5
-#define RTC_RAR_LRR_MASK 0x40u
-#define RTC_RAR_LRR_SHIFT 6
-#define RTC_RAR_IERR_MASK 0x80u
-#define RTC_RAR_IERR_SHIFT 7
-
-/**
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4003D000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-
-/**
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
- * @{
- */
-
-/** SIM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
- __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
- uint8_t RESERVED_0[4092];
- __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
- __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
- uint8_t RESERVED_2[4];
- __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
- uint8_t RESERVED_3[8];
- __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
- uint8_t RESERVED_4[12];
- __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
- __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
- __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
- __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
- __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
- __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
- __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
- __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
- __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
- __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
- __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
- __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type;
-
-/* ----------------------------------------------------------------------------
- -- SIM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Register_Masks SIM Register Masks
- * @{
- */
-
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT 12
-#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT 29
-#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT 30
-#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT 31
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT 24
-#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT 25
-#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT 26
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_PTD7PAD_MASK 0x800u
-#define SIM_SOPT2_PTD7PAD_SHIFT 11
-#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT 0
-#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT 1
-#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT 4
-#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK 0x70u
-#define SIM_SDID_FAMID_SHIFT 4
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK 0x2u
-#define SIM_SCGC4_EWM_SHIFT 1
-#define SIM_SCGC4_CMT_MASK 0x4u
-#define SIM_SCGC4_CMT_SHIFT 2
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_VREF_MASK 0x100000u
-#define SIM_SCGC4_VREF_SHIFT 20
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTIMER_MASK 0x1u
-#define SIM_SCGC5_LPTIMER_SHIFT 0
-#define SIM_SCGC5_TSI_MASK 0x20u
-#define SIM_SCGC5_TSI_SHIFT 5
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTFL_MASK 0x1u
-#define SIM_SCGC6_FTFL_SHIFT 0
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_SPI0_MASK 0x1000u
-#define SIM_SCGC6_SPI0_SHIFT 12
-#define SIM_SCGC6_I2S_MASK 0x8000u
-#define SIM_SCGC6_I2S_SHIFT 15
-#define SIM_SCGC6_CRC_MASK 0x40000u
-#define SIM_SCGC6_CRC_SHIFT 18
-#define SIM_SCGC6_USBDCD_MASK 0x200000u
-#define SIM_SCGC6_USBDCD_SHIFT 21
-#define SIM_SCGC6_PDB_MASK 0x400000u
-#define SIM_SCGC6_PDB_SHIFT 22
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_FTM0_MASK 0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT 24
-#define SIM_SCGC6_FTM1_MASK 0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT 25
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_DMA_MASK 0x2u
-#define SIM_SCGC7_DMA_SHIFT 1
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
-#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT 0
-#define SIM_CLKDIV2_USBDIV_MASK 0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT 1
-#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_DEPART_MASK 0xF00u
-#define SIM_FCFG1_DEPART_SHIFT 8
-#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
-#define SIM_FCFG1_EESIZE_MASK 0xF0000u
-#define SIM_FCFG1_EESIZE_SHIFT 16
-#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
-#define SIM_FCFG1_NVMSIZE_SHIFT 28
-#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT 16
-#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_PFLSH_MASK 0x800000u
-#define SIM_FCFG2_PFLSH_SHIFT 23
-#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT 24
-#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT 0
-#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
-
-/**
- * @}
- */ /* end of group SIM_Register_Masks */
-
-
-/* SIM - Peripheral instance base addresses */
-/** Peripheral SIM base address */
-#define SIM_BASE (0x40047000u)
-/** Peripheral SIM base pointer */
-#define SIM ((SIM_Type *)SIM_BASE)
-
-/**
- * @}
- */ /* end of group SIM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
- * @{
- */
-
-/** SMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
- __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
- __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
- __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
-} SMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- SMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Register_Masks SMC Register Masks
- * @{
- */
-
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-#define SMC_PMCTRL_LPWUI_MASK 0x80u
-#define SMC_PMCTRL_LPWUI_SHIFT 7
-/* VLLSCTRL Bit Fields */
-#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
-#define SMC_VLLSCTRL_VLLSM_SHIFT 0
-#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
-#define SMC_VLLSCTRL_PORPO_MASK 0x20u
-#define SMC_VLLSCTRL_PORPO_SHIFT 5
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
-
-/**
- * @}
- */ /* end of group SMC_Register_Masks */
-
-
-/* SMC - Peripheral instance base addresses */
-/** Peripheral SMC base address */
-#define SMC_BASE (0x4007E000u)
-/** Peripheral SMC base pointer */
-#define SMC ((SMC_Type *)SMC_BASE)
-
-/**
- * @}
- */ /* end of group SMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
- uint8_t RESERVED_0[4];
- __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
- union { /* offset: 0xC */
- __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
- __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
- };
- uint8_t RESERVED_1[24];
- __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
- __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
- union { /* offset: 0x34 */
- __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
- __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
- };
- __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
- __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
- __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
- __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
- __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
- uint8_t RESERVED_2[48];
- __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
- __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
- __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
- __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
-} SPI_Type;
-
-/* ----------------------------------------------------------------------------
- -- SPI Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK 0x1u
-#define SPI_MCR_HALT_SHIFT 0
-#define SPI_MCR_SMPL_PT_MASK 0x300u
-#define SPI_MCR_SMPL_PT_SHIFT 8
-#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK 0x400u
-#define SPI_MCR_CLR_RXF_SHIFT 10
-#define SPI_MCR_CLR_TXF_MASK 0x800u
-#define SPI_MCR_CLR_TXF_SHIFT 11
-#define SPI_MCR_DIS_RXF_MASK 0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT 12
-#define SPI_MCR_DIS_TXF_MASK 0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT 13
-#define SPI_MCR_MDIS_MASK 0x4000u
-#define SPI_MCR_MDIS_SHIFT 14
-#define SPI_MCR_DOZE_MASK 0x8000u
-#define SPI_MCR_DOZE_SHIFT 15
-#define SPI_MCR_PCSIS_MASK 0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT 16
-#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK 0x1000000u
-#define SPI_MCR_ROOE_SHIFT 24
-#define SPI_MCR_PCSSE_MASK 0x2000000u
-#define SPI_MCR_PCSSE_SHIFT 25
-#define SPI_MCR_MTFE_MASK 0x4000000u
-#define SPI_MCR_MTFE_SHIFT 26
-#define SPI_MCR_FRZ_MASK 0x8000000u
-#define SPI_MCR_FRZ_SHIFT 27
-#define SPI_MCR_DCONF_MASK 0x30000000u
-#define SPI_MCR_DCONF_SHIFT 28
-#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT 30
-#define SPI_MCR_MSTR_MASK 0x80000000u
-#define SPI_MCR_MSTR_SHIFT 31
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT 16
-#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK 0xFu
-#define SPI_CTAR_BR_SHIFT 0
-#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK 0xF0u
-#define SPI_CTAR_DT_SHIFT 4
-#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK 0xF00u
-#define SPI_CTAR_ASC_SHIFT 8
-#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK 0xF000u
-#define SPI_CTAR_CSSCK_SHIFT 12
-#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK 0x30000u
-#define SPI_CTAR_PBR_SHIFT 16
-#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK 0xC0000u
-#define SPI_CTAR_PDT_SHIFT 18
-#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK 0x300000u
-#define SPI_CTAR_PASC_SHIFT 20
-#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK 0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT 22
-#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK 0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT 24
-#define SPI_CTAR_CPHA_MASK 0x2000000u
-#define SPI_CTAR_CPHA_SHIFT 25
-#define SPI_CTAR_CPOL_MASK 0x4000000u
-#define SPI_CTAR_CPOL_SHIFT 26
-#define SPI_CTAR_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT 27
-#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK 0x80000000u
-#define SPI_CTAR_DBR_SHIFT 31
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
-#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
-#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
-#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK 0xFu
-#define SPI_SR_POPNXTPTR_SHIFT 0
-#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK 0xF0u
-#define SPI_SR_RXCTR_SHIFT 4
-#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK 0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT 8
-#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK 0xF000u
-#define SPI_SR_TXCTR_SHIFT 12
-#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK 0x20000u
-#define SPI_SR_RFDF_SHIFT 17
-#define SPI_SR_RFOF_MASK 0x80000u
-#define SPI_SR_RFOF_SHIFT 19
-#define SPI_SR_TFFF_MASK 0x2000000u
-#define SPI_SR_TFFF_SHIFT 25
-#define SPI_SR_TFUF_MASK 0x8000000u
-#define SPI_SR_TFUF_SHIFT 27
-#define SPI_SR_EOQF_MASK 0x10000000u
-#define SPI_SR_EOQF_SHIFT 28
-#define SPI_SR_TXRXS_MASK 0x40000000u
-#define SPI_SR_TXRXS_SHIFT 30
-#define SPI_SR_TCF_MASK 0x80000000u
-#define SPI_SR_TCF_SHIFT 31
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT 16
-#define SPI_RSER_RFDF_RE_MASK 0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT 17
-#define SPI_RSER_RFOF_RE_MASK 0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT 19
-#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT 24
-#define SPI_RSER_TFFF_RE_MASK 0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT 25
-#define SPI_RSER_TFUF_RE_MASK 0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT 27
-#define SPI_RSER_EOQF_RE_MASK 0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT 28
-#define SPI_RSER_TCF_RE_MASK 0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT 31
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT 0
-#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK 0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT 16
-#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK 0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT 26
-#define SPI_PUSHR_EOQ_MASK 0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT 27
-#define SPI_PUSHR_CTAS_MASK 0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT 28
-#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK 0x80000000u
-#define SPI_PUSHR_CONT_SHIFT 31
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
-#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT 0
-#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT 0
-#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT 0
-#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT 0
-#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT 0
-#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT 0
-#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT 0
-#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT 0
-#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT 0
-#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
-
-/**
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x4002C000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-
-/**
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- TSI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
- * @{
- */
-
-/** TSI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
- __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
- __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
- __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
- uint8_t RESERVED_0[240];
- __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
- __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
- __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
- __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
- __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
- __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
- __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
- __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
- __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
-} TSI_Type;
-
-/* ----------------------------------------------------------------------------
- -- TSI Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Register_Masks TSI Register Masks
- * @{
- */
-
-/* GENCS Bit Fields */
-#define TSI_GENCS_STPE_MASK 0x1u
-#define TSI_GENCS_STPE_SHIFT 0
-#define TSI_GENCS_STM_MASK 0x2u
-#define TSI_GENCS_STM_SHIFT 1
-#define TSI_GENCS_ESOR_MASK 0x10u
-#define TSI_GENCS_ESOR_SHIFT 4
-#define TSI_GENCS_ERIE_MASK 0x20u
-#define TSI_GENCS_ERIE_SHIFT 5
-#define TSI_GENCS_TSIIE_MASK 0x40u
-#define TSI_GENCS_TSIIE_SHIFT 6
-#define TSI_GENCS_TSIEN_MASK 0x80u
-#define TSI_GENCS_TSIEN_SHIFT 7
-#define TSI_GENCS_SWTS_MASK 0x100u
-#define TSI_GENCS_SWTS_SHIFT 8
-#define TSI_GENCS_SCNIP_MASK 0x200u
-#define TSI_GENCS_SCNIP_SHIFT 9
-#define TSI_GENCS_OVRF_MASK 0x1000u
-#define TSI_GENCS_OVRF_SHIFT 12
-#define TSI_GENCS_EXTERF_MASK 0x2000u
-#define TSI_GENCS_EXTERF_SHIFT 13
-#define TSI_GENCS_OUTRGF_MASK 0x4000u
-#define TSI_GENCS_OUTRGF_SHIFT 14
-#define TSI_GENCS_EOSF_MASK 0x8000u
-#define TSI_GENCS_EOSF_SHIFT 15
-#define TSI_GENCS_PS_MASK 0x70000u
-#define TSI_GENCS_PS_SHIFT 16
-#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
-#define TSI_GENCS_NSCN_MASK 0xF80000u
-#define TSI_GENCS_NSCN_SHIFT 19
-#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
-#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
-#define TSI_GENCS_LPSCNITV_SHIFT 24
-#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
-#define TSI_GENCS_LPCLKS_MASK 0x10000000u
-#define TSI_GENCS_LPCLKS_SHIFT 28
-/* SCANC Bit Fields */
-#define TSI_SCANC_AMPSC_MASK 0x7u
-#define TSI_SCANC_AMPSC_SHIFT 0
-#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
-#define TSI_SCANC_AMCLKS_MASK 0x18u
-#define TSI_SCANC_AMCLKS_SHIFT 3
-#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
-#define TSI_SCANC_SMOD_MASK 0xFF00u
-#define TSI_SCANC_SMOD_SHIFT 8
-#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
-#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
-#define TSI_SCANC_EXTCHRG_SHIFT 16
-#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
-#define TSI_SCANC_REFCHRG_MASK 0xF000000u
-#define TSI_SCANC_REFCHRG_SHIFT 24
-#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
-/* PEN Bit Fields */
-#define TSI_PEN_PEN0_MASK 0x1u
-#define TSI_PEN_PEN0_SHIFT 0
-#define TSI_PEN_PEN1_MASK 0x2u
-#define TSI_PEN_PEN1_SHIFT 1
-#define TSI_PEN_PEN2_MASK 0x4u
-#define TSI_PEN_PEN2_SHIFT 2
-#define TSI_PEN_PEN3_MASK 0x8u
-#define TSI_PEN_PEN3_SHIFT 3
-#define TSI_PEN_PEN4_MASK 0x10u
-#define TSI_PEN_PEN4_SHIFT 4
-#define TSI_PEN_PEN5_MASK 0x20u
-#define TSI_PEN_PEN5_SHIFT 5
-#define TSI_PEN_PEN6_MASK 0x40u
-#define TSI_PEN_PEN6_SHIFT 6
-#define TSI_PEN_PEN7_MASK 0x80u
-#define TSI_PEN_PEN7_SHIFT 7
-#define TSI_PEN_PEN8_MASK 0x100u
-#define TSI_PEN_PEN8_SHIFT 8
-#define TSI_PEN_PEN9_MASK 0x200u
-#define TSI_PEN_PEN9_SHIFT 9
-#define TSI_PEN_PEN10_MASK 0x400u
-#define TSI_PEN_PEN10_SHIFT 10
-#define TSI_PEN_PEN11_MASK 0x800u
-#define TSI_PEN_PEN11_SHIFT 11
-#define TSI_PEN_PEN12_MASK 0x1000u
-#define TSI_PEN_PEN12_SHIFT 12
-#define TSI_PEN_PEN13_MASK 0x2000u
-#define TSI_PEN_PEN13_SHIFT 13
-#define TSI_PEN_PEN14_MASK 0x4000u
-#define TSI_PEN_PEN14_SHIFT 14
-#define TSI_PEN_PEN15_MASK 0x8000u
-#define TSI_PEN_PEN15_SHIFT 15
-#define TSI_PEN_LPSP_MASK 0xF0000u
-#define TSI_PEN_LPSP_SHIFT 16
-#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
-/* WUCNTR Bit Fields */
-#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
-#define TSI_WUCNTR_WUCNT_SHIFT 0
-#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
-/* CNTR1 Bit Fields */
-#define TSI_CNTR1_CTN1_MASK 0xFFFFu
-#define TSI_CNTR1_CTN1_SHIFT 0
-#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
-#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR1_CTN_SHIFT 16
-#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
-/* CNTR3 Bit Fields */
-#define TSI_CNTR3_CTN1_MASK 0xFFFFu
-#define TSI_CNTR3_CTN1_SHIFT 0
-#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
-#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR3_CTN_SHIFT 16
-#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
-/* CNTR5 Bit Fields */
-#define TSI_CNTR5_CTN1_MASK 0xFFFFu
-#define TSI_CNTR5_CTN1_SHIFT 0
-#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
-#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR5_CTN_SHIFT 16
-#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
-/* CNTR7 Bit Fields */
-#define TSI_CNTR7_CTN1_MASK 0xFFFFu
-#define TSI_CNTR7_CTN1_SHIFT 0
-#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
-#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR7_CTN_SHIFT 16
-#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
-/* CNTR9 Bit Fields */
-#define TSI_CNTR9_CTN1_MASK 0xFFFFu
-#define TSI_CNTR9_CTN1_SHIFT 0
-#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
-#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR9_CTN_SHIFT 16
-#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
-/* CNTR11 Bit Fields */
-#define TSI_CNTR11_CTN1_MASK 0xFFFFu
-#define TSI_CNTR11_CTN1_SHIFT 0
-#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
-#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR11_CTN_SHIFT 16
-#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
-/* CNTR13 Bit Fields */
-#define TSI_CNTR13_CTN1_MASK 0xFFFFu
-#define TSI_CNTR13_CTN1_SHIFT 0
-#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
-#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR13_CTN_SHIFT 16
-#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
-/* CNTR15 Bit Fields */
-#define TSI_CNTR15_CTN1_MASK 0xFFFFu
-#define TSI_CNTR15_CTN1_SHIFT 0
-#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
-#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR15_CTN_SHIFT 16
-#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
-/* THRESHOLD Bit Fields */
-#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
-#define TSI_THRESHOLD_HTHH_SHIFT 0
-#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
-#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
-#define TSI_THRESHOLD_LTHH_SHIFT 16
-#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
-
-/**
- * @}
- */ /* end of group TSI_Register_Masks */
-
-
-/* TSI - Peripheral instance base addresses */
-/** Peripheral TSI0 base address */
-#define TSI0_BASE (0x40045000u)
-/** Peripheral TSI0 base pointer */
-#define TSI0 ((TSI_Type *)TSI0_BASE)
-
-/**
- * @}
- */ /* end of group TSI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- UART Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
- * @{
- */
-
-/** UART - Register Layout Typedef */
-typedef struct {
- __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
- __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
- __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
- __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
- __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
- __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
- __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
- __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
- __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
- __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
- __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
- __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
- __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
- __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
- __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
- uint8_t RESERVED_0[1];
- __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
- __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
- __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
- __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
- __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
- __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
- __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
- uint8_t RESERVED_1[1];
- __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
- __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
- __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
- union { /* offset: 0x1B */
- __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
- __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
- };
- __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
- __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
- __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
- __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
- uint8_t RESERVED_2[1];
- __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
- __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
- __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
- __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
- __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
- __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
- __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
- __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
- __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
- __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
- __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
- __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
- __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
- __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
- __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
- __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
- __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
-} UART_Type;
-
-/* ----------------------------------------------------------------------------
- -- UART Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Register_Masks UART Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_MSBF_MASK 0x20u
-#define UART_S2_MSBF_SHIFT 5
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-/* D Bit Fields */
-#define UART_D_RT_MASK 0xFFu
-#define UART_D_RT_SHIFT 0
-#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK 0xFFu
-#define UART_MA1_MA_SHIFT 0
-#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK 0xFFu
-#define UART_MA2_MA_SHIFT 0
-#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK 0x1Fu
-#define UART_C4_BRFA_SHIFT 0
-#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK 0x20u
-#define UART_C4_M10_SHIFT 5
-#define UART_C4_MAEN2_MASK 0x40u
-#define UART_C4_MAEN2_SHIFT 6
-#define UART_C4_MAEN1_MASK 0x80u
-#define UART_C4_MAEN1_SHIFT 7
-/* C5 Bit Fields */
-#define UART_C5_RDMAS_MASK 0x20u
-#define UART_C5_RDMAS_SHIFT 5
-#define UART_C5_TDMAS_MASK 0x80u
-#define UART_C5_TDMAS_SHIFT 7
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK 0x40u
-#define UART_ED_PARITYE_SHIFT 6
-#define UART_ED_NOISY_MASK 0x80u
-#define UART_ED_NOISY_SHIFT 7
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK 0x1u
-#define UART_MODEM_TXCTSE_SHIFT 0
-#define UART_MODEM_TXRTSE_MASK 0x2u
-#define UART_MODEM_TXRTSE_SHIFT 1
-#define UART_MODEM_TXRTSPOL_MASK 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT 2
-#define UART_MODEM_RXRTSE_MASK 0x8u
-#define UART_MODEM_RXRTSE_SHIFT 3
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK 0x3u
-#define UART_IR_TNP_SHIFT 0
-#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK 0x4u
-#define UART_IR_IREN_SHIFT 2
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
-#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK 0x8u
-#define UART_PFIFO_RXFE_SHIFT 3
-#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
-#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK 0x80u
-#define UART_PFIFO_TXFE_SHIFT 7
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK 0x1u
-#define UART_CFIFO_RXUFE_SHIFT 0
-#define UART_CFIFO_TXOFE_MASK 0x2u
-#define UART_CFIFO_TXOFE_SHIFT 1
-#define UART_CFIFO_RXFLUSH_MASK 0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT 6
-#define UART_CFIFO_TXFLUSH_MASK 0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT 7
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK 0x1u
-#define UART_SFIFO_RXUF_SHIFT 0
-#define UART_SFIFO_TXOF_MASK 0x2u
-#define UART_SFIFO_TXOF_SHIFT 1
-#define UART_SFIFO_RXEMPT_MASK 0x40u
-#define UART_SFIFO_RXEMPT_SHIFT 6
-#define UART_SFIFO_TXEMPT_MASK 0x80u
-#define UART_SFIFO_TXEMPT_SHIFT 7
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT 0
-#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT 0
-#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT 0
-#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT 0
-#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK 0x1u
-#define UART_C7816_ISO_7816E_SHIFT 0
-#define UART_C7816_TTYPE_MASK 0x2u
-#define UART_C7816_TTYPE_SHIFT 1
-#define UART_C7816_INIT_MASK 0x4u
-#define UART_C7816_INIT_SHIFT 2
-#define UART_C7816_ANACK_MASK 0x8u
-#define UART_C7816_ANACK_SHIFT 3
-#define UART_C7816_ONACK_MASK 0x10u
-#define UART_C7816_ONACK_SHIFT 4
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK 0x1u
-#define UART_IE7816_RXTE_SHIFT 0
-#define UART_IE7816_TXTE_MASK 0x2u
-#define UART_IE7816_TXTE_SHIFT 1
-#define UART_IE7816_GTVE_MASK 0x4u
-#define UART_IE7816_GTVE_SHIFT 2
-#define UART_IE7816_INITDE_MASK 0x10u
-#define UART_IE7816_INITDE_SHIFT 4
-#define UART_IE7816_BWTE_MASK 0x20u
-#define UART_IE7816_BWTE_SHIFT 5
-#define UART_IE7816_CWTE_MASK 0x40u
-#define UART_IE7816_CWTE_SHIFT 6
-#define UART_IE7816_WTE_MASK 0x80u
-#define UART_IE7816_WTE_SHIFT 7
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK 0x1u
-#define UART_IS7816_RXT_SHIFT 0
-#define UART_IS7816_TXT_MASK 0x2u
-#define UART_IS7816_TXT_SHIFT 1
-#define UART_IS7816_GTV_MASK 0x4u
-#define UART_IS7816_GTV_SHIFT 2
-#define UART_IS7816_INITD_MASK 0x10u
-#define UART_IS7816_INITD_SHIFT 4
-#define UART_IS7816_BWT_MASK 0x20u
-#define UART_IS7816_BWT_SHIFT 5
-#define UART_IS7816_CWT_MASK 0x40u
-#define UART_IS7816_CWT_SHIFT 6
-#define UART_IS7816_WT_MASK 0x80u
-#define UART_IS7816_WT_SHIFT 7
-/* WP7816_T_TYPE0 Bit Fields */
-#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
-#define UART_WP7816_T_TYPE0_WI_SHIFT 0
-#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
-/* WP7816_T_TYPE1 Bit Fields */
-#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
-#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
-#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
-#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
-#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
-#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK 0xFFu
-#define UART_WN7816_GTN_SHIFT 0
-#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK 0xFFu
-#define UART_WF7816_GTFD_SHIFT 0
-#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT 0
-#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT 4
-#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK 0xFFu
-#define UART_TL7816_TLEN_SHIFT 0
-#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-/* C6 Bit Fields */
-#define UART_C6_CP_MASK 0x10u
-#define UART_C6_CP_SHIFT 4
-#define UART_C6_CE_MASK 0x20u
-#define UART_C6_CE_SHIFT 5
-#define UART_C6_TX709_MASK 0x40u
-#define UART_C6_TX709_SHIFT 6
-#define UART_C6_EN709_MASK 0x80u
-#define UART_C6_EN709_SHIFT 7
-/* PCTH Bit Fields */
-#define UART_PCTH_PCTH_MASK 0xFFu
-#define UART_PCTH_PCTH_SHIFT 0
-#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
-/* PCTL Bit Fields */
-#define UART_PCTL_PCTL_MASK 0xFFu
-#define UART_PCTL_PCTL_SHIFT 0
-#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
-/* B1T Bit Fields */
-#define UART_B1T_B1T_MASK 0xFFu
-#define UART_B1T_B1T_SHIFT 0
-#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
-/* SDTH Bit Fields */
-#define UART_SDTH_SDTH_MASK 0xFFu
-#define UART_SDTH_SDTH_SHIFT 0
-#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
-/* SDTL Bit Fields */
-#define UART_SDTL_SDTL_MASK 0xFFu
-#define UART_SDTL_SDTL_SHIFT 0
-#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
-/* PRE Bit Fields */
-#define UART_PRE_PREAMBLE_MASK 0xFFu
-#define UART_PRE_PREAMBLE_SHIFT 0
-#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
-/* TPL Bit Fields */
-#define UART_TPL_TPL_MASK 0xFFu
-#define UART_TPL_TPL_SHIFT 0
-#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
-/* IE Bit Fields */
-#define UART_IE_TXFIE_MASK 0x1u
-#define UART_IE_TXFIE_SHIFT 0
-#define UART_IE_PSIE_MASK 0x2u
-#define UART_IE_PSIE_SHIFT 1
-#define UART_IE_PCTEIE_MASK 0x4u
-#define UART_IE_PCTEIE_SHIFT 2
-#define UART_IE_PTXIE_MASK 0x8u
-#define UART_IE_PTXIE_SHIFT 3
-#define UART_IE_PRXIE_MASK 0x10u
-#define UART_IE_PRXIE_SHIFT 4
-#define UART_IE_ISDIE_MASK 0x20u
-#define UART_IE_ISDIE_SHIFT 5
-#define UART_IE_WBEIE_MASK 0x40u
-#define UART_IE_WBEIE_SHIFT 6
-/* WB Bit Fields */
-#define UART_WB_WBASE_MASK 0xFFu
-#define UART_WB_WBASE_SHIFT 0
-#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
-/* S3 Bit Fields */
-#define UART_S3_TXFF_MASK 0x1u
-#define UART_S3_TXFF_SHIFT 0
-#define UART_S3_PSF_MASK 0x2u
-#define UART_S3_PSF_SHIFT 1
-#define UART_S3_PCTEF_MASK 0x4u
-#define UART_S3_PCTEF_SHIFT 2
-#define UART_S3_PTXF_MASK 0x8u
-#define UART_S3_PTXF_SHIFT 3
-#define UART_S3_PRXF_MASK 0x10u
-#define UART_S3_PRXF_SHIFT 4
-#define UART_S3_ISD_MASK 0x20u
-#define UART_S3_ISD_SHIFT 5
-#define UART_S3_WBEF_MASK 0x40u
-#define UART_S3_WBEF_SHIFT 6
-#define UART_S3_PEF_MASK 0x80u
-#define UART_S3_PEF_SHIFT 7
-/* S4 Bit Fields */
-#define UART_S4_FE_MASK 0x1u
-#define UART_S4_FE_SHIFT 0
-#define UART_S4_ILCV_MASK 0x2u
-#define UART_S4_ILCV_SHIFT 1
-#define UART_S4_CDET_MASK 0xCu
-#define UART_S4_CDET_SHIFT 2
-#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
-#define UART_S4_INITF_MASK 0x10u
-#define UART_S4_INITF_SHIFT 4
-/* RPL Bit Fields */
-#define UART_RPL_RPL_MASK 0xFFu
-#define UART_RPL_RPL_SHIFT 0
-#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
-/* RPREL Bit Fields */
-#define UART_RPREL_RPREL_MASK 0xFFu
-#define UART_RPREL_RPREL_SHIFT 0
-#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
-/* CPW Bit Fields */
-#define UART_CPW_CPW_MASK 0xFFu
-#define UART_CPW_CPW_SHIFT 0
-#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
-/* RIDT Bit Fields */
-#define UART_RIDT_RIDT_MASK 0xFFu
-#define UART_RIDT_RIDT_SHIFT 0
-#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
-/* TIDT Bit Fields */
-#define UART_TIDT_TIDT_MASK 0xFFu
-#define UART_TIDT_TIDT_SHIFT 0
-#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
-
-/**
- * @}
- */ /* end of group UART_Register_Masks */
-
-
-/* UART - Peripheral instance base addresses */
-/** Peripheral UART0 base address */
-#define UART0_BASE (0x4006A000u)
-/** Peripheral UART0 base pointer */
-#define UART0 ((UART_Type *)UART0_BASE)
-/** Peripheral UART1 base address */
-#define UART1_BASE (0x4006B000u)
-/** Peripheral UART1 base pointer */
-#define UART1 ((UART_Type *)UART1_BASE)
-/** Peripheral UART2 base address */
-#define UART2_BASE (0x4006C000u)
-/** Peripheral UART2 base pointer */
-#define UART2 ((UART_Type *)UART2_BASE)
-
-/**
- * @}
- */ /* end of group UART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
- __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
- uint8_t RESERVED_0[3];
- __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
- uint8_t RESERVED_1[3];
- __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
- uint8_t RESERVED_2[3];
- __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
- uint8_t RESERVED_3[3];
- __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
- uint8_t RESERVED_4[3];
- __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
- uint8_t RESERVED_5[3];
- __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
- uint8_t RESERVED_6[3];
- __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
- uint8_t RESERVED_7[99];
- __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
- uint8_t RESERVED_8[3];
- __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
- uint8_t RESERVED_9[3];
- __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
- uint8_t RESERVED_10[3];
- __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
- uint8_t RESERVED_11[3];
- __I uint8_t STAT; /**< Status Register, offset: 0x90 */
- uint8_t RESERVED_12[3];
- __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
- uint8_t RESERVED_13[3];
- __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
- uint8_t RESERVED_14[3];
- __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
- uint8_t RESERVED_15[3];
- __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
- uint8_t RESERVED_16[3];
- __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
- uint8_t RESERVED_17[3];
- __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
- uint8_t RESERVED_18[3];
- __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
- uint8_t RESERVED_19[3];
- __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
- uint8_t RESERVED_20[3];
- __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
- uint8_t RESERVED_21[11];
- struct { /* offset: 0xC0, array step: 0x4 */
- __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_0[3];
- } ENDPOINT[16];
- __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
- uint8_t RESERVED_22[3];
- __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
- uint8_t RESERVED_23[3];
- __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
- uint8_t RESERVED_24[3];
- __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
- uint8_t RESERVED_25[7];
- __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
-} USB_Type;
-
-/* ----------------------------------------------------------------------------
- -- USB Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-#define USB_ADDINFO_IRQNUM_MASK 0xF8u
-#define USB_ADDINFO_IRQNUM_SHIFT 3
-#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT 0
-#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
-
-/**
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x40072000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-
-/**
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USBDCD Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
- * @{
- */
-
-/** USBDCD - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
- __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
- __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
- uint8_t RESERVED_0[4];
- __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
- __IO uint32_t TIMER1; /**< , offset: 0x14 */
- __IO uint32_t TIMER2; /**< , offset: 0x18 */
-} USBDCD_Type;
-
-/* ----------------------------------------------------------------------------
- -- USBDCD Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
- * @{
- */
-
-/* CONTROL Bit Fields */
-#define USBDCD_CONTROL_IACK_MASK 0x1u
-#define USBDCD_CONTROL_IACK_SHIFT 0
-#define USBDCD_CONTROL_IF_MASK 0x100u
-#define USBDCD_CONTROL_IF_SHIFT 8
-#define USBDCD_CONTROL_IE_MASK 0x10000u
-#define USBDCD_CONTROL_IE_SHIFT 16
-#define USBDCD_CONTROL_START_MASK 0x1000000u
-#define USBDCD_CONTROL_START_SHIFT 24
-#define USBDCD_CONTROL_SR_MASK 0x2000000u
-#define USBDCD_CONTROL_SR_SHIFT 25
-/* CLOCK Bit Fields */
-#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
-#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
-#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
-#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
-#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
-/* STATUS Bit Fields */
-#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
-#define USBDCD_STATUS_SEQ_RES_SHIFT 16
-#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
-#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
-#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
-#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
-#define USBDCD_STATUS_ERR_MASK 0x100000u
-#define USBDCD_STATUS_ERR_SHIFT 20
-#define USBDCD_STATUS_TO_MASK 0x200000u
-#define USBDCD_STATUS_TO_SHIFT 21
-#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
-#define USBDCD_STATUS_ACTIVE_SHIFT 22
-/* TIMER0 Bit Fields */
-#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
-#define USBDCD_TIMER0_TUNITCON_SHIFT 0
-#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
-#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
-#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
-#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
-/* TIMER1 Bit Fields */
-#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
-#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
-#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
-#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
-#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
-#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
-/* TIMER2 Bit Fields */
-#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
-#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
-#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
-#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
-#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
-#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
-
-/**
- * @}
- */ /* end of group USBDCD_Register_Masks */
-
-
-/* USBDCD - Peripheral instance base addresses */
-/** Peripheral USBDCD base address */
-#define USBDCD_BASE (0x40035000u)
-/** Peripheral USBDCD base pointer */
-#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
-
-/**
- * @}
- */ /* end of group USBDCD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- VREF Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
- * @{
- */
-
-/** VREF - Register Layout Typedef */
-typedef struct {
- __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
- __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type;
-
-/* ----------------------------------------------------------------------------
- -- VREF Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup VREF_Register_Masks VREF Register Masks
- * @{
- */
-
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK 0x3Fu
-#define VREF_TRM_TRIM_SHIFT 0
-#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK 0x40u
-#define VREF_TRM_CHOPEN_SHIFT 6
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK 0x3u
-#define VREF_SC_MODE_LV_SHIFT 0
-#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK 0x4u
-#define VREF_SC_VREFST_SHIFT 2
-#define VREF_SC_REGEN_MASK 0x40u
-#define VREF_SC_REGEN_SHIFT 6
-#define VREF_SC_VREFEN_MASK 0x80u
-#define VREF_SC_VREFEN_SHIFT 7
-
-/**
- * @}
- */ /* end of group VREF_Register_Masks */
-
-
-/* VREF - Peripheral instance base addresses */
-/** Peripheral VREF base address */
-#define VREF_BASE (0x40074000u)
-/** Peripheral VREF base pointer */
-#define VREF ((VREF_Type *)VREF_BASE)
-
-/**
- * @}
- */ /* end of group VREF_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- WDOG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
- * @{
- */
-
-/** WDOG - Register Layout Typedef */
-typedef struct {
- __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
- __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
- __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
- __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
- __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
- __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
- __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
- __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
- __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
- __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
- __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
- __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
-} WDOG_Type;
-
-/* ----------------------------------------------------------------------------
- -- WDOG Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup WDOG_Register_Masks WDOG Register Masks
- * @{
- */
-
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT 0
-#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT 1
-#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
-#define WDOG_STCTRLH_WINEN_MASK 0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT 3
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
-#define WDOG_STCTRLH_DBGEN_MASK 0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT 5
-#define WDOG_STCTRLH_STOPEN_MASK 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT 6
-#define WDOG_STCTRLH_WAITEN_MASK 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT 7
-#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
-#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT 11
-#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT 12
-#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT 15
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
-#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT 0
-#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT 0
-#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK 0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT 0
-#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
-#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
-#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
-#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
-#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT 0
-#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT 8
-#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
-
-/**
- * @}
- */ /* end of group WDOG_Register_Masks */
-
-
-/* WDOG - Peripheral instance base addresses */
-/** Peripheral WDOG base address */
-#define WDOG_BASE (0x40052000u)
-/** Peripheral WDOG base pointer */
-#define WDOG ((WDOG_Type *)WDOG_BASE)
-
-/**
- * @}
- */ /* end of group WDOG_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma pop
-#elif defined(__CWCC__)
- #pragma pop
-#elif defined(__GNUC__)
- /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=default
-#else
- #error Not supported compiler type
-#endif
-
-/**
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
- -- Backward Compatibility
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
- * @{
- */
-
-/* No backward compatibility issues. */
-
-/**
- * @}
- */ /* end of group Backward_Compatibility_Symbols */
-
-
-#endif /* #if !defined(MK20D5_H_) */
-
-/* MK20D5.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct
deleted file mode 100644
index 9a661627b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct
+++ /dev/null
@@ -1,14 +0,0 @@
-
-LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k)
- ER_IROM1 0x00000000 0x20000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8
- ; 0x4000 - 0xF8 = 0x3F08
- RW_IRAM1 0x1FFFE0F8 0x3F08 {
- .ANY (+RW +ZI)
- }
-}
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s
deleted file mode 100644
index 24de2c250..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s
+++ /dev/null
@@ -1,412 +0,0 @@
-;/*****************************************************************************
-; * @file: startup_MK20D5.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
-; * MK20D5
-; * @version: 1.0
-; * @date: 2011-12-15
-; *
-; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-;*
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-__initial_sp EQU 0x20002000 ; Top of RAM
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
- DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
- DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
- DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
- DCD DMA_Error_IRQHandler ; DMA error interrupt
- DCD Reserved21_IRQHandler ; Reserved interrupt 21
- DCD FTFL_IRQHandler ; FTFL interrupt
- DCD Read_Collision_IRQHandler ; Read collision interrupt
- DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
- DCD LLW_IRQHandler ; Low Leakage Wakeup
- DCD Watchdog_IRQHandler ; WDOG interrupt
- DCD I2C0_IRQHandler ; I2C0 interrupt
- DCD SPI0_IRQHandler ; SPI0 interrupt
- DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
- DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
- DCD UART0_LON_IRQHandler ; UART0 LON interrupt
- DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
- DCD UART0_ERR_IRQHandler ; UART0 error interrupt
- DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
- DCD UART1_ERR_IRQHandler ; UART1 error interrupt
- DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
- DCD UART2_ERR_IRQHandler ; UART2 error interrupt
- DCD ADC0_IRQHandler ; ADC0 interrupt
- DCD CMP0_IRQHandler ; CMP0 interrupt
- DCD CMP1_IRQHandler ; CMP1 interrupt
- DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
- DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
- DCD CMT_IRQHandler ; CMT interrupt
- DCD RTC_IRQHandler ; RTC interrupt
- DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
- DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
- DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
- DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
- DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
- DCD PDB0_IRQHandler ; PDB0 interrupt
- DCD USB0_IRQHandler ; USB0 interrupt
- DCD USBDCD_IRQHandler ; USBDCD interrupt
- DCD TSI0_IRQHandler ; TSI0 interrupt
- DCD MCG_IRQHandler ; MCG interrupt
- DCD LPTimer_IRQHandler ; LPTimer interrupt
- DCD PORTA_IRQHandler ; Port A interrupt
- DCD PORTB_IRQHandler ; Port B interrupt
- DCD PORTC_IRQHandler ; Port C interrupt
- DCD PORTD_IRQHandler ; Port D interrupt
- DCD PORTE_IRQHandler ; Port E interrupt
- DCD SWI_IRQHandler ; Software interrupt
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; <h> Flash Configuration
-; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
-; <i> and security information that allows the MCU to restrict acces to the FTFL module.
-; <h> Backdoor Comparison Key
-; <o0> Backdoor Key 0 <0x0-0xFF:2>
-; <o1> Backdoor Key 1 <0x0-0xFF:2>
-; <o2> Backdoor Key 2 <0x0-0xFF:2>
-; <o3> Backdoor Key 3 <0x0-0xFF:2>
-; <o4> Backdoor Key 4 <0x0-0xFF:2>
-; <o5> Backdoor Key 5 <0x0-0xFF:2>
-; <o6> Backdoor Key 6 <0x0-0xFF:2>
-; <o7> Backdoor Key 7 <0x0-0xFF:2>
-BackDoorK0 EQU 0xFF
-BackDoorK1 EQU 0xFF
-BackDoorK2 EQU 0xFF
-BackDoorK3 EQU 0xFF
-BackDoorK4 EQU 0xFF
-BackDoorK5 EQU 0xFF
-BackDoorK6 EQU 0xFF
-BackDoorK7 EQU 0xFF
-; </h>
-; <h> Program flash protection bytes (FPROT)
-; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-; <i> Each bit protects a 1/32 region of the program flash memory.
-; <h> FPROT0
-; <i> Program flash protection bytes
-; <i> 1/32 - 8/32 region
-; <o.0> FPROT0.0
-; <o.1> FPROT0.1
-; <o.2> FPROT0.2
-; <o.3> FPROT0.3
-; <o.4> FPROT0.4
-; <o.5> FPROT0.5
-; <o.6> FPROT0.6
-; <o.7> FPROT0.7
-nFPROT0 EQU 0x00
-FPROT0 EQU nFPROT0:EOR:0xFF
-; </h>
-; <h> FPROT1
-; <i> Program Flash Region Protect Register 1
-; <i> 9/32 - 16/32 region
-; <o.0> FPROT1.0
-; <o.1> FPROT1.1
-; <o.2> FPROT1.2
-; <o.3> FPROT1.3
-; <o.4> FPROT1.4
-; <o.5> FPROT1.5
-; <o.6> FPROT1.6
-; <o.7> FPROT1.7
-nFPROT1 EQU 0x00
-FPROT1 EQU nFPROT1:EOR:0xFF
-; </h>
-; <h> FPROT2
-; <i> Program Flash Region Protect Register 2
-; <i> 17/32 - 24/32 region
-; <o.0> FPROT2.0
-; <o.1> FPROT2.1
-; <o.2> FPROT2.2
-; <o.3> FPROT2.3
-; <o.4> FPROT2.4
-; <o.5> FPROT2.5
-; <o.6> FPROT2.6
-; <o.7> FPROT2.7
-nFPROT2 EQU 0x00
-FPROT2 EQU nFPROT2:EOR:0xFF
-; </h>
-; <h> FPROT3
-; <i> Program Flash Region Protect Register 3
-; <i> 25/32 - 32/32 region
-; <o.0> FPROT3.0
-; <o.1> FPROT3.1
-; <o.2> FPROT3.2
-; <o.3> FPROT3.3
-; <o.4> FPROT3.4
-; <o.5> FPROT3.5
-; <o.6> FPROT3.6
-; <o.7> FPROT3.7
-nFPROT3 EQU 0x00
-FPROT3 EQU nFPROT3:EOR:0xFF
-; </h>
-; </h>
-; <h> Data flash protection byte (FDPROT)
-; <i> Each bit protects a 1/8 region of the data flash memory.
-; <i> (Program flash only devices: Reserved)
-; <o.0> FDPROT.0
-; <o.1> FDPROT.1
-; <o.2> FDPROT.2
-; <o.3> FDPROT.3
-; <o.4> FDPROT.4
-; <o.5> FDPROT.5
-; <o.6> FDPROT.6
-; <o.7> FDPROT.7
-nFDPROT EQU 0x00
-FDPROT EQU nFDPROT:EOR:0xFF
-; </h>
-; <h> EEPROM protection byte (FEPROT)
-; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
-; <i> (Program flash only devices: Reserved)
-; <o.0> FEPROT.0
-; <o.1> FEPROT.1
-; <o.2> FEPROT.2
-; <o.3> FEPROT.3
-; <o.4> FEPROT.4
-; <o.5> FEPROT.5
-; <o.6> FEPROT.6
-; <o.7> FEPROT.7
-nFEPROT EQU 0x00
-FEPROT EQU nFEPROT:EOR:0xFF
-; </h>
-; <h> Flash nonvolatile option byte (FOPT)
-; <i> Allows the user to customize the operation of the MCU at boot time.
-; <o.0> LPBOOT
-; <0=> Low-power boot
-; <1=> normal boot
-; <o.1> EZPORT_DIS
-; <0=> EzPort operation is enabled
-; <1=> EzPort operation is disabled
-FOPT EQU 0xFF
-; </h>
-; <h> Flash security byte (FSEC)
-; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-; <o.0..1> SEC
-; <2=> MCU security status is unsecure
-; <3=> MCU security status is secure
-; <i> Flash Security
-; <i> This bits define the security state of the MCU.
-; <o.2..3> FSLACC
-; <2=> Freescale factory access denied
-; <3=> Freescale factory access granted
-; <i> Freescale Failure Analysis Access Code
-; <i> This bits define the security state of the MCU.
-; <o.4..5> MEEN
-; <2=> Mass erase is disabled
-; <3=> Mass erase is enabled
-; <i> Mass Erase Enable Bits
-; <i> Enables and disables mass erase capability of the FTFL module
-; <o.6..7> KEYEN
-; <2=> Backdoor key access enabled
-; <3=> Backdoor key access disabled
-; <i> Backdoor key Security Enable
-; <i> These bits enable and disable backdoor key access to the FTFL module.
-FSEC EQU 0xFE
-; </h>
-; </h>
- IF :LNOT::DEF:RAM_TARGET
- AREA |.ARM.__at_0x400|, CODE, READONLY
- DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
- DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
- DCB FPROT0, FPROT1, FPROT2, FPROT3
- DCB FSEC, FOPT, FEPROT, FDPROT
- ENDIF
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT DMA0_IRQHandler [WEAK]
- EXPORT DMA1_IRQHandler [WEAK]
- EXPORT DMA2_IRQHandler [WEAK]
- EXPORT DMA3_IRQHandler [WEAK]
- EXPORT DMA_Error_IRQHandler [WEAK]
- EXPORT Reserved21_IRQHandler [WEAK]
- EXPORT FTFL_IRQHandler [WEAK]
- EXPORT Read_Collision_IRQHandler [WEAK]
- EXPORT LVD_LVW_IRQHandler [WEAK]
- EXPORT LLW_IRQHandler [WEAK]
- EXPORT Watchdog_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT I2S0_Tx_IRQHandler [WEAK]
- EXPORT I2S0_Rx_IRQHandler [WEAK]
- EXPORT UART0_LON_IRQHandler [WEAK]
- EXPORT UART0_RX_TX_IRQHandler [WEAK]
- EXPORT UART0_ERR_IRQHandler [WEAK]
- EXPORT UART1_RX_TX_IRQHandler [WEAK]
- EXPORT UART1_ERR_IRQHandler [WEAK]
- EXPORT UART2_RX_TX_IRQHandler [WEAK]
- EXPORT UART2_ERR_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT CMP0_IRQHandler [WEAK]
- EXPORT CMP1_IRQHandler [WEAK]
- EXPORT FTM0_IRQHandler [WEAK]
- EXPORT FTM1_IRQHandler [WEAK]
- EXPORT CMT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT RTC_Seconds_IRQHandler [WEAK]
- EXPORT PIT0_IRQHandler [WEAK]
- EXPORT PIT1_IRQHandler [WEAK]
- EXPORT PIT2_IRQHandler [WEAK]
- EXPORT PIT3_IRQHandler [WEAK]
- EXPORT PDB0_IRQHandler [WEAK]
- EXPORT USB0_IRQHandler [WEAK]
- EXPORT USBDCD_IRQHandler [WEAK]
- EXPORT TSI0_IRQHandler [WEAK]
- EXPORT MCG_IRQHandler [WEAK]
- EXPORT LPTimer_IRQHandler [WEAK]
- EXPORT PORTA_IRQHandler [WEAK]
- EXPORT PORTB_IRQHandler [WEAK]
- EXPORT PORTC_IRQHandler [WEAK]
- EXPORT PORTD_IRQHandler [WEAK]
- EXPORT PORTE_IRQHandler [WEAK]
- EXPORT SWI_IRQHandler [WEAK]
- EXPORT DefaultISR [WEAK]
-
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-DMA_Error_IRQHandler
-Reserved21_IRQHandler
-FTFL_IRQHandler
-Read_Collision_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-Watchdog_IRQHandler
-I2C0_IRQHandler
-SPI0_IRQHandler
-I2S0_Tx_IRQHandler
-I2S0_Rx_IRQHandler
-UART0_LON_IRQHandler
-UART0_RX_TX_IRQHandler
-UART0_ERR_IRQHandler
-UART1_RX_TX_IRQHandler
-UART1_ERR_IRQHandler
-UART2_RX_TX_IRQHandler
-UART2_ERR_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-CMP1_IRQHandler
-FTM0_IRQHandler
-FTM1_IRQHandler
-CMT_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT0_IRQHandler
-PIT1_IRQHandler
-PIT2_IRQHandler
-PIT3_IRQHandler
-PDB0_IRQHandler
-USB0_IRQHandler
-USBDCD_IRQHandler
-TSI0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-PORTA_IRQHandler
-PORTB_IRQHandler
-PORTC_IRQHandler
-PORTD_IRQHandler
-PORTE_IRQHandler
-SWI_IRQHandler
-DefaultISR
-
- B .
-
- ENDP
-
-
- ALIGN
- END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp
deleted file mode 100644
index 3296df192..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp
+++ /dev/null
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
deleted file mode 100644
index 600751ca0..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * K20 ARM GCC linker script file
- */
-
-MEMORY
-{
- VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
- FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
- FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
- RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * _reset_init : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .isr_vector :
- {
- __vector_table = .;
- KEEP(*(.vector_table))
- *(.text.Reset_Handler)
- *(.text.System_Init)
- . = ALIGN(4);
- } > VECTORS
-
- .flash_protect :
- {
- KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
- } > FLASH_PROTECTION
-
- .text :
- {
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
-
- } > RAM
-
- .bss :
- {
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- __bss_end__ = .;
- } > RAM
-
- .heap :
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy :
- {
- *(.stack)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
deleted file mode 100644
index ffa33181f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
+++ /dev/null
@@ -1,259 +0,0 @@
-/* File: startup_MK20D5.s
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V1.3
- * Date: 08 Feb 2012
- *
- * Copyright (c) 2015, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of the ARM Limited nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- .syntax unified
- .arch armv7-m
-
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x400
-#endif
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0xC00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long DMA0_IRQHandler /* 0: Watchdog Timer */
- .long DMA1_IRQHandler /* 1: Real Time Clock */
- .long DMA2_IRQHandler /* 2: Timer0 / Timer1 */
- .long DMA3_IRQHandler /* 3: Timer2 / Timer3 */
- .long DMA_Error_IRQHandler /* 4: MCIa */
- .long 0 /* 5: MCIb */
- .long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */
- .long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */
- .long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */
- .long LLW_IRQHandler /* 9: UART4 - not connected */
- .long Watchdog_IRQHandler /* 10: AACI / AC97 */
- .long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */
- .long SPI0_IRQHandler /* 12: Ethernet */
- .long I2S0_Tx_IRQHandler /* 13: USB Device */
- .long I2S0_Rx_IRQHandler /* 14: USB Host Controller */
- .long UART0_LON_IRQHandler /* 15: Character LCD */
- .long UART0_RX_TX_IRQHandler /* 16: Flexray */
- .long UART0_ERR_IRQHandler /* 17: CAN */
- .long UART1_RX_TX_IRQHandler /* 18: LIN */
- .long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */
- .long UART2_RX_TX_IRQHandler /* 20: Reserved */
- .long UART2_ERR_IRQHandler /* 21: Reserved */
- .long ADC0_IRQHandler /* 22: Reserved */
- .long CMP0_IRQHandler /* 23: Reserved */
- .long CMP1_IRQHandler /* 24: Reserved */
- .long FTM0_IRQHandler /* 25: Reserved */
- .long FTM1_IRQHandler /* 26: Reserved */
- .long CMT_IRQHandler /* 27: Reserved */
- .long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */
- .long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */
- .long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
- .long PIT2_IRQHandler
- .long PIT3_IRQHandler
- .long PDB0_IRQHandler
- .long USB0_IRQHandler
- .long USBDCD_IRQHandler
- .long TSI0_IRQHandler
- .long MCG_IRQHandler
- .long LPTimer_IRQHandler
- .long PORTA_IRQHandler
- .long PORTB_IRQHandler
- .long PORTC_IRQHandler
- .long PORTD_IRQHandler
- .long PORTE_IRQHandler
- .long SWI_IRQHandler
- .size __isr_vector, . - __isr_vector
-
- .section .text.Reset_Handler
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.Lflash_to_ram_loop:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .Lflash_to_ram_loop
-
-.Lflash_to_ram_loop_end:
-
- ldr r0, =SystemInit
- blx r0
- ldr r0, =_start
- bx r0
- .pool
- .size Reset_Handler, . - Reset_Handler
-
- .text
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_default_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- .type \handler_name, %function
-\handler_name :
- b .
- .size \handler_name, . - \handler_name
- .endm
-
- def_default_handler NMI_Handler
- def_default_handler HardFault_Handler
- def_default_handler MemManage_Handler
- def_default_handler BusFault_Handler
- def_default_handler UsageFault_Handler
- def_default_handler SVC_Handler
- def_default_handler DebugMon_Handler
- def_default_handler PendSV_Handler
- def_default_handler SysTick_Handler
- def_default_handler Default_Handler
-
- .macro def_irq_default_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
-
- def_irq_default_handler DMA0_IRQHandler
- def_irq_default_handler DMA1_IRQHandler
- def_irq_default_handler DMA2_IRQHandler
- def_irq_default_handler DMA3_IRQHandler
- def_irq_default_handler DMA_Error_IRQHandler
- def_irq_default_handler FTFL_IRQHandler
- def_irq_default_handler Read_Collision_IRQHandler
- def_irq_default_handler LVD_LVW_IRQHandler
- def_irq_default_handler LLW_IRQHandler
- def_irq_default_handler Watchdog_IRQHandler
- def_irq_default_handler I2C0_IRQHandler
- def_irq_default_handler SPI0_IRQHandler
- def_irq_default_handler I2S0_Tx_IRQHandler
- def_irq_default_handler I2S0_Rx_IRQHandler
- def_irq_default_handler UART0_LON_IRQHandler
- def_irq_default_handler UART0_RX_TX_IRQHandler
- def_irq_default_handler UART0_ERR_IRQHandler
- def_irq_default_handler UART1_RX_TX_IRQHandler
- def_irq_default_handler UART1_ERR_IRQHandler
- def_irq_default_handler UART2_RX_TX_IRQHandler
- def_irq_default_handler UART2_ERR_IRQHandler
- def_irq_default_handler ADC0_IRQHandler
- def_irq_default_handler CMP0_IRQHandler
- def_irq_default_handler CMP1_IRQHandler
- def_irq_default_handler FTM0_IRQHandler
- def_irq_default_handler FTM1_IRQHandler
- def_irq_default_handler CMT_IRQHandler
- def_irq_default_handler RTC_IRQHandler
- def_irq_default_handler RTC_Seconds_IRQHandler
- def_irq_default_handler PIT0_IRQHandler
- def_irq_default_handler PIT1_IRQHandler
- def_irq_default_handler PIT2_IRQHandler
- def_irq_default_handler PIT3_IRQHandler
- def_irq_default_handler PDB0_IRQHandler
- def_irq_default_handler USB0_IRQHandler
- def_irq_default_handler USBDCD_IRQHandler
- def_irq_default_handler TSI0_IRQHandler
- def_irq_default_handler MCG_IRQHandler
- def_irq_default_handler LPTimer_IRQHandler
- def_irq_default_handler PORTA_IRQHandler
- def_irq_default_handler PORTB_IRQHandler
- def_irq_default_handler PORTC_IRQHandler
- def_irq_default_handler PORTD_IRQHandler
- def_irq_default_handler PORTE_IRQHandler
- def_irq_default_handler SWI_IRQHandler
- def_irq_default_handler DEF_IRQHandler
-
-/* Flash protection region, placed at 0x400 */
- .text
- .thumb
- .align 2
- .section .kinetis_flash_config_field,"a",%progbits
-kinetis_flash_config:
- .long 0xffffffff
- .long 0xffffffff
- .long 0xffffffff
- .long 0xfffffffe
-
- .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf
deleted file mode 100644
index e73c38a0c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf
+++ /dev/null
@@ -1,52 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
-define symbol __ICFEDIT_region_NVIC_start__ = 0x1fffe000;
-define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0f7;
-define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0f8;
-define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
-/*-Sizes-*/
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __ICFEDIT_size_cstack__ = 0x600;
-define symbol __ICFEDIT_size_heap__ = 0xC00;
-/**** End of ICF editor section. ###ICF###*/
-
-define symbol __region_RAM2_start__ = 0x20000000;
-define symbol __region_RAM2_end__ = 0x20001fff;
-
-define symbol __FlashConfig_start__ = 0x00000400;
-define symbol __FlashConfig_end__ = 0x0000040f;
-
-define symbol __region_FlexNVM_start__ = 0x10000000;
-define symbol __region_FlexNVM_end__ = 0x10007fff;
-
-define symbol __region_FlexRAM_start__ = 0x14000000;
-define symbol __region_FlexRAM_end__ = 0x140007ff;
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__] | mem:[from __region_FlexNVM_start__ to __region_FlexNVM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
-define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in FlashConfig_region {section FlashConfig};
-
-place in ROM_region { readonly };
-
-place in RAM_region { readwrite, block HEAP, block CSTACK };
-
-place in FlexRAM_region { section .flex_ram };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s
deleted file mode 100644
index cee394eaf..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s
+++ /dev/null
@@ -1,271 +0,0 @@
-/**************************************************
- *
- * Copyright 2010 IAR Systems. All rights reserved.
- *
- * $Revision: 16 $
- *
- **************************************************/
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:ROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK) ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- ; External Interrupts
- DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete
- DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete
- DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete
- DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete
- DCD DMA_ERR_IRQHandler ; 4: DMA Error Interrupt Channels 0-15
- DCD 0 ; 5: Reserved
- DCD FLASH_CC_IRQHandler ; 6: Flash memory command complete
- DCD FLASH_RC_IRQHandler ; 7: Flash memory read collision
- DCD VLD_IRQHandler ; 8: Low Voltage Detect, Low Voltage Warning
- DCD LLWU_IRQHandler ; 9: Low Leakage Wakeup
- DCD WDOG_IRQHandler ;10: WDOG interrupt
- DCD I2C0_IRQHandler ;11: I2C0 interrupt
- DCD SPI0_IRQHandler ;12: SPI 0 interrupt
- DCD I2S0_IRQHandler ;13: I2S 0 interrupt
- DCD I2S1_IRQHandler ;14: I2S 1 interrupt
- DCD UART0_LON_IRQHandler ;15: UART 0 LON intertrupt
- DCD UART0_IRQHandler ;16: UART 0 intertrupt
- DCD UART0_ERR_IRQHandler ;17: UART 0 error intertrupt
- DCD UART1_IRQHandler ;18: UART 1 intertrupt
- DCD UART1_ERR_IRQHandler ;19: UART 1 error intertrupt
- DCD UART2_IRQHandler ;20: UART 2 intertrupt
- DCD UART2_ERR_IRQHandler ;21: UART 2 error intertrupt
- DCD ADC0_IRQHandler ;22: ADC 0 interrupt
- DCD CMP0_IRQHandler ;23: CMP 0 High-speed comparator interrupt
- DCD CMP1_IRQHandler ;24: CMP 1 interrupt
- DCD FTM0_IRQHandler ;25: FTM 0 interrupt
- DCD FTM1_IRQHandler ;26: FTM 1 interrupt
- DCD CMT_IRQHandler ;27: CMT intrrupt
- DCD RTC_ALRM_IRQHandler ;28: RTC Alarm interrupt
- DCD RTC_SEC_IRQHandler ;29: RTC Sec interrupt
- DCD PIT0_IRQHandler ;30: PIT 0 interrupt
- DCD PIT1_IRQHandler ;31: PIT 1 interrupt
- DCD PIT2_IRQHandler ;32: PIT 2 interrupt
- DCD PIT3_IRQHandler ;33: PIT 3 interrupt
- DCD PDB_IRQHandler ;34: PDB interrupt
- DCD USB_OTG_IRQHandler ;35: USB OTG interrupt
- DCD USB_CD_IRQHandler ;36: USB Charger Detect interrupt
- DCD TSI_IRQHandler ;37: TSI interrupt
- DCD MCG_IRQHandler ;38: MCG interrupt
- DCD LPT_IRQHandler ;39: LPT interrupt
- DCD PORTA_IRQHandler ;40: PORT A interrupt
- DCD PORTB_IRQHandler ;41: PORT B interrupt
- DCD PORTC_IRQHandler ;42: PORT C interrupt
- DCD PORTD_IRQHandler ;43: PORT D interrupt
- DCD PORTE_IRQHandler ;44: PORT E interrupt
- DCD SW_IRQHandler ;45: Software initiated interrupt
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;Flash Configuration
-;;16-byte flash configuration field that stores default protection settings (loaded on reset)
-;;and security information that allows the MCU to restrict acces to the FTFL module.
-
-BackDoorK0 EQU 0xFF
-BackDoorK1 EQU 0xFF
-BackDoorK2 EQU 0xFF
-BackDoorK3 EQU 0xFF
-BackDoorK4 EQU 0xFF
-BackDoorK5 EQU 0xFF
-BackDoorK6 EQU 0xFF
-BackDoorK7 EQU 0xFF
-
-nFPROT0 EQU 0x00
-FPROT0 EQU nFPROT0^0xFF
-
-nFPROT1 EQU 0x00
-FPROT1 EQU nFPROT1^0xFF
-
-nFPROT2 EQU 0x00
-FPROT2 EQU nFPROT2^0xFF
-
-nFPROT3 EQU 0x00
-FPROT3 EQU nFPROT3^0xFF
-
-nFEPROT EQU 0x00
-FEPROT EQU nFEPROT^0xFF
-
-nFDPROT EQU 0x00
-FDPROT EQU nFDPROT^0xFF
-
-FOPT EQU 0xFF
-
-FSEC EQU 0xFE
- SECTION FlashConfig:CONST:REORDER:ROOT(2)
-Config:
- DATA
- DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
- DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
- DCB FPROT0, FPROT1, FPROT2, FPROT3
- DCB FSEC, FOPT, FEPROT, FDPROT
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- PUBWEAK HardFault_Handler
- PUBWEAK MemManage_Handler
- PUBWEAK BusFault_Handler
- PUBWEAK UsageFault_Handler
- PUBWEAK SVC_Handler
- PUBWEAK DebugMon_Handler
- PUBWEAK PendSV_Handler
- PUBWEAK SysTick_Handler
- PUBWEAK DMA0_IRQHandler
- PUBWEAK DMA1_IRQHandler
- PUBWEAK DMA2_IRQHandler
- PUBWEAK DMA3_IRQHandler
- PUBWEAK DMA_ERR_IRQHandler
- PUBWEAK FLASH_CC_IRQHandler
- PUBWEAK FLASH_RC_IRQHandler
- PUBWEAK VLD_IRQHandler
- PUBWEAK LLWU_IRQHandler
- PUBWEAK WDOG_IRQHandler
- PUBWEAK I2C0_IRQHandler
- PUBWEAK SPI0_IRQHandler
- PUBWEAK I2S0_IRQHandler
- PUBWEAK I2S1_IRQHandler
- PUBWEAK UART0_LON_IRQHandler
- PUBWEAK UART0_IRQHandler
- PUBWEAK UART0_ERR_IRQHandler
- PUBWEAK UART1_IRQHandler
- PUBWEAK UART1_ERR_IRQHandler
- PUBWEAK UART2_IRQHandler
- PUBWEAK UART2_ERR_IRQHandler
- PUBWEAK ADC0_IRQHandler
- PUBWEAK CMP0_IRQHandler
- PUBWEAK CMP1_IRQHandler
- PUBWEAK FTM0_IRQHandler
- PUBWEAK FTM1_IRQHandler
- PUBWEAK CMT_IRQHandler
- PUBWEAK RTC_ALRM_IRQHandler
- PUBWEAK RTC_SEC_IRQHandler
- PUBWEAK PIT0_IRQHandler
- PUBWEAK PIT1_IRQHandler
- PUBWEAK PIT2_IRQHandler
- PUBWEAK PIT3_IRQHandler
- PUBWEAK PDB_IRQHandler
- PUBWEAK USB_OTG_IRQHandler
- PUBWEAK USB_CD_IRQHandler
- PUBWEAK TSI_IRQHandler
- PUBWEAK MCG_IRQHandler
- PUBWEAK LPT_IRQHandler
- PUBWEAK PORTA_IRQHandler
- PUBWEAK PORTB_IRQHandler
- PUBWEAK PORTC_IRQHandler
- PUBWEAK PORTD_IRQHandler
- PUBWEAK PORTE_IRQHandler
- PUBWEAK SW_IRQHandler
-
- SECTION .text:CODE:REORDER:NOROOT(1)
- THUMB
-NMI_Handler
-HardFault_Handler
-MemManage_Handler
-BusFault_Handler
-UsageFault_Handler
-SVC_Handler
-DebugMon_Handler
-PendSV_Handler
-SysTick_Handler
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-DMA_ERR_IRQHandler
-FLASH_CC_IRQHandler
-FLASH_RC_IRQHandler
-VLD_IRQHandler
-LLWU_IRQHandler
-WDOG_IRQHandler
-I2C0_IRQHandler
-SPI0_IRQHandler
-I2S0_IRQHandler
-I2S1_IRQHandler
-UART0_LON_IRQHandler
-UART0_IRQHandler
-UART0_ERR_IRQHandler
-UART1_IRQHandler
-UART1_ERR_IRQHandler
-UART2_IRQHandler
-UART2_ERR_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-CMP1_IRQHandler
-FTM0_IRQHandler
-FTM1_IRQHandler
-CMT_IRQHandler
-RTC_ALRM_IRQHandler
-RTC_SEC_IRQHandler
-PIT0_IRQHandler
-PIT1_IRQHandler
-PIT2_IRQHandler
-PIT3_IRQHandler
-PDB_IRQHandler
-USB_OTG_IRQHandler
-USB_CD_IRQHandler
-TSI_IRQHandler
-MCG_IRQHandler
-LPT_IRQHandler
-PORTA_IRQHandler
-PORTB_IRQHandler
-PORTC_IRQHandler
-PORTD_IRQHandler
-PORTE_IRQHandler
-SW_IRQHandler
-Default_Handler
-
- B Default_Handler
- END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h
deleted file mode 100644
index 099017c7f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
- *
- * A generic CMSIS include header, pulling in LPC11U24 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "MK20D5.h"
-#include "cmsis_nvic.h"
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c
deleted file mode 100644
index 16d1b1f7e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2015 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- uint32_t i;
-
- // Copy and switch to dynamic vectors if the first time called
- if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
- uint32_t *old_vectors = vectors;
- vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- for (i=0; i<NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
- }
- SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
- }
- vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- return vectors[IRQn + 16];
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h
deleted file mode 100644
index 04cf15b21..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2015 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c
deleted file mode 100644
index 9cd3c16b0..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
-** ###################################################################
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
-** K20P32M50SF0RM Rev. 1, Oct 2011
-** K20P48M50SF0RM Rev. 1, Oct 2011
-**
-** Version: rev. 1.0, 2011-12-15
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2011-12-15)
-** Initial version
-**
-** ###################################################################
-*/
-
-/**
- * @file MK20D5
- * @version 1.0
- * @date 2011-12-15
- * @brief Device specific configuration file for MK20D5 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "MK20D5.h"
-
-#define DISABLE_WDOG 1
-
-#define CLOCK_SETUP 1
-/* Predefined clock setups
- 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
- Reference clock source for MCG module is the slow internal clock source 32.768kHz
- Core clock = 41.94MHz, BusClock = 41.94MHz
- 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
- Reference clock source for MCG module is an external crystal 8MHz
- Core clock = 48MHz, BusClock = 48MHz
- 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
- Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
- Core clock = 8MHz, BusClock = 8MHz
-*/
-
-/*----------------------------------------------------------------------------
- Define clock source values
- *----------------------------------------------------------------------------*/
-#if (CLOCK_SETUP == 0)
- #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
-#elif (CLOCK_SETUP == 1)
- #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
-#elif (CLOCK_SETUP == 2)
- #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
-#endif /* (CLOCK_SETUP == 2) */
-
-
-/* ----------------------------------------------------------------------------
- -- Core clock
- ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
- -- SystemInit()
- ---------------------------------------------------------------------------- */
-
-void SystemInit (void) {
-#if (DISABLE_WDOG)
- /* Disable the WDOG module */
- /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
- WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
- /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
- WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
- /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
- WDOG->STCTRLH = (uint16_t)0x01D2u;
-#endif /* (DISABLE_WDOG) */
-#if (CLOCK_SETUP == 0)
- /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
- SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
- /* Switch to FEI Mode */
- /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = (uint8_t)0x06u;
- /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
- MCG->C2 = (uint8_t)0x00u;
- /* MCG_C4: DMX32=0,DRST_DRS=1 */
- MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
- /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
- MCG->C5 = (uint8_t)0x00u;
- /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x00u;
- while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
- }
- while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
- }
-#elif (CLOCK_SETUP == 1)
- /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
- SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
- /* Switch to FBE Mode */
- /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- OSC0->CR = (uint8_t)0x00u;
- /* MCG->C7: OSCSEL=0 */
- MCG->C7 = (uint8_t)0x00u;
- /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- MCG->C2 = (uint8_t)0x24u;
- /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = (uint8_t)0x9Au;
- /* MCG->C4: DMX32=0,DRST_DRS=0 */
- MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
- /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
- MCG->C5 = (uint8_t)0x03u;
- /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x00u;
- while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
- }
-#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
- while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
- }
-#endif
- while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
- }
- /* Switch to PBE Mode */
- /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
- MCG->C5 = (uint8_t)0x03u;
- /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x40u;
- while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
- }
- while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
- }
- /* Switch to PEE Mode */
- /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = (uint8_t)0x1Au;
- while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
- }
- while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
- }
-#elif (CLOCK_SETUP == 2)
- /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
- SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
- /* Switch to FBE Mode */
- /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- OSC0->CR = (uint8_t)0x00u;
- /* MCG->C7: OSCSEL=0 */
- MCG->C7 = (uint8_t)0x00u;
- /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- MCG->C2 = (uint8_t)0x24u;
- /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = (uint8_t)0x9Au;
- /* MCG->C4: DMX32=0,DRST_DRS=0 */
- MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
- /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
- MCG->C5 = (uint8_t)0x00u;
- /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x00u;
- while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
- }
-#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
- while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
- }
-#endif
- while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
- }
- /* Switch to BLPE Mode */
- /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- MCG->C2 = (uint8_t)0x24u;
-#endif /* (CLOCK_SETUP == 2) */
-}
-
-/* ----------------------------------------------------------------------------
- -- SystemCoreClockUpdate()
- ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
- uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
- uint8_t Divider;
-
- if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
- /* Output of FLL or PLL is selected */
- if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
- /* FLL is selected */
- if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
- /* External reference clock is selected */
- if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
- MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
- } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
- } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
- MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
- if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
- MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
- } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
- } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
- MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
- } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
- /* Select correct multiplier to calculate the MCG output clock */
- switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
- case 0x0u:
- MCGOUTClock *= 640u;
- break;
- case 0x20u:
- MCGOUTClock *= 1280u;
- break;
- case 0x40u:
- MCGOUTClock *= 1920u;
- break;
- case 0x60u:
- MCGOUTClock *= 2560u;
- break;
- case 0x80u:
- MCGOUTClock *= 732u;
- break;
- case 0xA0u:
- MCGOUTClock *= 1464u;
- break;
- case 0xC0u:
- MCGOUTClock *= 2197u;
- break;
- case 0xE0u:
- MCGOUTClock *= 2929u;
- break;
- default:
- break;
- }
- } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
- /* PLL is selected */
- Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
- MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
- Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
- MCGOUTClock *= Divider; /* Calculate the MCG output clock */
- } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
- } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
- /* Internal reference clock is selected */
- if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
- MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
- } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
- MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
- } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
- } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
- /* External reference clock is selected */
- if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
- MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
- } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
- } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
- /* Reserved value */
- return;
- } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
- SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h
deleted file mode 100644
index 738791790..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-** ###################################################################
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
-** K20P32M50SF0RM Rev. 1, Oct 2011
-** K20P48M50SF0RM Rev. 1, Oct 2011
-**
-** Version: rev. 2.0, 2012-03-19
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2011-12-15)
-** Initial version
-** - rev. 2.0 (2012-03-19)
-** PDB Peripheral register structure updated.
-** DMA Registers and bits for unsupported DMA channels removed.
-**
-** ###################################################################
-*/
-
-/**
- * @file MK20D5
- * @version 2.0
- * @date 2012-03-19
- * @brief Device specific configuration file for MK20D5 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef SYSTEM_MK20D5_H_
-#define SYSTEM_MK20D5_H_ /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #if !defined(SYSTEM_MK20D5_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h
deleted file mode 100644
index 041f99782..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h
+++ /dev/null
@@ -1,6032 +0,0 @@
-/*
-** ###################################################################
-** Processors: MK20DX64VLH7
-** MK20DX128VLH7
-** MK20DX256VLH7
-** MK20DX64VLK7
-** MK20DX128VLK7
-** MK20DX256VLK7
-** MK20DX128VLL7
-** MK20DX256VLL7
-** MK20DX64VMB7
-** MK20DX128VMB7
-** MK20DX256VMB7
-** MK20DX128VML7
-** MK20DX256VML7
-**
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011
-** Version: rev. 1.0, 2012-01-15
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2012-01-15)
-** Initial public version.
-**
-** ###################################################################
-*/
-
-/**
- * @file MK20DX256.h
- * @version 2.0
- * @date 2012-03-19
- * @brief CMSIS Peripheral Access Layer for MK20DX256
- *
- * CMSIS Peripheral Access Layer for MK20DX256
- */
-
-#if !defined(MK20DX256_H_)
-#define MK20DX256_H_ /**< Symbol preventing repeated inclusion */
-#define MCU_MK20DX256
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0200u
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
-
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
-
-/* ----------------------------------------------------------------------------
- -- Interrupt vector numbers
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-typedef enum IRQn {
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
-
- /* Device specific interrupts */
-
- DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
- DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
- DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
- DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
- DMA4_IRQn = 4,
- DMA5_IRQn = 5,
- DMA6_IRQn = 6,
- DMA7_IRQn = 7,
- DMA8_IRQn = 8,
- DMA9_IRQn = 9,
- DMA10_IRQn = 10,
- DMA11_IRQn = 11,
- DMA12_IRQn = 12,
- DMA13_IRQn = 13,
- DMA14_IRQn = 14,
- DMA15_IRQn = 15,
- DMA_Error_IRQn = 16, /**< DMA error interrupt */
- Reserved33_IRQn = 17,
- FTFL_IRQn = 18, /**< FTFL interrupt */
- Read_Collision_IRQn = 19, /**< Read collision interrupt */
- LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
- LLW_IRQn = 21, /**< Low Leakage Wakeup */
- Watchdog_IRQn = 22, /**< WDOG interrupt */
- Reserved39_IRQn = 23,
- I2C0_IRQn = 24, /**< I2C0 interrupt */
- I2C1_IRQn = 25,
- SPI0_IRQn = 26, /**< SPI0 interrupt */
- SPI1_IRQn = 27,
- Reserved44_IRQn = 28,
- CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */
- CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */
- CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */
- CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */
- CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */
- CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */
- I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */
- I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */
- Reserved53_IRQn = 37,
- Reserved54_IRQn = 38,
- Reserved55_IRQn = 39,
- Reserved56_IRQn = 40,
- Reserved57_IRQn = 41,
- Reserved58_IRQn = 42,
- Reserved59_IRQn = 43,
- UART0_LON_IRQn = 44, /**< UART0 LON interrupt */
- UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */
- UART0_ERR_IRQn = 46, /**< UART0 error interrupt */
- UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */
- UART1_ERR_IRQn = 48, /**< UART1 error interrupt */
- UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */
- UART2_ERR_IRQn = 50, /**< UART2 error interrupt */
- Reserved67_IRQn = 51,
- Reserved68_IRQn = 52,
- Reserved69_IRQn = 53,
- Reserved70_IRQn = 54,
- Reserved71_IRQn = 55,
- Reserved72_IRQn = 56,
- ADC0_IRQn = 57, /**< ADC0 interrupt */
- ADC1_IRQn = 58,
- CMP0_IRQn = 59, /**< CMP0 interrupt */
- CMP1_IRQn = 60, /**< CMP1 interrupt */
- CMP2_IRQn = 61,
- FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
- FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
- FTM2_IRQn = 64,
- CMT_IRQn = 65, /**< CMT interrupt */
- RTC_IRQn = 66, /**< RTC interrupt */
- RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */
- PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
- PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
- PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
- PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
- PDB0_IRQn = 72, /**< PDB0 interrupt */
- USB0_IRQn = 73, /**< USB0 interrupt */
- USBDCD_IRQn = 74, /**< USBDCD interrupt */
- Reserved91_IRQn = 75,
- Reserved92_IRQn = 76,
- Reserved93_IRQn = 77,
- Reserved94_IRQn = 78,
- Reserved95_IRQn = 79,
- Reserved96_IRQn = 80,
- DAC0_IRQn = 81,
- Reserved98_IRQn = 82,
- TSI0_IRQn = 83, /**< TSI0 interrupt */
- MCG_IRQn = 84, /**< MCG interrupt */
- LPTimer_IRQn = 85, /**< LPTimer interrupt */
- Reserved102_IRQn = 86,
- PORTA_IRQn = 87, /**< Port A interrupt */
- PORTB_IRQn = 88, /**< Port B interrupt */
- PORTC_IRQn = 89, /**< Port C interrupt */
- PORTD_IRQn = 90, /**< Port D interrupt */
- PORTE_IRQn = 91, /**< Port E interrupt */
- Reserved108_IRQn = 92,
- Reserved109_IRQn = 93,
- SWI_IRQn = 94 /**< Software interrupt */
-
-} IRQn_Type;
-
-/**
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
- -- Cortex M4 Core Configuration
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
- * @{
- */
-
-#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-
-#include "core_cm4.h" /* Core Peripheral Access Layer */
-#include "system_MK20DX256.h" /* Device specific configuration file */
-
-/**
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
- -- Device Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
- -- ADC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
- __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
- __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
- __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
- __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
- __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
- __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
- __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
- __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
- __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
- __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
- __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
- __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
- __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
- __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
- __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
- __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
- __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
- __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
- __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
- __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
- __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
- __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
- __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
-} ADC_Type;
-
-/* ----------------------------------------------------------------------------
- -- ADC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
-
-/**
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x4003B000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-
-/**
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
- * @{
- */
-
-/** CMP - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
- __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
- __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
- __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
- __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
- __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type;
-
-/* ----------------------------------------------------------------------------
- -- CMP Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Register_Masks CMP Register Masks
- * @{
- */
-
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-
-/**
- * @}
- */ /* end of group CMP_Register_Masks */
-
-
-/* CMP - Peripheral instance base addresses */
-/** Peripheral CMP0 base address */
-#define CMP0_BASE (0x40073000u)
-/** Peripheral CMP0 base pointer */
-#define CMP0 ((CMP_Type *)CMP0_BASE)
-/** Peripheral CMP1 base address */
-#define CMP1_BASE (0x40073008u)
-/** Peripheral CMP1 base pointer */
-#define CMP1 ((CMP_Type *)CMP1_BASE)
-
-/**
- * @}
- */ /* end of group CMP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
- * @{
- */
-
-/** CMT - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
- __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
- __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
- __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
- __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
- __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
- __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
- __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
- __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
- __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
- __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
- __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
-} CMT_Type;
-
-/* ----------------------------------------------------------------------------
- -- CMT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMT_Register_Masks CMT Register Masks
- * @{
- */
-
-/* CGH1 Bit Fields */
-#define CMT_CGH1_PH_MASK 0xFFu
-#define CMT_CGH1_PH_SHIFT 0
-#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
-/* CGL1 Bit Fields */
-#define CMT_CGL1_PL_MASK 0xFFu
-#define CMT_CGL1_PL_SHIFT 0
-#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
-/* CGH2 Bit Fields */
-#define CMT_CGH2_SH_MASK 0xFFu
-#define CMT_CGH2_SH_SHIFT 0
-#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
-/* CGL2 Bit Fields */
-#define CMT_CGL2_SL_MASK 0xFFu
-#define CMT_CGL2_SL_SHIFT 0
-#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
-/* OC Bit Fields */
-#define CMT_OC_IROPEN_MASK 0x20u
-#define CMT_OC_IROPEN_SHIFT 5
-#define CMT_OC_CMTPOL_MASK 0x40u
-#define CMT_OC_CMTPOL_SHIFT 6
-#define CMT_OC_IROL_MASK 0x80u
-#define CMT_OC_IROL_SHIFT 7
-/* MSC Bit Fields */
-#define CMT_MSC_MCGEN_MASK 0x1u
-#define CMT_MSC_MCGEN_SHIFT 0
-#define CMT_MSC_EOCIE_MASK 0x2u
-#define CMT_MSC_EOCIE_SHIFT 1
-#define CMT_MSC_FSK_MASK 0x4u
-#define CMT_MSC_FSK_SHIFT 2
-#define CMT_MSC_BASE_MASK 0x8u
-#define CMT_MSC_BASE_SHIFT 3
-#define CMT_MSC_EXSPC_MASK 0x10u
-#define CMT_MSC_EXSPC_SHIFT 4
-#define CMT_MSC_CMTDIV_MASK 0x60u
-#define CMT_MSC_CMTDIV_SHIFT 5
-#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
-#define CMT_MSC_EOCF_MASK 0x80u
-#define CMT_MSC_EOCF_SHIFT 7
-/* CMD1 Bit Fields */
-#define CMT_CMD1_MB_MASK 0xFFu
-#define CMT_CMD1_MB_SHIFT 0
-#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
-/* CMD2 Bit Fields */
-#define CMT_CMD2_MB_MASK 0xFFu
-#define CMT_CMD2_MB_SHIFT 0
-#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
-/* CMD3 Bit Fields */
-#define CMT_CMD3_SB_MASK 0xFFu
-#define CMT_CMD3_SB_SHIFT 0
-#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
-/* CMD4 Bit Fields */
-#define CMT_CMD4_SB_MASK 0xFFu
-#define CMT_CMD4_SB_SHIFT 0
-#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
-/* PPS Bit Fields */
-#define CMT_PPS_PPSDIV_MASK 0xFu
-#define CMT_PPS_PPSDIV_SHIFT 0
-#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
-/* DMA Bit Fields */
-#define CMT_DMA_DMA_MASK 0x1u
-#define CMT_DMA_DMA_SHIFT 0
-
-/**
- * @}
- */ /* end of group CMT_Register_Masks */
-
-
-/* CMT - Peripheral instance base addresses */
-/** Peripheral CMT base address */
-#define CMT_BASE (0x40062000u)
-/** Peripheral CMT base pointer */
-#define CMT ((CMT_Type *)CMT_BASE)
-
-/**
- * @}
- */ /* end of group CMT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CRC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
- * @{
- */
-
-/** CRC - Register Layout Typedef */
-typedef struct {
- union { /* offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
- __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
- } ACCESS16BIT;
- __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
- __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
- __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
- __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
- } ACCESS8BIT;
- };
- union { /* offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
- __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
- } GPOLY_ACCESS16BIT;
- __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
- __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
- __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
- __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
- } GPOLY_ACCESS8BIT;
- };
- union { /* offset: 0x8 */
- __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
- struct { /* offset: 0x8 */
- uint8_t RESERVED_0[3];
- __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
- } CTRL_ACCESS8BIT;
- };
-} CRC_Type;
-
-/* ----------------------------------------------------------------------------
- -- CRC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CRC_Register_Masks CRC Register Masks
- * @{
- */
-
-/* CRCL Bit Fields */
-#define CRC_CRCL_CRCL_MASK 0xFFFFu
-#define CRC_CRCL_CRCL_SHIFT 0
-#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
-/* CRCH Bit Fields */
-#define CRC_CRCH_CRCH_MASK 0xFFFFu
-#define CRC_CRCH_CRCH_SHIFT 0
-#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
-/* CRC Bit Fields */
-#define CRC_CRC_LL_MASK 0xFFu
-#define CRC_CRC_LL_SHIFT 0
-#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
-#define CRC_CRC_LU_MASK 0xFF00u
-#define CRC_CRC_LU_SHIFT 8
-#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
-#define CRC_CRC_HL_MASK 0xFF0000u
-#define CRC_CRC_HL_SHIFT 16
-#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
-#define CRC_CRC_HU_MASK 0xFF000000u
-#define CRC_CRC_HU_SHIFT 24
-#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
-/* CRCLL Bit Fields */
-#define CRC_CRCLL_CRCLL_MASK 0xFFu
-#define CRC_CRCLL_CRCLL_SHIFT 0
-#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
-/* CRCLU Bit Fields */
-#define CRC_CRCLU_CRCLU_MASK 0xFFu
-#define CRC_CRCLU_CRCLU_SHIFT 0
-#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
-/* CRCHL Bit Fields */
-#define CRC_CRCHL_CRCHL_MASK 0xFFu
-#define CRC_CRCHL_CRCHL_SHIFT 0
-#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
-/* CRCHU Bit Fields */
-#define CRC_CRCHU_CRCHU_MASK 0xFFu
-#define CRC_CRCHU_CRCHU_SHIFT 0
-#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT 0
-#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT 0
-#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK 0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT 0
-#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT 16
-#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
-#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
-#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
-#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
-#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK 0x1000000u
-#define CRC_CTRL_TCRC_SHIFT 24
-#define CRC_CTRL_WAS_MASK 0x2000000u
-#define CRC_CTRL_WAS_SHIFT 25
-#define CRC_CTRL_FXOR_MASK 0x4000000u
-#define CRC_CTRL_FXOR_SHIFT 26
-#define CRC_CTRL_TOTR_MASK 0x30000000u
-#define CRC_CTRL_TOTR_SHIFT 28
-#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK 0xC0000000u
-#define CRC_CTRL_TOT_SHIFT 30
-#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK 0x1u
-#define CRC_CTRLHU_TCRC_SHIFT 0
-#define CRC_CTRLHU_WAS_MASK 0x2u
-#define CRC_CTRLHU_WAS_SHIFT 1
-#define CRC_CTRLHU_FXOR_MASK 0x4u
-#define CRC_CTRLHU_FXOR_SHIFT 2
-#define CRC_CTRLHU_TOTR_MASK 0x30u
-#define CRC_CTRLHU_TOTR_SHIFT 4
-#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK 0xC0u
-#define CRC_CTRLHU_TOT_SHIFT 6
-#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
-
-/**
- * @}
- */ /* end of group CRC_Register_Masks */
-
-
-/* CRC - Peripheral instance base addresses */
-/** Peripheral CRC base address */
-#define CRC_BASE (0x40032000u)
-/** Peripheral CRC base pointer */
-#define CRC0 ((CRC_Type *)CRC_BASE)
-
-/**
- * @}
- */ /* end of group CRC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DAC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
- * @{
- */
-
-/** DAC - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x2 */
- __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
- __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
- } DAT[16];
- __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
- __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
- __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
- __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type, *DAC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DAC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Register_Masks DAC Register Masks
- * @{
- */
-
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-#define DAC_SR_DACBFWMF_MASK 0x4u
-#define DAC_SR_DACBFWMF_SHIFT 2
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_DACBWIEN_MASK 0x4u
-#define DAC_C0_DACBWIEN_SHIFT 2
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFMD_MASK 0x6u
-#define DAC_C1_DACBFMD_SHIFT 1
-#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
-#define DAC_C1_DACBFWM_MASK 0x18u
-#define DAC_C1_DACBFWM_SHIFT 3
-#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0xFu
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
-#define DAC_C2_DACBFRP_MASK 0xF0u
-#define DAC_C2_DACBFRP_SHIFT 4
-#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
-
-/**
- * @}
- */ /* end of group DAC_Register_Masks */
-
-
-/* DAC - Peripheral instance base addresses */
-/** Peripheral DAC0 base address */
-#define DAC0_BASE (0x400CC000u)
-/** Peripheral DAC0 base pointer */
-#define DAC0 ((DAC_Type *)DAC0_BASE)
-/** Array initializer of DAC peripheral base pointers */
-#define DAC_BASES { DAC0 }
-
-/**
- * @}
- */ /* end of group DAC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CR; /**< Control Register, offset: 0x0 */
- __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
- uint8_t RESERVED_0[4];
- __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
- uint8_t RESERVED_1[4];
- __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
- __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
- __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
- __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
- __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
- __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
- __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
- __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
- __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
- uint8_t RESERVED_2[4];
- __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
- uint8_t RESERVED_3[4];
- __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
- uint8_t RESERVED_4[4];
- __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
- uint8_t RESERVED_5[200];
- __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
- __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
- __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
- __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
- uint8_t RESERVED_6[3836];
- struct { /* offset: 0x1000, array step: 0x20 */
- __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
- __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
- __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
- union { /* offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
- };
- __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
- __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
- __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
- union { /* offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
- };
- __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
- __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
- union { /* offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
- };
- } TCD[4];
-} DMA_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK 0x2u
-#define DMA_CR_EDBG_SHIFT 1
-#define DMA_CR_ERCA_MASK 0x4u
-#define DMA_CR_ERCA_SHIFT 2
-#define DMA_CR_HOE_MASK 0x10u
-#define DMA_CR_HOE_SHIFT 4
-#define DMA_CR_HALT_MASK 0x20u
-#define DMA_CR_HALT_SHIFT 5
-#define DMA_CR_CLM_MASK 0x40u
-#define DMA_CR_CLM_SHIFT 6
-#define DMA_CR_EMLM_MASK 0x80u
-#define DMA_CR_EMLM_SHIFT 7
-#define DMA_CR_ECX_MASK 0x10000u
-#define DMA_CR_ECX_SHIFT 16
-#define DMA_CR_CX_MASK 0x20000u
-#define DMA_CR_CX_SHIFT 17
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK 0x1u
-#define DMA_ES_DBE_SHIFT 0
-#define DMA_ES_SBE_MASK 0x2u
-#define DMA_ES_SBE_SHIFT 1
-#define DMA_ES_SGE_MASK 0x4u
-#define DMA_ES_SGE_SHIFT 2
-#define DMA_ES_NCE_MASK 0x8u
-#define DMA_ES_NCE_SHIFT 3
-#define DMA_ES_DOE_MASK 0x10u
-#define DMA_ES_DOE_SHIFT 4
-#define DMA_ES_DAE_MASK 0x20u
-#define DMA_ES_DAE_SHIFT 5
-#define DMA_ES_SOE_MASK 0x40u
-#define DMA_ES_SOE_SHIFT 6
-#define DMA_ES_SAE_MASK 0x80u
-#define DMA_ES_SAE_SHIFT 7
-#define DMA_ES_ERRCHN_MASK 0xF00u
-#define DMA_ES_ERRCHN_SHIFT 8
-#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK 0x4000u
-#define DMA_ES_CPE_SHIFT 14
-#define DMA_ES_ECX_MASK 0x10000u
-#define DMA_ES_ECX_SHIFT 16
-#define DMA_ES_VLD_MASK 0x80000000u
-#define DMA_ES_VLD_SHIFT 31
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK 0x1u
-#define DMA_ERQ_ERQ0_SHIFT 0
-#define DMA_ERQ_ERQ1_MASK 0x2u
-#define DMA_ERQ_ERQ1_SHIFT 1
-#define DMA_ERQ_ERQ2_MASK 0x4u
-#define DMA_ERQ_ERQ2_SHIFT 2
-#define DMA_ERQ_ERQ3_MASK 0x8u
-#define DMA_ERQ_ERQ3_SHIFT 3
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK 0x1u
-#define DMA_EEI_EEI0_SHIFT 0
-#define DMA_EEI_EEI1_MASK 0x2u
-#define DMA_EEI_EEI1_SHIFT 1
-#define DMA_EEI_EEI2_MASK 0x4u
-#define DMA_EEI_EEI2_SHIFT 2
-#define DMA_EEI_EEI3_MASK 0x8u
-#define DMA_EEI_EEI3_SHIFT 3
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK 0xFu
-#define DMA_CEEI_CEEI_SHIFT 0
-#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK 0x40u
-#define DMA_CEEI_CAEE_SHIFT 6
-#define DMA_CEEI_NOP_MASK 0x80u
-#define DMA_CEEI_NOP_SHIFT 7
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK 0xFu
-#define DMA_SEEI_SEEI_SHIFT 0
-#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK 0x40u
-#define DMA_SEEI_SAEE_SHIFT 6
-#define DMA_SEEI_NOP_MASK 0x80u
-#define DMA_SEEI_NOP_SHIFT 7
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK 0xFu
-#define DMA_CERQ_CERQ_SHIFT 0
-#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK 0x40u
-#define DMA_CERQ_CAER_SHIFT 6
-#define DMA_CERQ_NOP_MASK 0x80u
-#define DMA_CERQ_NOP_SHIFT 7
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK 0xFu
-#define DMA_SERQ_SERQ_SHIFT 0
-#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK 0x40u
-#define DMA_SERQ_SAER_SHIFT 6
-#define DMA_SERQ_NOP_MASK 0x80u
-#define DMA_SERQ_NOP_SHIFT 7
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK 0xFu
-#define DMA_CDNE_CDNE_SHIFT 0
-#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK 0x40u
-#define DMA_CDNE_CADN_SHIFT 6
-#define DMA_CDNE_NOP_MASK 0x80u
-#define DMA_CDNE_NOP_SHIFT 7
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK 0xFu
-#define DMA_SSRT_SSRT_SHIFT 0
-#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK 0x40u
-#define DMA_SSRT_SAST_SHIFT 6
-#define DMA_SSRT_NOP_MASK 0x80u
-#define DMA_SSRT_NOP_SHIFT 7
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK 0xFu
-#define DMA_CERR_CERR_SHIFT 0
-#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK 0x40u
-#define DMA_CERR_CAEI_SHIFT 6
-#define DMA_CERR_NOP_MASK 0x80u
-#define DMA_CERR_NOP_SHIFT 7
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK 0xFu
-#define DMA_CINT_CINT_SHIFT 0
-#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK 0x40u
-#define DMA_CINT_CAIR_SHIFT 6
-#define DMA_CINT_NOP_MASK 0x80u
-#define DMA_CINT_NOP_SHIFT 7
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK 0x1u
-#define DMA_INT_INT0_SHIFT 0
-#define DMA_INT_INT1_MASK 0x2u
-#define DMA_INT_INT1_SHIFT 1
-#define DMA_INT_INT2_MASK 0x4u
-#define DMA_INT_INT2_SHIFT 2
-#define DMA_INT_INT3_MASK 0x8u
-#define DMA_INT_INT3_SHIFT 3
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK 0x1u
-#define DMA_ERR_ERR0_SHIFT 0
-#define DMA_ERR_ERR1_MASK 0x2u
-#define DMA_ERR_ERR1_SHIFT 1
-#define DMA_ERR_ERR2_MASK 0x4u
-#define DMA_ERR_ERR2_SHIFT 2
-#define DMA_ERR_ERR3_MASK 0x8u
-#define DMA_ERR_ERR3_SHIFT 3
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK 0x1u
-#define DMA_HRS_HRS0_SHIFT 0
-#define DMA_HRS_HRS1_MASK 0x2u
-#define DMA_HRS_HRS1_SHIFT 1
-#define DMA_HRS_HRS2_MASK 0x4u
-#define DMA_HRS_HRS2_SHIFT 2
-#define DMA_HRS_HRS3_MASK 0x8u
-#define DMA_HRS_HRS3_SHIFT 3
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK 0xFu
-#define DMA_DCHPRI3_CHPRI_SHIFT 0
-#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK 0x40u
-#define DMA_DCHPRI3_DPA_SHIFT 6
-#define DMA_DCHPRI3_ECP_MASK 0x80u
-#define DMA_DCHPRI3_ECP_SHIFT 7
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK 0xFu
-#define DMA_DCHPRI2_CHPRI_SHIFT 0
-#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK 0x40u
-#define DMA_DCHPRI2_DPA_SHIFT 6
-#define DMA_DCHPRI2_ECP_MASK 0x80u
-#define DMA_DCHPRI2_ECP_SHIFT 7
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK 0xFu
-#define DMA_DCHPRI1_CHPRI_SHIFT 0
-#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK 0x40u
-#define DMA_DCHPRI1_DPA_SHIFT 6
-#define DMA_DCHPRI1_ECP_MASK 0x80u
-#define DMA_DCHPRI1_ECP_SHIFT 7
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK 0xFu
-#define DMA_DCHPRI0_CHPRI_SHIFT 0
-#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK 0x40u
-#define DMA_DCHPRI0_DPA_SHIFT 6
-#define DMA_DCHPRI0_ECP_MASK 0x80u
-#define DMA_DCHPRI0_ECP_SHIFT 7
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT 0
-#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK 0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT 0
-#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK 0x7u
-#define DMA_ATTR_DSIZE_SHIFT 0
-#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK 0xF8u
-#define DMA_ATTR_DMOD_SHIFT 3
-#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK 0x700u
-#define DMA_ATTR_SSIZE_SHIFT 8
-#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK 0xF800u
-#define DMA_ATTR_SMOD_SHIFT 11
-#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
-#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT 0
-#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT 0
-#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK 0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT 0
-#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT 0
-#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT 0
-#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
-#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK 0x1u
-#define DMA_CSR_START_SHIFT 0
-#define DMA_CSR_INTMAJOR_MASK 0x2u
-#define DMA_CSR_INTMAJOR_SHIFT 1
-#define DMA_CSR_INTHALF_MASK 0x4u
-#define DMA_CSR_INTHALF_SHIFT 2
-#define DMA_CSR_DREQ_MASK 0x8u
-#define DMA_CSR_DREQ_SHIFT 3
-#define DMA_CSR_ESG_MASK 0x10u
-#define DMA_CSR_ESG_SHIFT 4
-#define DMA_CSR_MAJORELINK_MASK 0x20u
-#define DMA_CSR_MAJORELINK_SHIFT 5
-#define DMA_CSR_ACTIVE_MASK 0x40u
-#define DMA_CSR_ACTIVE_SHIFT 6
-#define DMA_CSR_DONE_MASK 0x80u
-#define DMA_CSR_DONE_SHIFT 7
-#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
-#define DMA_CSR_MAJORLINKCH_SHIFT 8
-#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK 0xC000u
-#define DMA_CSR_BWC_SHIFT 14
-#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT 0
-#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT 0
-#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
-
-/**
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA base address */
-#define DMA_BASE (0x40008000u)
-/** Peripheral DMA base pointer */
-#define DMA0 ((DMA_Type *)DMA_BASE)
-
-/**
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
- * @{
- */
-
-/** DMAMUX - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
- * @{
- */
-
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-
-/**
- * @}
- */ /* end of group DMAMUX_Register_Masks */
-
-
-/* DMAMUX - Peripheral instance base addresses */
-/** Peripheral DMAMUX base address */
-#define DMAMUX_BASE (0x40021000u)
-/** Peripheral DMAMUX base pointer */
-#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
-
-/**
- * @}
- */ /* end of group DMAMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- EWM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
- * @{
- */
-
-/** EWM - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
- __O uint8_t SERV; /**< Service Register, offset: 0x1 */
- __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
- __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
-} EWM_Type;
-
-/* ----------------------------------------------------------------------------
- -- EWM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
-
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK 0x1u
-#define EWM_CTRL_EWMEN_SHIFT 0
-#define EWM_CTRL_ASSIN_MASK 0x2u
-#define EWM_CTRL_ASSIN_SHIFT 1
-#define EWM_CTRL_INEN_MASK 0x4u
-#define EWM_CTRL_INEN_SHIFT 2
-#define EWM_CTRL_INTEN_MASK 0x8u
-#define EWM_CTRL_INTEN_SHIFT 3
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK 0xFFu
-#define EWM_SERV_SERVICE_SHIFT 0
-#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK 0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT 0
-#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK 0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT 0
-#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
-
-/**
- * @}
- */ /* end of group EWM_Register_Masks */
-
-
-/* EWM - Peripheral instance base addresses */
-/** Peripheral EWM base address */
-#define EWM_BASE (0x40061000u)
-/** Peripheral EWM base pointer */
-#define EWM ((EWM_Type *)EWM_BASE)
-
-/**
- * @}
- */ /* end of group EWM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
- * @{
- */
-
-/** FMC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
- __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
- uint8_t RESERVED_0[248];
- struct { /* offset: 0x100, array step: 0x20 */
- __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
- uint8_t RESERVED_0[24];
- } TAG_WAY[4];
- uint8_t RESERVED_1[132];
- struct { /* offset: 0x204, array step: 0x8 */
- __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW0S[2];
- uint8_t RESERVED_2[48];
- struct { /* offset: 0x244, array step: 0x8 */
- __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW1S[2];
- uint8_t RESERVED_3[48];
- struct { /* offset: 0x284, array step: 0x8 */
- __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW2S[2];
- uint8_t RESERVED_4[48];
- struct { /* offset: 0x2C4, array step: 0x8 */
- __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
- uint8_t RESERVED_0[4];
- } DATAW3S[2];
-} FMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- FMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FMC_Register_Masks FMC Register Masks
- * @{
- */
-
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK 0x3u
-#define FMC_PFAPR_M0AP_SHIFT 0
-#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK 0xCu
-#define FMC_PFAPR_M1AP_SHIFT 2
-#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK 0x30u
-#define FMC_PFAPR_M2AP_SHIFT 4
-#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK 0xC0u
-#define FMC_PFAPR_M3AP_SHIFT 6
-#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK 0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT 16
-#define FMC_PFAPR_M1PFD_MASK 0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT 17
-#define FMC_PFAPR_M2PFD_MASK 0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT 18
-#define FMC_PFAPR_M3PFD_MASK 0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT 19
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK 0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT 0
-#define FMC_PFB0CR_B0IPE_MASK 0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT 1
-#define FMC_PFB0CR_B0DPE_MASK 0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT 2
-#define FMC_PFB0CR_B0ICE_MASK 0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT 3
-#define FMC_PFB0CR_B0DCE_MASK 0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT 4
-#define FMC_PFB0CR_CRC_MASK 0xE0u
-#define FMC_PFB0CR_CRC_SHIFT 5
-#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK 0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT 17
-#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT 19
-#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT 20
-#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
-#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT 28
-#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* TAGVD Bit Fields */
-#define FMC_TAGVD_valid_MASK 0x1u
-#define FMC_TAGVD_valid_SHIFT 0
-#define FMC_TAGVD_tag_MASK 0x7FFC0u
-#define FMC_TAGVD_tag_SHIFT 6
-#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
-/* DATAW0S Bit Fields */
-#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW0S_data_SHIFT 0
-#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
-/* DATAW1S Bit Fields */
-#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW1S_data_SHIFT 0
-#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
-/* DATAW2S Bit Fields */
-#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW2S_data_SHIFT 0
-#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
-/* DATAW3S Bit Fields */
-#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
-#define FMC_DATAW3S_data_SHIFT 0
-#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
-
-/**
- * @}
- */ /* end of group FMC_Register_Masks */
-
-
-/* FMC - Peripheral instance base addresses */
-/** Peripheral FMC base address */
-#define FMC_BASE (0x4001F000u)
-/** Peripheral FMC base pointer */
-#define FMC ((FMC_Type *)FMC_BASE)
-
-/**
- * @}
- */ /* end of group FMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFL Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
- * @{
- */
-
-/** FTFL - Register Layout Typedef */
-typedef struct {
- __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
- __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
- __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
- __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
- __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
- __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
- __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
- __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
- __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
- __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
- __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
- __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
- __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
- __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
- __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
- __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
- __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
- __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
- __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
- __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
- uint8_t RESERVED_0[2];
- __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
- __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
-} FTFL_Type;
-
-/* ----------------------------------------------------------------------------
- -- FTFL Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFL_Register_Masks FTFL Register Masks
- * @{
- */
-
-/* FSTAT Bit Fields */
-#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFL_FSTAT_MGSTAT0_SHIFT 0
-#define FTFL_FSTAT_FPVIOL_MASK 0x10u
-#define FTFL_FSTAT_FPVIOL_SHIFT 4
-#define FTFL_FSTAT_ACCERR_MASK 0x20u
-#define FTFL_FSTAT_ACCERR_SHIFT 5
-#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFL_FSTAT_RDCOLERR_SHIFT 6
-#define FTFL_FSTAT_CCIF_MASK 0x80u
-#define FTFL_FSTAT_CCIF_SHIFT 7
-/* FCNFG Bit Fields */
-#define FTFL_FCNFG_EEERDY_MASK 0x1u
-#define FTFL_FCNFG_EEERDY_SHIFT 0
-#define FTFL_FCNFG_RAMRDY_MASK 0x2u
-#define FTFL_FCNFG_RAMRDY_SHIFT 1
-#define FTFL_FCNFG_PFLSH_MASK 0x4u
-#define FTFL_FCNFG_PFLSH_SHIFT 2
-#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFL_FCNFG_ERSSUSP_SHIFT 4
-#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFL_FCNFG_ERSAREQ_SHIFT 5
-#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFL_FCNFG_CCIE_MASK 0x80u
-#define FTFL_FCNFG_CCIE_SHIFT 7
-/* FSEC Bit Fields */
-#define FTFL_FSEC_SEC_MASK 0x3u
-#define FTFL_FSEC_SEC_SHIFT 0
-#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
-#define FTFL_FSEC_FSLACC_MASK 0xCu
-#define FTFL_FSEC_FSLACC_SHIFT 2
-#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
-#define FTFL_FSEC_MEEN_MASK 0x30u
-#define FTFL_FSEC_MEEN_SHIFT 4
-#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
-#define FTFL_FSEC_KEYEN_MASK 0xC0u
-#define FTFL_FSEC_KEYEN_SHIFT 6
-#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFL_FOPT_OPT_MASK 0xFFu
-#define FTFL_FOPT_OPT_SHIFT 0
-#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB3_CCOBn_SHIFT 0
-#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB2_CCOBn_SHIFT 0
-#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB1_CCOBn_SHIFT 0
-#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB0_CCOBn_SHIFT 0
-#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB7_CCOBn_SHIFT 0
-#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB6_CCOBn_SHIFT 0
-#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB5_CCOBn_SHIFT 0
-#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB4_CCOBn_SHIFT 0
-#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFL_FCCOBB_CCOBn_SHIFT 0
-#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFL_FCCOBA_CCOBn_SHIFT 0
-#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB9_CCOBn_SHIFT 0
-#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFL_FCCOB8_CCOBn_SHIFT 0
-#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFL_FPROT3_PROT_MASK 0xFFu
-#define FTFL_FPROT3_PROT_SHIFT 0
-#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFL_FPROT2_PROT_MASK 0xFFu
-#define FTFL_FPROT2_PROT_SHIFT 0
-#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFL_FPROT1_PROT_MASK 0xFFu
-#define FTFL_FPROT1_PROT_SHIFT 0
-#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFL_FPROT0_PROT_MASK 0xFFu
-#define FTFL_FPROT0_PROT_SHIFT 0
-#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
-/* FEPROT Bit Fields */
-#define FTFL_FEPROT_EPROT_MASK 0xFFu
-#define FTFL_FEPROT_EPROT_SHIFT 0
-#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define FTFL_FDPROT_DPROT_MASK 0xFFu
-#define FTFL_FDPROT_DPROT_SHIFT 0
-#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
-
-/**
- * @}
- */ /* end of group FTFL_Register_Masks */
-
-
-/* FTFL - Peripheral instance base addresses */
-/** Peripheral FTFL base address */
-#define FTFL_BASE (0x40020000u)
-/** Peripheral FTFL base pointer */
-#define FTFL ((FTFL_Type *)FTFL_BASE)
-
-/**
- * @}
- */ /* end of group FTFL_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
- * @{
- */
-
-/** FTM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
- __IO uint32_t CNT; /**< Counter, offset: 0x4 */
- __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
- struct { /* offset: 0xC, array step: 0x8 */
- __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
- __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
- } CONTROLS[8];
- __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
- __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
- __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
- __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
- __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
- __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
- __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
- __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
- __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
- __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
- __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
- __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
- __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
- __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
- __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
- __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
- __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
- __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
- __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
- __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type;
-
-/* ----------------------------------------------------------------------------
- -- FTM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTM_Register_Masks FTM Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK 0x7u
-#define FTM_SC_PS_SHIFT 0
-#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK 0x18u
-#define FTM_SC_CLKS_SHIFT 3
-#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK 0x20u
-#define FTM_SC_CPWMS_SHIFT 5
-#define FTM_SC_TOIE_MASK 0x40u
-#define FTM_SC_TOIE_SHIFT 6
-#define FTM_SC_TOF_MASK 0x80u
-#define FTM_SC_TOF_SHIFT 7
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK 0xFFFFu
-#define FTM_CNT_COUNT_SHIFT 0
-#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK 0xFFFFu
-#define FTM_MOD_MOD_SHIFT 0
-#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK 0x1u
-#define FTM_CnSC_DMA_SHIFT 0
-#define FTM_CnSC_ELSA_MASK 0x4u
-#define FTM_CnSC_ELSA_SHIFT 2
-#define FTM_CnSC_ELSB_MASK 0x8u
-#define FTM_CnSC_ELSB_SHIFT 3
-#define FTM_CnSC_MSA_MASK 0x10u
-#define FTM_CnSC_MSA_SHIFT 4
-#define FTM_CnSC_MSB_MASK 0x20u
-#define FTM_CnSC_MSB_SHIFT 5
-#define FTM_CnSC_CHIE_MASK 0x40u
-#define FTM_CnSC_CHIE_SHIFT 6
-#define FTM_CnSC_CHF_MASK 0x80u
-#define FTM_CnSC_CHF_SHIFT 7
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK 0xFFFFu
-#define FTM_CnV_VAL_SHIFT 0
-#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK 0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT 0
-#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK 0x1u
-#define FTM_STATUS_CH0F_SHIFT 0
-#define FTM_STATUS_CH1F_MASK 0x2u
-#define FTM_STATUS_CH1F_SHIFT 1
-#define FTM_STATUS_CH2F_MASK 0x4u
-#define FTM_STATUS_CH2F_SHIFT 2
-#define FTM_STATUS_CH3F_MASK 0x8u
-#define FTM_STATUS_CH3F_SHIFT 3
-#define FTM_STATUS_CH4F_MASK 0x10u
-#define FTM_STATUS_CH4F_SHIFT 4
-#define FTM_STATUS_CH5F_MASK 0x20u
-#define FTM_STATUS_CH5F_SHIFT 5
-#define FTM_STATUS_CH6F_MASK 0x40u
-#define FTM_STATUS_CH6F_SHIFT 6
-#define FTM_STATUS_CH7F_MASK 0x80u
-#define FTM_STATUS_CH7F_SHIFT 7
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK 0x1u
-#define FTM_MODE_FTMEN_SHIFT 0
-#define FTM_MODE_INIT_MASK 0x2u
-#define FTM_MODE_INIT_SHIFT 1
-#define FTM_MODE_WPDIS_MASK 0x4u
-#define FTM_MODE_WPDIS_SHIFT 2
-#define FTM_MODE_PWMSYNC_MASK 0x8u
-#define FTM_MODE_PWMSYNC_SHIFT 3
-#define FTM_MODE_CAPTEST_MASK 0x10u
-#define FTM_MODE_CAPTEST_SHIFT 4
-#define FTM_MODE_FAULTM_MASK 0x60u
-#define FTM_MODE_FAULTM_SHIFT 5
-#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK 0x80u
-#define FTM_MODE_FAULTIE_SHIFT 7
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK 0x1u
-#define FTM_SYNC_CNTMIN_SHIFT 0
-#define FTM_SYNC_CNTMAX_MASK 0x2u
-#define FTM_SYNC_CNTMAX_SHIFT 1
-#define FTM_SYNC_REINIT_MASK 0x4u
-#define FTM_SYNC_REINIT_SHIFT 2
-#define FTM_SYNC_SYNCHOM_MASK 0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT 3
-#define FTM_SYNC_TRIG0_MASK 0x10u
-#define FTM_SYNC_TRIG0_SHIFT 4
-#define FTM_SYNC_TRIG1_MASK 0x20u
-#define FTM_SYNC_TRIG1_SHIFT 5
-#define FTM_SYNC_TRIG2_MASK 0x40u
-#define FTM_SYNC_TRIG2_SHIFT 6
-#define FTM_SYNC_SWSYNC_MASK 0x80u
-#define FTM_SYNC_SWSYNC_SHIFT 7
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK 0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT 0
-#define FTM_OUTINIT_CH1OI_MASK 0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT 1
-#define FTM_OUTINIT_CH2OI_MASK 0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT 2
-#define FTM_OUTINIT_CH3OI_MASK 0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT 3
-#define FTM_OUTINIT_CH4OI_MASK 0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT 4
-#define FTM_OUTINIT_CH5OI_MASK 0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT 5
-#define FTM_OUTINIT_CH6OI_MASK 0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT 6
-#define FTM_OUTINIT_CH7OI_MASK 0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT 7
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK 0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT 0
-#define FTM_OUTMASK_CH1OM_MASK 0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT 1
-#define FTM_OUTMASK_CH2OM_MASK 0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT 2
-#define FTM_OUTMASK_CH3OM_MASK 0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT 3
-#define FTM_OUTMASK_CH4OM_MASK 0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT 4
-#define FTM_OUTMASK_CH5OM_MASK 0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT 5
-#define FTM_OUTMASK_CH6OM_MASK 0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT 6
-#define FTM_OUTMASK_CH7OM_MASK 0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT 7
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK 0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT 0
-#define FTM_COMBINE_COMP0_MASK 0x2u
-#define FTM_COMBINE_COMP0_SHIFT 1
-#define FTM_COMBINE_DECAPEN0_MASK 0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT 2
-#define FTM_COMBINE_DECAP0_MASK 0x8u
-#define FTM_COMBINE_DECAP0_SHIFT 3
-#define FTM_COMBINE_DTEN0_MASK 0x10u
-#define FTM_COMBINE_DTEN0_SHIFT 4
-#define FTM_COMBINE_SYNCEN0_MASK 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT 5
-#define FTM_COMBINE_FAULTEN0_MASK 0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT 6
-#define FTM_COMBINE_COMBINE1_MASK 0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT 8
-#define FTM_COMBINE_COMP1_MASK 0x200u
-#define FTM_COMBINE_COMP1_SHIFT 9
-#define FTM_COMBINE_DECAPEN1_MASK 0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT 10
-#define FTM_COMBINE_DECAP1_MASK 0x800u
-#define FTM_COMBINE_DECAP1_SHIFT 11
-#define FTM_COMBINE_DTEN1_MASK 0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT 12
-#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT 13
-#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT 14
-#define FTM_COMBINE_COMBINE2_MASK 0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT 16
-#define FTM_COMBINE_COMP2_MASK 0x20000u
-#define FTM_COMBINE_COMP2_SHIFT 17
-#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT 18
-#define FTM_COMBINE_DECAP2_MASK 0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT 19
-#define FTM_COMBINE_DTEN2_MASK 0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT 20
-#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT 21
-#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT 22
-#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT 24
-#define FTM_COMBINE_COMP3_MASK 0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT 25
-#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT 26
-#define FTM_COMBINE_DECAP3_MASK 0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT 27
-#define FTM_COMBINE_DTEN3_MASK 0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT 28
-#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT 29
-#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT 30
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT 0
-#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK 0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT 6
-#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
-#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
-#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
-#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
-#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
-#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
-#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
-#define FTM_EXTTRIG_TRIGF_MASK 0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT 7
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK 0x1u
-#define FTM_POL_POL0_SHIFT 0
-#define FTM_POL_POL1_MASK 0x2u
-#define FTM_POL_POL1_SHIFT 1
-#define FTM_POL_POL2_MASK 0x4u
-#define FTM_POL_POL2_SHIFT 2
-#define FTM_POL_POL3_MASK 0x8u
-#define FTM_POL_POL3_SHIFT 3
-#define FTM_POL_POL4_MASK 0x10u
-#define FTM_POL_POL4_SHIFT 4
-#define FTM_POL_POL5_MASK 0x20u
-#define FTM_POL_POL5_SHIFT 5
-#define FTM_POL_POL6_MASK 0x40u
-#define FTM_POL_POL6_SHIFT 6
-#define FTM_POL_POL7_MASK 0x80u
-#define FTM_POL_POL7_SHIFT 7
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK 0x1u
-#define FTM_FMS_FAULTF0_SHIFT 0
-#define FTM_FMS_FAULTF1_MASK 0x2u
-#define FTM_FMS_FAULTF1_SHIFT 1
-#define FTM_FMS_FAULTF2_MASK 0x4u
-#define FTM_FMS_FAULTF2_SHIFT 2
-#define FTM_FMS_FAULTF3_MASK 0x8u
-#define FTM_FMS_FAULTF3_SHIFT 3
-#define FTM_FMS_FAULTIN_MASK 0x20u
-#define FTM_FMS_FAULTIN_SHIFT 5
-#define FTM_FMS_WPEN_MASK 0x40u
-#define FTM_FMS_WPEN_SHIFT 6
-#define FTM_FMS_FAULTF_MASK 0x80u
-#define FTM_FMS_FAULTF_SHIFT 7
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK 0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT 0
-#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK 0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT 4
-#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK 0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT 8
-#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK 0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT 12
-#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
-#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
-#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
-#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
-#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
-#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
-#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
-#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
-#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT 8
-#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK 0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT 0
-#define FTM_QDCTRL_TOFDIR_MASK 0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT 1
-#define FTM_QDCTRL_QUADIR_MASK 0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT 2
-#define FTM_QDCTRL_QUADMODE_MASK 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT 3
-#define FTM_QDCTRL_PHBPOL_MASK 0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT 4
-#define FTM_QDCTRL_PHAPOL_MASK 0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT 5
-#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
-#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK 0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT 0
-#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK 0xC0u
-#define FTM_CONF_BDMMODE_SHIFT 6
-#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK 0x200u
-#define FTM_CONF_GTBEEN_SHIFT 9
-#define FTM_CONF_GTBEOUT_MASK 0x400u
-#define FTM_CONF_GTBEOUT_SHIFT 10
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK 0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT 0
-#define FTM_FLTPOL_FLT1POL_MASK 0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT 1
-#define FTM_FLTPOL_FLT2POL_MASK 0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT 2
-#define FTM_FLTPOL_FLT3POL_MASK 0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT 3
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
-#define FTM_SYNCONF_CNTINC_MASK 0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT 2
-#define FTM_SYNCONF_INVC_MASK 0x10u
-#define FTM_SYNCONF_INVC_SHIFT 4
-#define FTM_SYNCONF_SWOC_MASK 0x20u
-#define FTM_SYNCONF_SWOC_SHIFT 5
-#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT 7
-#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
-#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT 9
-#define FTM_SYNCONF_SWOM_MASK 0x400u
-#define FTM_SYNCONF_SWOM_SHIFT 10
-#define FTM_SYNCONF_SWINVC_MASK 0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT 11
-#define FTM_SYNCONF_SWSOC_MASK 0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT 12
-#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
-#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT 17
-#define FTM_SYNCONF_HWOM_MASK 0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT 18
-#define FTM_SYNCONF_HWINVC_MASK 0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT 19
-#define FTM_SYNCONF_HWSOC_MASK 0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT 20
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK 0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT 0
-#define FTM_INVCTRL_INV1EN_MASK 0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT 1
-#define FTM_INVCTRL_INV2EN_MASK 0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT 2
-#define FTM_INVCTRL_INV3EN_MASK 0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT 3
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK 0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT 0
-#define FTM_SWOCTRL_CH1OC_MASK 0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT 1
-#define FTM_SWOCTRL_CH2OC_MASK 0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT 2
-#define FTM_SWOCTRL_CH3OC_MASK 0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT 3
-#define FTM_SWOCTRL_CH4OC_MASK 0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT 4
-#define FTM_SWOCTRL_CH5OC_MASK 0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT 5
-#define FTM_SWOCTRL_CH6OC_MASK 0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT 6
-#define FTM_SWOCTRL_CH7OC_MASK 0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT 7
-#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT 8
-#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT 9
-#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT 10
-#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT 11
-#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT 12
-#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT 13
-#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT 14
-#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT 15
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT 0
-#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT 1
-#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT 2
-#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT 3
-#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT 4
-#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT 5
-#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT 6
-#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT 7
-#define FTM_PWMLOAD_LDOK_MASK 0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT 9
-
-/**
- * @}
- */ /* end of group FTM_Register_Masks */
-
-
-/* FTM - Peripheral instance base addresses */
-/** Peripheral FTM0 base address */
-#define FTM0_BASE (0x40038000u)
-/** Peripheral FTM0 base pointer */
-#define FTM0 ((FTM_Type *)FTM0_BASE)
-/** Peripheral FTM1 base address */
-#define FTM1_BASE (0x40039000u)
-/** Peripheral FTM1 base pointer */
-#define FTM1 ((FTM_Type *)FTM1_BASE)
-
-/**
- * @}
- */ /* end of group FTM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type;
-
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-/** Peripheral PTC base address */
-#define PTC_BASE (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC ((GPIO_Type *)PTC_BASE)
-/** Peripheral PTD base address */
-#define PTD_BASE (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD ((GPIO_Type *)PTD_BASE)
-/** Peripheral PTE base address */
-#define PTE_BASE (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE ((GPIO_Type *)PTE_BASE)
-
-/**
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
- __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
- __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
- __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
- __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
- __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
- __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
- __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
- __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
- __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
- __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
- __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
- __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2C Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0x1Fu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-
-/**
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40066000u)
-#define I2C1_BASE (0x40067000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-#define I2C1 ((I2C_Type *)I2C1_BASE)
-/**
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2S Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
- * @{
- */
-
-/** I2S - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
- __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
- __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
- __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
- __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
- __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
- uint8_t RESERVED_0[8];
- __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[24];
- __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_2[24];
- __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
- uint8_t RESERVED_3[28];
- __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
- __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
- __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
- __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
- __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
- __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
- uint8_t RESERVED_4[8];
- __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
- uint8_t RESERVED_5[24];
- __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_6[24];
- __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
- uint8_t RESERVED_7[28];
- __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
- __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
-} I2S_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2S Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2S_Register_Masks I2S Register Masks
- * @{
- */
-
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK 0x1u
-#define I2S_TCSR_FRDE_SHIFT 0
-#define I2S_TCSR_FWDE_MASK 0x2u
-#define I2S_TCSR_FWDE_SHIFT 1
-#define I2S_TCSR_FRIE_MASK 0x100u
-#define I2S_TCSR_FRIE_SHIFT 8
-#define I2S_TCSR_FWIE_MASK 0x200u
-#define I2S_TCSR_FWIE_SHIFT 9
-#define I2S_TCSR_FEIE_MASK 0x400u
-#define I2S_TCSR_FEIE_SHIFT 10
-#define I2S_TCSR_SEIE_MASK 0x800u
-#define I2S_TCSR_SEIE_SHIFT 11
-#define I2S_TCSR_WSIE_MASK 0x1000u
-#define I2S_TCSR_WSIE_SHIFT 12
-#define I2S_TCSR_FRF_MASK 0x10000u
-#define I2S_TCSR_FRF_SHIFT 16
-#define I2S_TCSR_FWF_MASK 0x20000u
-#define I2S_TCSR_FWF_SHIFT 17
-#define I2S_TCSR_FEF_MASK 0x40000u
-#define I2S_TCSR_FEF_SHIFT 18
-#define I2S_TCSR_SEF_MASK 0x80000u
-#define I2S_TCSR_SEF_SHIFT 19
-#define I2S_TCSR_WSF_MASK 0x100000u
-#define I2S_TCSR_WSF_SHIFT 20
-#define I2S_TCSR_SR_MASK 0x1000000u
-#define I2S_TCSR_SR_SHIFT 24
-#define I2S_TCSR_FR_MASK 0x2000000u
-#define I2S_TCSR_FR_SHIFT 25
-#define I2S_TCSR_BCE_MASK 0x10000000u
-#define I2S_TCSR_BCE_SHIFT 28
-#define I2S_TCSR_DBGE_MASK 0x20000000u
-#define I2S_TCSR_DBGE_SHIFT 29
-#define I2S_TCSR_STOPE_MASK 0x40000000u
-#define I2S_TCSR_STOPE_SHIFT 30
-#define I2S_TCSR_TE_MASK 0x80000000u
-#define I2S_TCSR_TE_SHIFT 31
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK 0x7u
-#define I2S_TCR1_TFW_SHIFT 0
-#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK 0xFFu
-#define I2S_TCR2_DIV_SHIFT 0
-#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK 0x1000000u
-#define I2S_TCR2_BCD_SHIFT 24
-#define I2S_TCR2_BCP_MASK 0x2000000u
-#define I2S_TCR2_BCP_SHIFT 25
-#define I2S_TCR2_MSEL_MASK 0xC000000u
-#define I2S_TCR2_MSEL_SHIFT 26
-#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK 0x10000000u
-#define I2S_TCR2_BCI_SHIFT 28
-#define I2S_TCR2_BCS_MASK 0x20000000u
-#define I2S_TCR2_BCS_SHIFT 29
-#define I2S_TCR2_SYNC_MASK 0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT 30
-#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK 0x1Fu
-#define I2S_TCR3_WDFL_SHIFT 0
-#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK 0x30000u
-#define I2S_TCR3_TCE_SHIFT 16
-#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK 0x1u
-#define I2S_TCR4_FSD_SHIFT 0
-#define I2S_TCR4_FSP_MASK 0x2u
-#define I2S_TCR4_FSP_SHIFT 1
-#define I2S_TCR4_FSE_MASK 0x8u
-#define I2S_TCR4_FSE_SHIFT 3
-#define I2S_TCR4_MF_MASK 0x10u
-#define I2S_TCR4_MF_SHIFT 4
-#define I2S_TCR4_SYWD_MASK 0x1F00u
-#define I2S_TCR4_SYWD_SHIFT 8
-#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK 0x1F0000u
-#define I2S_TCR4_FRSZ_SHIFT 16
-#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK 0x1F00u
-#define I2S_TCR5_FBT_SHIFT 8
-#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK 0x1F0000u
-#define I2S_TCR5_W0W_SHIFT 16
-#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK 0x1F000000u
-#define I2S_TCR5_WNW_SHIFT 24
-#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT 0
-#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK 0xFu
-#define I2S_TFR_RFP_SHIFT 0
-#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK 0xF0000u
-#define I2S_TFR_WFP_SHIFT 16
-#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
-#define I2S_TMR_TWM_SHIFT 0
-#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK 0x1u
-#define I2S_RCSR_FRDE_SHIFT 0
-#define I2S_RCSR_FWDE_MASK 0x2u
-#define I2S_RCSR_FWDE_SHIFT 1
-#define I2S_RCSR_FRIE_MASK 0x100u
-#define I2S_RCSR_FRIE_SHIFT 8
-#define I2S_RCSR_FWIE_MASK 0x200u
-#define I2S_RCSR_FWIE_SHIFT 9
-#define I2S_RCSR_FEIE_MASK 0x400u
-#define I2S_RCSR_FEIE_SHIFT 10
-#define I2S_RCSR_SEIE_MASK 0x800u
-#define I2S_RCSR_SEIE_SHIFT 11
-#define I2S_RCSR_WSIE_MASK 0x1000u
-#define I2S_RCSR_WSIE_SHIFT 12
-#define I2S_RCSR_FRF_MASK 0x10000u
-#define I2S_RCSR_FRF_SHIFT 16
-#define I2S_RCSR_FWF_MASK 0x20000u
-#define I2S_RCSR_FWF_SHIFT 17
-#define I2S_RCSR_FEF_MASK 0x40000u
-#define I2S_RCSR_FEF_SHIFT 18
-#define I2S_RCSR_SEF_MASK 0x80000u
-#define I2S_RCSR_SEF_SHIFT 19
-#define I2S_RCSR_WSF_MASK 0x100000u
-#define I2S_RCSR_WSF_SHIFT 20
-#define I2S_RCSR_SR_MASK 0x1000000u
-#define I2S_RCSR_SR_SHIFT 24
-#define I2S_RCSR_FR_MASK 0x2000000u
-#define I2S_RCSR_FR_SHIFT 25
-#define I2S_RCSR_BCE_MASK 0x10000000u
-#define I2S_RCSR_BCE_SHIFT 28
-#define I2S_RCSR_DBGE_MASK 0x20000000u
-#define I2S_RCSR_DBGE_SHIFT 29
-#define I2S_RCSR_STOPE_MASK 0x40000000u
-#define I2S_RCSR_STOPE_SHIFT 30
-#define I2S_RCSR_RE_MASK 0x80000000u
-#define I2S_RCSR_RE_SHIFT 31
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK 0x7u
-#define I2S_RCR1_RFW_SHIFT 0
-#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK 0xFFu
-#define I2S_RCR2_DIV_SHIFT 0
-#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK 0x1000000u
-#define I2S_RCR2_BCD_SHIFT 24
-#define I2S_RCR2_BCP_MASK 0x2000000u
-#define I2S_RCR2_BCP_SHIFT 25
-#define I2S_RCR2_MSEL_MASK 0xC000000u
-#define I2S_RCR2_MSEL_SHIFT 26
-#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK 0x10000000u
-#define I2S_RCR2_BCI_SHIFT 28
-#define I2S_RCR2_BCS_MASK 0x20000000u
-#define I2S_RCR2_BCS_SHIFT 29
-#define I2S_RCR2_SYNC_MASK 0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT 30
-#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK 0x1Fu
-#define I2S_RCR3_WDFL_SHIFT 0
-#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK 0x30000u
-#define I2S_RCR3_RCE_SHIFT 16
-#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK 0x1u
-#define I2S_RCR4_FSD_SHIFT 0
-#define I2S_RCR4_FSP_MASK 0x2u
-#define I2S_RCR4_FSP_SHIFT 1
-#define I2S_RCR4_FSE_MASK 0x8u
-#define I2S_RCR4_FSE_SHIFT 3
-#define I2S_RCR4_MF_MASK 0x10u
-#define I2S_RCR4_MF_SHIFT 4
-#define I2S_RCR4_SYWD_MASK 0x1F00u
-#define I2S_RCR4_SYWD_SHIFT 8
-#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK 0x1F0000u
-#define I2S_RCR4_FRSZ_SHIFT 16
-#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK 0x1F00u
-#define I2S_RCR5_FBT_SHIFT 8
-#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK 0x1F0000u
-#define I2S_RCR5_W0W_SHIFT 16
-#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK 0x1F000000u
-#define I2S_RCR5_WNW_SHIFT 24
-#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT 0
-#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK 0xFu
-#define I2S_RFR_RFP_SHIFT 0
-#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK 0xF0000u
-#define I2S_RFR_WFP_SHIFT 16
-#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
-#define I2S_RMR_RWM_SHIFT 0
-#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK 0x3000000u
-#define I2S_MCR_MICS_SHIFT 24
-#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK 0x40000000u
-#define I2S_MCR_MOE_SHIFT 30
-#define I2S_MCR_DUF_MASK 0x80000000u
-#define I2S_MCR_DUF_SHIFT 31
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK 0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT 0
-#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK 0xFF000u
-#define I2S_MDR_FRACT_SHIFT 12
-#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
-
-/**
- * @}
- */ /* end of group I2S_Register_Masks */
-
-
-/* I2S - Peripheral instance base addresses */
-/** Peripheral I2S0 base address */
-#define I2S0_BASE (0x4002F000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0 ((I2S_Type *)I2S0_BASE)
-
-/**
- * @}
- */ /* end of group I2S_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
- * @{
- */
-
-/** LLWU - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
- __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
- __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
- __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
- __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
- __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
- __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
- __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
- __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
- __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
- __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
-} LLWU_Type;
-
-/* ----------------------------------------------------------------------------
- -- LLWU Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Register_Masks LLWU Register Masks
- * @{
- */
-
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-/* RST Bit Fields */
-#define LLWU_RST_RSTFILT_MASK 0x1u
-#define LLWU_RST_RSTFILT_SHIFT 0
-#define LLWU_RST_LLRSTE_MASK 0x2u
-#define LLWU_RST_LLRSTE_SHIFT 1
-
-/**
- * @}
- */ /* end of group LLWU_Register_Masks */
-
-
-/* LLWU - Peripheral instance base addresses */
-/** Peripheral LLWU base address */
-#define LLWU_BASE (0x4007C000u)
-/** Peripheral LLWU base pointer */
-#define LLWU ((LLWU_Type *)LLWU_BASE)
-
-/**
- * @}
- */ /* end of group LLWU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
- * @{
- */
-
-/** LPTMR - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
- __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
- __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
- __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
- * @{
- */
-
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-
-/**
- * @}
- */ /* end of group LPTMR_Register_Masks */
-
-
-/* LPTMR - Peripheral instance base addresses */
-/** Peripheral LPTMR0 base address */
-#define LPTMR0_BASE (0x40040000u)
-/** Peripheral LPTMR0 base pointer */
-#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-
-/**
- * @}
- */ /* end of group LPTMR_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
- * @{
- */
-
-/** MCG - Register Layout Typedef */
-typedef struct {
- __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
- __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
- __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
- __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
- __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
- __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
- __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
- uint8_t RESERVED_0[1];
- __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
- uint8_t RESERVED_1[1];
- __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
- __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
- __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
- __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
-} MCG_Type;
-
-/* ----------------------------------------------------------------------------
- -- MCG Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Register_Masks MCG Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_EREFS0_MASK 0x4u
-#define MCG_C2_EREFS0_SHIFT 2
-#define MCG_C2_HGO0_MASK 0x8u
-#define MCG_C2_HGO0_SHIFT 3
-#define MCG_C2_RANGE0_MASK 0x30u
-#define MCG_C2_RANGE0_SHIFT 4
-#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK 0x1Fu
-#define MCG_C5_PRDIV0_SHIFT 0
-#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK 0x20u
-#define MCG_C5_PLLSTEN0_SHIFT 5
-#define MCG_C5_PLLCLKEN0_MASK 0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT 6
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK 0x1Fu
-#define MCG_C6_VDIV0_SHIFT 0
-#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK 0x20u
-#define MCG_C6_CME0_SHIFT 5
-#define MCG_C6_PLLS_MASK 0x40u
-#define MCG_C6_PLLS_SHIFT 6
-#define MCG_C6_LOLIE0_MASK 0x80u
-#define MCG_C6_LOLIE0_SHIFT 7
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_PLLST_MASK 0x20u
-#define MCG_S_PLLST_SHIFT 5
-#define MCG_S_LOCK0_MASK 0x40u
-#define MCG_S_LOCK0_SHIFT 6
-#define MCG_S_LOLS0_MASK 0x80u
-#define MCG_S_LOLS0_SHIFT 7
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK 0x1u
-#define MCG_C7_OSCSEL_SHIFT 0
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK 0x1u
-#define MCG_C8_LOCS1_SHIFT 0
-#define MCG_C8_CME1_MASK 0x20u
-#define MCG_C8_CME1_SHIFT 5
-#define MCG_C8_LOLRE_MASK 0x40u
-#define MCG_C8_LOLRE_SHIFT 6
-#define MCG_C8_LOCRE1_MASK 0x80u
-#define MCG_C8_LOCRE1_SHIFT 7
-
-/**
- * @}
- */ /* end of group MCG_Register_Masks */
-
-
-/* MCG - Peripheral instance base addresses */
-/** Peripheral MCG base address */
-#define MCG_BASE (0x40064000u)
-/** Peripheral MCG base pointer */
-#define MCG ((MCG_Type *)MCG_BASE)
-
-/**
- * @}
- */ /* end of group MCG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
- * @{
- */
-
-/** NV - Register Layout Typedef */
-typedef struct {
- __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
- __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
- __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
- __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
- __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
- __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
- __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
- __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
- __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
- __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
- __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
- __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
- __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
- __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
- __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
- __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
-} NV_Type;
-
-/* ----------------------------------------------------------------------------
- -- NV Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Register_Masks NV Register Masks
- * @{
- */
-
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK 0x1u
-#define NV_FOPT_LPBOOT_SHIFT 0
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-/* FEPROT Bit Fields */
-#define NV_FEPROT_EPROT_MASK 0xFFu
-#define NV_FEPROT_EPROT_SHIFT 0
-#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define NV_FDPROT_DPROT_MASK 0xFFu
-#define NV_FDPROT_DPROT_SHIFT 0
-#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
-
-/**
- * @}
- */ /* end of group NV_Register_Masks */
-
-
-/* NV - Peripheral instance base addresses */
-/** Peripheral FTFL_FlashConfig base address */
-#define FTFL_FlashConfig_BASE (0x400u)
-/** Peripheral FTFL_FlashConfig base pointer */
-#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
-
-/**
- * @}
- */ /* end of group NV_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
- * @{
- */
-
-/** OSC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
-} OSC_Type;
-
-/* ----------------------------------------------------------------------------
- -- OSC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Register_Masks OSC Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-
-/**
- * @}
- */ /* end of group OSC_Register_Masks */
-
-
-/* OSC - Peripheral instance base addresses */
-/** Peripheral OSC0 base address */
-#define OSC0_BASE (0x40065000u)
-/** Peripheral OSC0 base pointer */
-#define OSC0 ((OSC_Type *)OSC0_BASE)
-
-/**
- * @}
- */ /* end of group OSC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PDB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
- * @{
- */
-
-/** PDB - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
- __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
- __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
- __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
- struct { /* offset: 0x10, array step: 0x10 */
- __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
- __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
- __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
- } CH[1];
- uint8_t RESERVED_0[368];
- __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
- __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
-} PDB_Type;
-
-/* ----------------------------------------------------------------------------
- -- PDB Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PDB_Register_Masks PDB Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK 0x1u
-#define PDB_SC_LDOK_SHIFT 0
-#define PDB_SC_CONT_MASK 0x2u
-#define PDB_SC_CONT_SHIFT 1
-#define PDB_SC_MULT_MASK 0xCu
-#define PDB_SC_MULT_SHIFT 2
-#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK 0x20u
-#define PDB_SC_PDBIE_SHIFT 5
-#define PDB_SC_PDBIF_MASK 0x40u
-#define PDB_SC_PDBIF_SHIFT 6
-#define PDB_SC_PDBEN_MASK 0x80u
-#define PDB_SC_PDBEN_SHIFT 7
-#define PDB_SC_TRGSEL_MASK 0xF00u
-#define PDB_SC_TRGSEL_SHIFT 8
-#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK 0x7000u
-#define PDB_SC_PRESCALER_SHIFT 12
-#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK 0x8000u
-#define PDB_SC_DMAEN_SHIFT 15
-#define PDB_SC_SWTRIG_MASK 0x10000u
-#define PDB_SC_SWTRIG_SHIFT 16
-#define PDB_SC_PDBEIE_MASK 0x20000u
-#define PDB_SC_PDBEIE_SHIFT 17
-#define PDB_SC_LDMOD_MASK 0xC0000u
-#define PDB_SC_LDMOD_SHIFT 18
-#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK 0xFFFFu
-#define PDB_MOD_MOD_SHIFT 0
-#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK 0xFFFFu
-#define PDB_CNT_CNT_SHIFT 0
-#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK 0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT 0
-#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK 0xFFu
-#define PDB_C1_EN_SHIFT 0
-#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK 0xFF00u
-#define PDB_C1_TOS_SHIFT 8
-#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK 0xFF0000u
-#define PDB_C1_BB_SHIFT 16
-#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK 0xFFu
-#define PDB_S_ERR_SHIFT 0
-#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK 0xFF0000u
-#define PDB_S_CF_SHIFT 16
-#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK 0xFFFFu
-#define PDB_DLY_DLY_SHIFT 0
-#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK 0xFFu
-#define PDB_POEN_POEN_SHIFT 0
-#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK 0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT 0
-#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT 16
-#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
-
-/**
- * @}
- */ /* end of group PDB_Register_Masks */
-
-
-/* PDB - Peripheral instance base addresses */
-/** Peripheral PDB0 base address */
-#define PDB0_BASE (0x40036000u)
-/** Peripheral PDB0 base pointer */
-#define PDB0 ((PDB_Type *)PDB0_BASE)
-
-/**
- * @}
- */ /* end of group PDB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
- * @{
- */
-
-/** PIT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
- uint8_t RESERVED_0[252];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
- __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
- __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
- __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
- } CHANNEL[4];
-} PIT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-
-/**
- * @}
- */ /* end of group PIT_Register_Masks */
-
-
-/* PIT - Peripheral instance base addresses */
-/** Peripheral PIT base address */
-#define PIT_BASE (0x40037000u)
-/** Peripheral PIT base pointer */
-#define PIT ((PIT_Type *)PIT_BASE)
-
-/**
- * @}
- */ /* end of group PIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
- * @{
- */
-
-/** PMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
- __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
- __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
-} PMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- PMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Register_Masks PMC Register Masks
- * @{
- */
-
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-
-/**
- * @}
- */ /* end of group PMC_Register_Masks */
-
-
-/* PMC - Peripheral instance base addresses */
-/** Peripheral PMC base address */
-#define PMC_BASE (0x4007D000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-
-/**
- * @}
- */ /* end of group PMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
- * @{
- */
-
-/** PORT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
- __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
- __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
- uint8_t RESERVED_0[24];
- __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
- uint8_t RESERVED_1[28];
- __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
- __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
- __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PORT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Register_Masks PORT Register Masks
- * @{
- */
-
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_ODE_MASK 0x20u
-#define PORT_PCR_ODE_SHIFT 5
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK 0x8000u
-#define PORT_PCR_LK_SHIFT 15
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT 0
-#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK 0x1u
-#define PORT_DFCR_CS_SHIFT 0
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK 0x1Fu
-#define PORT_DFWR_FILT_SHIFT 0
-#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
-
-/**
- * @}
- */ /* end of group PORT_Register_Masks */
-
-
-/* PORT - Peripheral instance base addresses */
-/** Peripheral PORTA base address */
-#define PORTA_BASE (0x40049000u)
-/** Peripheral PORTA base pointer */
-#define PORTA ((PORT_Type *)PORTA_BASE)
-/** Peripheral PORTB base address */
-#define PORTB_BASE (0x4004A000u)
-/** Peripheral PORTB base pointer */
-#define PORTB ((PORT_Type *)PORTB_BASE)
-/** Peripheral PORTC base address */
-#define PORTC_BASE (0x4004B000u)
-/** Peripheral PORTC base pointer */
-#define PORTC ((PORT_Type *)PORTC_BASE)
-/** Peripheral PORTD base address */
-#define PORTD_BASE (0x4004C000u)
-/** Peripheral PORTD base pointer */
-#define PORTD ((PORT_Type *)PORTD_BASE)
-/** Peripheral PORTE base address */
-#define PORTE_BASE (0x4004D000u)
-/** Peripheral PORTE base pointer */
-#define PORTE ((PORT_Type *)PORTE_BASE)
-
-/**
- * @}
- */ /* end of group PORT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
- * @{
- */
-
-/** RCM - Register Layout Typedef */
-typedef struct {
- __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
- __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
- uint8_t RESERVED_0[2];
- __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
- __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
- uint8_t RESERVED_1[1];
- __I uint8_t MR; /**< Mode Register, offset: 0x7 */
-} RCM_Type;
-
-/* ----------------------------------------------------------------------------
- -- RCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Register_Masks RCM Register Masks
- * @{
- */
-
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOL_MASK 0x8u
-#define RCM_SRS0_LOL_SHIFT 3
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK 0x1u
-#define RCM_SRS1_JTAG_SHIFT 0
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_EZPT_MASK 0x10u
-#define RCM_SRS1_EZPT_SHIFT 4
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK 0x2u
-#define RCM_MR_EZP_MS_SHIFT 1
-
-/**
- * @}
- */ /* end of group RCM_Register_Masks */
-
-
-/* RCM - Peripheral instance base addresses */
-/** Peripheral RCM base address */
-#define RCM_BASE (0x4007F000u)
-/** Peripheral RCM base pointer */
-#define RCM ((RCM_Type *)RCM_BASE)
-
-/**
- * @}
- */ /* end of group RCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
- * @{
- */
-
-/** RFSYS - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type;
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK 0xFFu
-#define RFSYS_REG_LL_SHIFT 0
-#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK 0xFF00u
-#define RFSYS_REG_LH_SHIFT 8
-#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK 0xFF0000u
-#define RFSYS_REG_HL_SHIFT 16
-#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK 0xFF000000u
-#define RFSYS_REG_HH_SHIFT 24
-#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
-
-/**
- * @}
- */ /* end of group RFSYS_Register_Masks */
-
-
-/* RFSYS - Peripheral instance base addresses */
-/** Peripheral RFSYS base address */
-#define RFSYS_BASE (0x40041000u)
-/** Peripheral RFSYS base pointer */
-#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
-
-/**
- * @}
- */ /* end of group RFSYS_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
- * @{
- */
-
-/** RFVBAT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type;
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK 0xFFu
-#define RFVBAT_REG_LL_SHIFT 0
-#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK 0xFF00u
-#define RFVBAT_REG_LH_SHIFT 8
-#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK 0xFF0000u
-#define RFVBAT_REG_HL_SHIFT 16
-#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK 0xFF000000u
-#define RFVBAT_REG_HH_SHIFT 24
-#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
-
-/**
- * @}
- */ /* end of group RFVBAT_Register_Masks */
-
-
-/* RFVBAT - Peripheral instance base addresses */
-/** Peripheral RFVBAT base address */
-#define RFVBAT_BASE (0x4003E000u)
-/** Peripheral RFVBAT base pointer */
-#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
-
-/**
- * @}
- */ /* end of group RFVBAT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
- __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
- __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
- __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
- __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
- __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
- __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
- __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
- uint8_t RESERVED_0[2016];
- __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
- __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type;
-
-/* ----------------------------------------------------------------------------
- -- RTC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK 0x1u
-#define RTC_WAR_TSRW_SHIFT 0
-#define RTC_WAR_TPRW_MASK 0x2u
-#define RTC_WAR_TPRW_SHIFT 1
-#define RTC_WAR_TARW_MASK 0x4u
-#define RTC_WAR_TARW_SHIFT 2
-#define RTC_WAR_TCRW_MASK 0x8u
-#define RTC_WAR_TCRW_SHIFT 3
-#define RTC_WAR_CRW_MASK 0x10u
-#define RTC_WAR_CRW_SHIFT 4
-#define RTC_WAR_SRW_MASK 0x20u
-#define RTC_WAR_SRW_SHIFT 5
-#define RTC_WAR_LRW_MASK 0x40u
-#define RTC_WAR_LRW_SHIFT 6
-#define RTC_WAR_IERW_MASK 0x80u
-#define RTC_WAR_IERW_SHIFT 7
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK 0x1u
-#define RTC_RAR_TSRR_SHIFT 0
-#define RTC_RAR_TPRR_MASK 0x2u
-#define RTC_RAR_TPRR_SHIFT 1
-#define RTC_RAR_TARR_MASK 0x4u
-#define RTC_RAR_TARR_SHIFT 2
-#define RTC_RAR_TCRR_MASK 0x8u
-#define RTC_RAR_TCRR_SHIFT 3
-#define RTC_RAR_CRR_MASK 0x10u
-#define RTC_RAR_CRR_SHIFT 4
-#define RTC_RAR_SRR_MASK 0x20u
-#define RTC_RAR_SRR_SHIFT 5
-#define RTC_RAR_LRR_MASK 0x40u
-#define RTC_RAR_LRR_SHIFT 6
-#define RTC_RAR_IERR_MASK 0x80u
-#define RTC_RAR_IERR_SHIFT 7
-
-/**
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4003D000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-
-/**
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
- * @{
- */
-
-/** SIM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
- __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
- uint8_t RESERVED_0[4092];
- __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
- __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
- uint8_t RESERVED_2[4];
- __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
- uint8_t RESERVED_3[8];
- __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
- __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
- __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
- __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
- __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
- __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
- __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
- __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
- __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
- __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
- __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
- __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
- __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
- __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
- __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
- __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type;
-
-/* ----------------------------------------------------------------------------
- -- SIM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Register_Masks SIM Register Masks
- * @{
- */
-
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT 12
-#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT 29
-#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT 30
-#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT 31
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT 24
-#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT 25
-#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT 26
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_PTD7PAD_MASK 0x800u
-#define SIM_SOPT2_PTD7PAD_SHIFT 11
-#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT 0
-#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT 1
-#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
-#define SIM_SOPT4_FTM0FLT2_SHIFT 2
-#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT 4
-#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
-#define SIM_SOPT4_FTM2FLT0_SHIFT 8
-#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
-#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
-#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
-#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
-#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
-#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
-#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
-#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
-#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
-#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
-#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
-#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
-#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
-#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK 0x70u
-#define SIM_SDID_FAMID_SHIFT 4
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-/* SCGC2 Bit Fields */
-#define SIM_SCGC2_DAC0_MASK 0x1000u
-#define SIM_SCGC2_DAC0_SHIFT 12
-/* SCGC3 Bit Fields */
-#define SIM_SCGC3_FTM2_MASK 0x1000000u
-#define SIM_SCGC3_FTM2_SHIFT 24
-#define SIM_SCGC3_ADC1_MASK 0x8000000u
-#define SIM_SCGC3_ADC1_SHIFT 27
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK 0x2u
-#define SIM_SCGC4_EWM_SHIFT 1
-#define SIM_SCGC4_CMT_MASK 0x4u
-#define SIM_SCGC4_CMT_SHIFT 2
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_I2C1_MASK 0x80u
-#define SIM_SCGC4_I2C1_SHIFT 7
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_VREF_MASK 0x100000u
-#define SIM_SCGC4_VREF_SHIFT 20
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTIMER_MASK 0x1u
-#define SIM_SCGC5_LPTIMER_SHIFT 0
-#define SIM_SCGC5_TSI_MASK 0x20u
-#define SIM_SCGC5_TSI_SHIFT 5
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTFL_MASK 0x1u
-#define SIM_SCGC6_FTFL_SHIFT 0
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
-#define SIM_SCGC6_FLEXCAN0_SHIFT 4
-#define SIM_SCGC6_SPI0_MASK 0x1000u
-#define SIM_SCGC6_SPI0_SHIFT 12
-#define SIM_SCGC6_SPI1_MASK 0x2000u
-#define SIM_SCGC6_SPI1_SHIFT 13
-#define SIM_SCGC6_I2S_MASK 0x8000u
-#define SIM_SCGC6_I2S_SHIFT 15
-#define SIM_SCGC6_CRC_MASK 0x40000u
-#define SIM_SCGC6_CRC_SHIFT 18
-#define SIM_SCGC6_USBDCD_MASK 0x200000u
-#define SIM_SCGC6_USBDCD_SHIFT 21
-#define SIM_SCGC6_PDB_MASK 0x400000u
-#define SIM_SCGC6_PDB_SHIFT 22
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_FTM0_MASK 0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT 24
-#define SIM_SCGC6_FTM1_MASK 0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT 25
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_DMA_MASK 0x2u
-#define SIM_SCGC7_DMA_SHIFT 1
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
-#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT 0
-#define SIM_CLKDIV2_USBDIV_MASK 0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT 1
-#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_DEPART_MASK 0xF00u
-#define SIM_FCFG1_DEPART_SHIFT 8
-#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
-#define SIM_FCFG1_EESIZE_MASK 0xF0000u
-#define SIM_FCFG1_EESIZE_SHIFT 16
-#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
-#define SIM_FCFG1_NVMSIZE_SHIFT 28
-#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT 16
-#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_PFLSH_MASK 0x800000u
-#define SIM_FCFG2_PFLSH_SHIFT 23
-#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT 24
-#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT 0
-#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
-
-/**
- * @}
- */ /* end of group SIM_Register_Masks */
-
-
-/* SIM - Peripheral instance base addresses */
-/** Peripheral SIM base address */
-#define SIM_BASE (0x40047000u)
-/** Peripheral SIM base pointer */
-#define SIM ((SIM_Type *)SIM_BASE)
-
-/**
- * @}
- */ /* end of group SIM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
- * @{
- */
-
-/** SMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
- __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
- __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
- __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
-} SMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- SMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Register_Masks SMC Register Masks
- * @{
- */
-
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-#define SMC_PMCTRL_LPWUI_MASK 0x80u
-#define SMC_PMCTRL_LPWUI_SHIFT 7
-/* VLLSCTRL Bit Fields */
-#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
-#define SMC_VLLSCTRL_VLLSM_SHIFT 0
-#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
-#define SMC_VLLSCTRL_PORPO_MASK 0x20u
-#define SMC_VLLSCTRL_PORPO_SHIFT 5
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
-
-/**
- * @}
- */ /* end of group SMC_Register_Masks */
-
-
-/* SMC - Peripheral instance base addresses */
-/** Peripheral SMC base address */
-#define SMC_BASE (0x4007E000u)
-/** Peripheral SMC base pointer */
-#define SMC ((SMC_Type *)SMC_BASE)
-
-/**
- * @}
- */ /* end of group SMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
- uint8_t RESERVED_0[4];
- __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
- union { /* offset: 0xC */
- __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
- __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
- };
- uint8_t RESERVED_1[24];
- __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
- __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
- union { /* offset: 0x34 */
- __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
- __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
- };
- __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
- __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
- __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
- __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
- __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
- uint8_t RESERVED_2[48];
- __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
- __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
- __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
- __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
-} SPI_Type;
-
-/* ----------------------------------------------------------------------------
- -- SPI Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK 0x1u
-#define SPI_MCR_HALT_SHIFT 0
-#define SPI_MCR_SMPL_PT_MASK 0x300u
-#define SPI_MCR_SMPL_PT_SHIFT 8
-#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK 0x400u
-#define SPI_MCR_CLR_RXF_SHIFT 10
-#define SPI_MCR_CLR_TXF_MASK 0x800u
-#define SPI_MCR_CLR_TXF_SHIFT 11
-#define SPI_MCR_DIS_RXF_MASK 0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT 12
-#define SPI_MCR_DIS_TXF_MASK 0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT 13
-#define SPI_MCR_MDIS_MASK 0x4000u
-#define SPI_MCR_MDIS_SHIFT 14
-#define SPI_MCR_DOZE_MASK 0x8000u
-#define SPI_MCR_DOZE_SHIFT 15
-#define SPI_MCR_PCSIS_MASK 0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT 16
-#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK 0x1000000u
-#define SPI_MCR_ROOE_SHIFT 24
-#define SPI_MCR_PCSSE_MASK 0x2000000u
-#define SPI_MCR_PCSSE_SHIFT 25
-#define SPI_MCR_MTFE_MASK 0x4000000u
-#define SPI_MCR_MTFE_SHIFT 26
-#define SPI_MCR_FRZ_MASK 0x8000000u
-#define SPI_MCR_FRZ_SHIFT 27
-#define SPI_MCR_DCONF_MASK 0x30000000u
-#define SPI_MCR_DCONF_SHIFT 28
-#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT 30
-#define SPI_MCR_MSTR_MASK 0x80000000u
-#define SPI_MCR_MSTR_SHIFT 31
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT 16
-#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK 0xFu
-#define SPI_CTAR_BR_SHIFT 0
-#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK 0xF0u
-#define SPI_CTAR_DT_SHIFT 4
-#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK 0xF00u
-#define SPI_CTAR_ASC_SHIFT 8
-#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK 0xF000u
-#define SPI_CTAR_CSSCK_SHIFT 12
-#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK 0x30000u
-#define SPI_CTAR_PBR_SHIFT 16
-#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK 0xC0000u
-#define SPI_CTAR_PDT_SHIFT 18
-#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK 0x300000u
-#define SPI_CTAR_PASC_SHIFT 20
-#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK 0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT 22
-#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK 0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT 24
-#define SPI_CTAR_CPHA_MASK 0x2000000u
-#define SPI_CTAR_CPHA_SHIFT 25
-#define SPI_CTAR_CPOL_MASK 0x4000000u
-#define SPI_CTAR_CPOL_SHIFT 26
-#define SPI_CTAR_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT 27
-#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK 0x80000000u
-#define SPI_CTAR_DBR_SHIFT 31
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
-#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
-#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
-#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK 0xFu
-#define SPI_SR_POPNXTPTR_SHIFT 0
-#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK 0xF0u
-#define SPI_SR_RXCTR_SHIFT 4
-#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK 0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT 8
-#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK 0xF000u
-#define SPI_SR_TXCTR_SHIFT 12
-#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK 0x20000u
-#define SPI_SR_RFDF_SHIFT 17
-#define SPI_SR_RFOF_MASK 0x80000u
-#define SPI_SR_RFOF_SHIFT 19
-#define SPI_SR_TFFF_MASK 0x2000000u
-#define SPI_SR_TFFF_SHIFT 25
-#define SPI_SR_TFUF_MASK 0x8000000u
-#define SPI_SR_TFUF_SHIFT 27
-#define SPI_SR_EOQF_MASK 0x10000000u
-#define SPI_SR_EOQF_SHIFT 28
-#define SPI_SR_TXRXS_MASK 0x40000000u
-#define SPI_SR_TXRXS_SHIFT 30
-#define SPI_SR_TCF_MASK 0x80000000u
-#define SPI_SR_TCF_SHIFT 31
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT 16
-#define SPI_RSER_RFDF_RE_MASK 0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT 17
-#define SPI_RSER_RFOF_RE_MASK 0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT 19
-#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT 24
-#define SPI_RSER_TFFF_RE_MASK 0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT 25
-#define SPI_RSER_TFUF_RE_MASK 0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT 27
-#define SPI_RSER_EOQF_RE_MASK 0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT 28
-#define SPI_RSER_TCF_RE_MASK 0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT 31
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT 0
-#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK 0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT 16
-#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK 0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT 26
-#define SPI_PUSHR_EOQ_MASK 0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT 27
-#define SPI_PUSHR_CTAS_MASK 0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT 28
-#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK 0x80000000u
-#define SPI_PUSHR_CONT_SHIFT 31
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
-#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT 0
-#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT 0
-#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT 0
-#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT 0
-#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT 0
-#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT 0
-#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT 0
-#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT 0
-#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT 0
-#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
-
-/**
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x4002C000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-
-/**
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- TSI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
- * @{
- */
-
-/** TSI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
- __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
- __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
- __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
- uint8_t RESERVED_0[240];
- __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
- __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
- __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
- __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
- __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
- __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
- __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
- __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
- __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
-} TSI_Type;
-
-/* ----------------------------------------------------------------------------
- -- TSI Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Register_Masks TSI Register Masks
- * @{
- */
-
-/* GENCS Bit Fields */
-#define TSI_GENCS_STPE_MASK 0x1u
-#define TSI_GENCS_STPE_SHIFT 0
-#define TSI_GENCS_STM_MASK 0x2u
-#define TSI_GENCS_STM_SHIFT 1
-#define TSI_GENCS_ESOR_MASK 0x10u
-#define TSI_GENCS_ESOR_SHIFT 4
-#define TSI_GENCS_ERIE_MASK 0x20u
-#define TSI_GENCS_ERIE_SHIFT 5
-#define TSI_GENCS_TSIIE_MASK 0x40u
-#define TSI_GENCS_TSIIE_SHIFT 6
-#define TSI_GENCS_TSIEN_MASK 0x80u
-#define TSI_GENCS_TSIEN_SHIFT 7
-#define TSI_GENCS_SWTS_MASK 0x100u
-#define TSI_GENCS_SWTS_SHIFT 8
-#define TSI_GENCS_SCNIP_MASK 0x200u
-#define TSI_GENCS_SCNIP_SHIFT 9
-#define TSI_GENCS_OVRF_MASK 0x1000u
-#define TSI_GENCS_OVRF_SHIFT 12
-#define TSI_GENCS_EXTERF_MASK 0x2000u
-#define TSI_GENCS_EXTERF_SHIFT 13
-#define TSI_GENCS_OUTRGF_MASK 0x4000u
-#define TSI_GENCS_OUTRGF_SHIFT 14
-#define TSI_GENCS_EOSF_MASK 0x8000u
-#define TSI_GENCS_EOSF_SHIFT 15
-#define TSI_GENCS_PS_MASK 0x70000u
-#define TSI_GENCS_PS_SHIFT 16
-#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
-#define TSI_GENCS_NSCN_MASK 0xF80000u
-#define TSI_GENCS_NSCN_SHIFT 19
-#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
-#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
-#define TSI_GENCS_LPSCNITV_SHIFT 24
-#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
-#define TSI_GENCS_LPCLKS_MASK 0x10000000u
-#define TSI_GENCS_LPCLKS_SHIFT 28
-/* SCANC Bit Fields */
-#define TSI_SCANC_AMPSC_MASK 0x7u
-#define TSI_SCANC_AMPSC_SHIFT 0
-#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
-#define TSI_SCANC_AMCLKS_MASK 0x18u
-#define TSI_SCANC_AMCLKS_SHIFT 3
-#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
-#define TSI_SCANC_SMOD_MASK 0xFF00u
-#define TSI_SCANC_SMOD_SHIFT 8
-#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
-#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
-#define TSI_SCANC_EXTCHRG_SHIFT 16
-#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
-#define TSI_SCANC_REFCHRG_MASK 0xF000000u
-#define TSI_SCANC_REFCHRG_SHIFT 24
-#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
-/* PEN Bit Fields */
-#define TSI_PEN_PEN0_MASK 0x1u
-#define TSI_PEN_PEN0_SHIFT 0
-#define TSI_PEN_PEN1_MASK 0x2u
-#define TSI_PEN_PEN1_SHIFT 1
-#define TSI_PEN_PEN2_MASK 0x4u
-#define TSI_PEN_PEN2_SHIFT 2
-#define TSI_PEN_PEN3_MASK 0x8u
-#define TSI_PEN_PEN3_SHIFT 3
-#define TSI_PEN_PEN4_MASK 0x10u
-#define TSI_PEN_PEN4_SHIFT 4
-#define TSI_PEN_PEN5_MASK 0x20u
-#define TSI_PEN_PEN5_SHIFT 5
-#define TSI_PEN_PEN6_MASK 0x40u
-#define TSI_PEN_PEN6_SHIFT 6
-#define TSI_PEN_PEN7_MASK 0x80u
-#define TSI_PEN_PEN7_SHIFT 7
-#define TSI_PEN_PEN8_MASK 0x100u
-#define TSI_PEN_PEN8_SHIFT 8
-#define TSI_PEN_PEN9_MASK 0x200u
-#define TSI_PEN_PEN9_SHIFT 9
-#define TSI_PEN_PEN10_MASK 0x400u
-#define TSI_PEN_PEN10_SHIFT 10
-#define TSI_PEN_PEN11_MASK 0x800u
-#define TSI_PEN_PEN11_SHIFT 11
-#define TSI_PEN_PEN12_MASK 0x1000u
-#define TSI_PEN_PEN12_SHIFT 12
-#define TSI_PEN_PEN13_MASK 0x2000u
-#define TSI_PEN_PEN13_SHIFT 13
-#define TSI_PEN_PEN14_MASK 0x4000u
-#define TSI_PEN_PEN14_SHIFT 14
-#define TSI_PEN_PEN15_MASK 0x8000u
-#define TSI_PEN_PEN15_SHIFT 15
-#define TSI_PEN_LPSP_MASK 0xF0000u
-#define TSI_PEN_LPSP_SHIFT 16
-#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
-/* WUCNTR Bit Fields */
-#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
-#define TSI_WUCNTR_WUCNT_SHIFT 0
-#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
-/* CNTR1 Bit Fields */
-#define TSI_CNTR1_CTN1_MASK 0xFFFFu
-#define TSI_CNTR1_CTN1_SHIFT 0
-#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
-#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR1_CTN_SHIFT 16
-#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
-/* CNTR3 Bit Fields */
-#define TSI_CNTR3_CTN1_MASK 0xFFFFu
-#define TSI_CNTR3_CTN1_SHIFT 0
-#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
-#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR3_CTN_SHIFT 16
-#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
-/* CNTR5 Bit Fields */
-#define TSI_CNTR5_CTN1_MASK 0xFFFFu
-#define TSI_CNTR5_CTN1_SHIFT 0
-#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
-#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR5_CTN_SHIFT 16
-#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
-/* CNTR7 Bit Fields */
-#define TSI_CNTR7_CTN1_MASK 0xFFFFu
-#define TSI_CNTR7_CTN1_SHIFT 0
-#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
-#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR7_CTN_SHIFT 16
-#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
-/* CNTR9 Bit Fields */
-#define TSI_CNTR9_CTN1_MASK 0xFFFFu
-#define TSI_CNTR9_CTN1_SHIFT 0
-#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
-#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR9_CTN_SHIFT 16
-#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
-/* CNTR11 Bit Fields */
-#define TSI_CNTR11_CTN1_MASK 0xFFFFu
-#define TSI_CNTR11_CTN1_SHIFT 0
-#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
-#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR11_CTN_SHIFT 16
-#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
-/* CNTR13 Bit Fields */
-#define TSI_CNTR13_CTN1_MASK 0xFFFFu
-#define TSI_CNTR13_CTN1_SHIFT 0
-#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
-#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR13_CTN_SHIFT 16
-#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
-/* CNTR15 Bit Fields */
-#define TSI_CNTR15_CTN1_MASK 0xFFFFu
-#define TSI_CNTR15_CTN1_SHIFT 0
-#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
-#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
-#define TSI_CNTR15_CTN_SHIFT 16
-#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
-/* THRESHOLD Bit Fields */
-#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
-#define TSI_THRESHOLD_HTHH_SHIFT 0
-#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
-#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
-#define TSI_THRESHOLD_LTHH_SHIFT 16
-#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
-
-/**
- * @}
- */ /* end of group TSI_Register_Masks */
-
-
-/* TSI - Peripheral instance base addresses */
-/** Peripheral TSI0 base address */
-#define TSI0_BASE (0x40045000u)
-/** Peripheral TSI0 base pointer */
-#define TSI0 ((TSI_Type *)TSI0_BASE)
-
-/**
- * @}
- */ /* end of group TSI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- UART Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
- * @{
- */
-
-/** UART - Register Layout Typedef */
-typedef struct {
- __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
- __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
- __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
- __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
- __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
- __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
- __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
- __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
- __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
- __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
- __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
- __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
- __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
- __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
- __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
- uint8_t RESERVED_0[1];
- __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
- __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
- __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
- __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
- __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
- __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
- __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
- uint8_t RESERVED_1[1];
- __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
- __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
- __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
- union { /* offset: 0x1B */
- __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
- __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
- };
- __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
- __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
- __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
- __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
- uint8_t RESERVED_2[1];
- __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
- __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
- __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
- __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
- __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
- __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
- __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
- __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
- __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
- __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
- __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
- __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
- __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
- __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
- __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
- __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
- __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
-} UART_Type;
-
-/* ----------------------------------------------------------------------------
- -- UART Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Register_Masks UART Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_MSBF_MASK 0x20u
-#define UART_S2_MSBF_SHIFT 5
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-/* D Bit Fields */
-#define UART_D_RT_MASK 0xFFu
-#define UART_D_RT_SHIFT 0
-#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK 0xFFu
-#define UART_MA1_MA_SHIFT 0
-#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK 0xFFu
-#define UART_MA2_MA_SHIFT 0
-#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK 0x1Fu
-#define UART_C4_BRFA_SHIFT 0
-#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK 0x20u
-#define UART_C4_M10_SHIFT 5
-#define UART_C4_MAEN2_MASK 0x40u
-#define UART_C4_MAEN2_SHIFT 6
-#define UART_C4_MAEN1_MASK 0x80u
-#define UART_C4_MAEN1_SHIFT 7
-/* C5 Bit Fields */
-#define UART_C5_RDMAS_MASK 0x20u
-#define UART_C5_RDMAS_SHIFT 5
-#define UART_C5_TDMAS_MASK 0x80u
-#define UART_C5_TDMAS_SHIFT 7
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK 0x40u
-#define UART_ED_PARITYE_SHIFT 6
-#define UART_ED_NOISY_MASK 0x80u
-#define UART_ED_NOISY_SHIFT 7
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK 0x1u
-#define UART_MODEM_TXCTSE_SHIFT 0
-#define UART_MODEM_TXRTSE_MASK 0x2u
-#define UART_MODEM_TXRTSE_SHIFT 1
-#define UART_MODEM_TXRTSPOL_MASK 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT 2
-#define UART_MODEM_RXRTSE_MASK 0x8u
-#define UART_MODEM_RXRTSE_SHIFT 3
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK 0x3u
-#define UART_IR_TNP_SHIFT 0
-#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK 0x4u
-#define UART_IR_IREN_SHIFT 2
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
-#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK 0x8u
-#define UART_PFIFO_RXFE_SHIFT 3
-#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
-#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK 0x80u
-#define UART_PFIFO_TXFE_SHIFT 7
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK 0x1u
-#define UART_CFIFO_RXUFE_SHIFT 0
-#define UART_CFIFO_TXOFE_MASK 0x2u
-#define UART_CFIFO_TXOFE_SHIFT 1
-#define UART_CFIFO_RXFLUSH_MASK 0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT 6
-#define UART_CFIFO_TXFLUSH_MASK 0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT 7
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK 0x1u
-#define UART_SFIFO_RXUF_SHIFT 0
-#define UART_SFIFO_TXOF_MASK 0x2u
-#define UART_SFIFO_TXOF_SHIFT 1
-#define UART_SFIFO_RXEMPT_MASK 0x40u
-#define UART_SFIFO_RXEMPT_SHIFT 6
-#define UART_SFIFO_TXEMPT_MASK 0x80u
-#define UART_SFIFO_TXEMPT_SHIFT 7
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT 0
-#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT 0
-#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT 0
-#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT 0
-#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK 0x1u
-#define UART_C7816_ISO_7816E_SHIFT 0
-#define UART_C7816_TTYPE_MASK 0x2u
-#define UART_C7816_TTYPE_SHIFT 1
-#define UART_C7816_INIT_MASK 0x4u
-#define UART_C7816_INIT_SHIFT 2
-#define UART_C7816_ANACK_MASK 0x8u
-#define UART_C7816_ANACK_SHIFT 3
-#define UART_C7816_ONACK_MASK 0x10u
-#define UART_C7816_ONACK_SHIFT 4
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK 0x1u
-#define UART_IE7816_RXTE_SHIFT 0
-#define UART_IE7816_TXTE_MASK 0x2u
-#define UART_IE7816_TXTE_SHIFT 1
-#define UART_IE7816_GTVE_MASK 0x4u
-#define UART_IE7816_GTVE_SHIFT 2
-#define UART_IE7816_INITDE_MASK 0x10u
-#define UART_IE7816_INITDE_SHIFT 4
-#define UART_IE7816_BWTE_MASK 0x20u
-#define UART_IE7816_BWTE_SHIFT 5
-#define UART_IE7816_CWTE_MASK 0x40u
-#define UART_IE7816_CWTE_SHIFT 6
-#define UART_IE7816_WTE_MASK 0x80u
-#define UART_IE7816_WTE_SHIFT 7
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK 0x1u
-#define UART_IS7816_RXT_SHIFT 0
-#define UART_IS7816_TXT_MASK 0x2u
-#define UART_IS7816_TXT_SHIFT 1
-#define UART_IS7816_GTV_MASK 0x4u
-#define UART_IS7816_GTV_SHIFT 2
-#define UART_IS7816_INITD_MASK 0x10u
-#define UART_IS7816_INITD_SHIFT 4
-#define UART_IS7816_BWT_MASK 0x20u
-#define UART_IS7816_BWT_SHIFT 5
-#define UART_IS7816_CWT_MASK 0x40u
-#define UART_IS7816_CWT_SHIFT 6
-#define UART_IS7816_WT_MASK 0x80u
-#define UART_IS7816_WT_SHIFT 7
-/* WP7816_T_TYPE0 Bit Fields */
-#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
-#define UART_WP7816_T_TYPE0_WI_SHIFT 0
-#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
-/* WP7816_T_TYPE1 Bit Fields */
-#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
-#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
-#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
-#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
-#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
-#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK 0xFFu
-#define UART_WN7816_GTN_SHIFT 0
-#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK 0xFFu
-#define UART_WF7816_GTFD_SHIFT 0
-#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT 0
-#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT 4
-#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK 0xFFu
-#define UART_TL7816_TLEN_SHIFT 0
-#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-/* C6 Bit Fields */
-#define UART_C6_CP_MASK 0x10u
-#define UART_C6_CP_SHIFT 4
-#define UART_C6_CE_MASK 0x20u
-#define UART_C6_CE_SHIFT 5
-#define UART_C6_TX709_MASK 0x40u
-#define UART_C6_TX709_SHIFT 6
-#define UART_C6_EN709_MASK 0x80u
-#define UART_C6_EN709_SHIFT 7
-/* PCTH Bit Fields */
-#define UART_PCTH_PCTH_MASK 0xFFu
-#define UART_PCTH_PCTH_SHIFT 0
-#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
-/* PCTL Bit Fields */
-#define UART_PCTL_PCTL_MASK 0xFFu
-#define UART_PCTL_PCTL_SHIFT 0
-#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
-/* B1T Bit Fields */
-#define UART_B1T_B1T_MASK 0xFFu
-#define UART_B1T_B1T_SHIFT 0
-#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
-/* SDTH Bit Fields */
-#define UART_SDTH_SDTH_MASK 0xFFu
-#define UART_SDTH_SDTH_SHIFT 0
-#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
-/* SDTL Bit Fields */
-#define UART_SDTL_SDTL_MASK 0xFFu
-#define UART_SDTL_SDTL_SHIFT 0
-#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
-/* PRE Bit Fields */
-#define UART_PRE_PREAMBLE_MASK 0xFFu
-#define UART_PRE_PREAMBLE_SHIFT 0
-#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
-/* TPL Bit Fields */
-#define UART_TPL_TPL_MASK 0xFFu
-#define UART_TPL_TPL_SHIFT 0
-#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
-/* IE Bit Fields */
-#define UART_IE_TXFIE_MASK 0x1u
-#define UART_IE_TXFIE_SHIFT 0
-#define UART_IE_PSIE_MASK 0x2u
-#define UART_IE_PSIE_SHIFT 1
-#define UART_IE_PCTEIE_MASK 0x4u
-#define UART_IE_PCTEIE_SHIFT 2
-#define UART_IE_PTXIE_MASK 0x8u
-#define UART_IE_PTXIE_SHIFT 3
-#define UART_IE_PRXIE_MASK 0x10u
-#define UART_IE_PRXIE_SHIFT 4
-#define UART_IE_ISDIE_MASK 0x20u
-#define UART_IE_ISDIE_SHIFT 5
-#define UART_IE_WBEIE_MASK 0x40u
-#define UART_IE_WBEIE_SHIFT 6
-/* WB Bit Fields */
-#define UART_WB_WBASE_MASK 0xFFu
-#define UART_WB_WBASE_SHIFT 0
-#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
-/* S3 Bit Fields */
-#define UART_S3_TXFF_MASK 0x1u
-#define UART_S3_TXFF_SHIFT 0
-#define UART_S3_PSF_MASK 0x2u
-#define UART_S3_PSF_SHIFT 1
-#define UART_S3_PCTEF_MASK 0x4u
-#define UART_S3_PCTEF_SHIFT 2
-#define UART_S3_PTXF_MASK 0x8u
-#define UART_S3_PTXF_SHIFT 3
-#define UART_S3_PRXF_MASK 0x10u
-#define UART_S3_PRXF_SHIFT 4
-#define UART_S3_ISD_MASK 0x20u
-#define UART_S3_ISD_SHIFT 5
-#define UART_S3_WBEF_MASK 0x40u
-#define UART_S3_WBEF_SHIFT 6
-#define UART_S3_PEF_MASK 0x80u
-#define UART_S3_PEF_SHIFT 7
-/* S4 Bit Fields */
-#define UART_S4_FE_MASK 0x1u
-#define UART_S4_FE_SHIFT 0
-#define UART_S4_ILCV_MASK 0x2u
-#define UART_S4_ILCV_SHIFT 1
-#define UART_S4_CDET_MASK 0xCu
-#define UART_S4_CDET_SHIFT 2
-#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
-#define UART_S4_INITF_MASK 0x10u
-#define UART_S4_INITF_SHIFT 4
-/* RPL Bit Fields */
-#define UART_RPL_RPL_MASK 0xFFu
-#define UART_RPL_RPL_SHIFT 0
-#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
-/* RPREL Bit Fields */
-#define UART_RPREL_RPREL_MASK 0xFFu
-#define UART_RPREL_RPREL_SHIFT 0
-#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
-/* CPW Bit Fields */
-#define UART_CPW_CPW_MASK 0xFFu
-#define UART_CPW_CPW_SHIFT 0
-#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
-/* RIDT Bit Fields */
-#define UART_RIDT_RIDT_MASK 0xFFu
-#define UART_RIDT_RIDT_SHIFT 0
-#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
-/* TIDT Bit Fields */
-#define UART_TIDT_TIDT_MASK 0xFFu
-#define UART_TIDT_TIDT_SHIFT 0
-#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
-
-/**
- * @}
- */ /* end of group UART_Register_Masks */
-
-
-/* UART - Peripheral instance base addresses */
-/** Peripheral UART0 base address */
-#define UART0_BASE (0x4006A000u)
-/** Peripheral UART0 base pointer */
-#define UART0 ((UART_Type *)UART0_BASE)
-/** Peripheral UART1 base address */
-#define UART1_BASE (0x4006B000u)
-/** Peripheral UART1 base pointer */
-#define UART1 ((UART_Type *)UART1_BASE)
-/** Peripheral UART2 base address */
-#define UART2_BASE (0x4006C000u)
-/** Peripheral UART2 base pointer */
-#define UART2 ((UART_Type *)UART2_BASE)
-
-/**
- * @}
- */ /* end of group UART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
- __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
- uint8_t RESERVED_0[3];
- __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
- uint8_t RESERVED_1[3];
- __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
- uint8_t RESERVED_2[3];
- __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
- uint8_t RESERVED_3[3];
- __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
- uint8_t RESERVED_4[3];
- __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
- uint8_t RESERVED_5[3];
- __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
- uint8_t RESERVED_6[3];
- __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
- uint8_t RESERVED_7[99];
- __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
- uint8_t RESERVED_8[3];
- __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
- uint8_t RESERVED_9[3];
- __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
- uint8_t RESERVED_10[3];
- __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
- uint8_t RESERVED_11[3];
- __I uint8_t STAT; /**< Status Register, offset: 0x90 */
- uint8_t RESERVED_12[3];
- __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
- uint8_t RESERVED_13[3];
- __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
- uint8_t RESERVED_14[3];
- __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
- uint8_t RESERVED_15[3];
- __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
- uint8_t RESERVED_16[3];
- __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
- uint8_t RESERVED_17[3];
- __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
- uint8_t RESERVED_18[3];
- __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
- uint8_t RESERVED_19[3];
- __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
- uint8_t RESERVED_20[3];
- __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
- uint8_t RESERVED_21[11];
- struct { /* offset: 0xC0, array step: 0x4 */
- __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_0[3];
- } ENDPOINT[16];
- __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
- uint8_t RESERVED_22[3];
- __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
- uint8_t RESERVED_23[3];
- __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
- uint8_t RESERVED_24[3];
- __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
- uint8_t RESERVED_25[7];
- __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
-} USB_Type;
-
-/* ----------------------------------------------------------------------------
- -- USB Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-#define USB_ADDINFO_IRQNUM_MASK 0xF8u
-#define USB_ADDINFO_IRQNUM_SHIFT 3
-#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT 0
-#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
-
-/**
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x40072000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-
-/**
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USBDCD Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
- * @{
- */
-
-/** USBDCD - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
- __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
- __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
- uint8_t RESERVED_0[4];
- __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
- __IO uint32_t TIMER1; /**< , offset: 0x14 */
- __IO uint32_t TIMER2; /**< , offset: 0x18 */
-} USBDCD_Type;
-
-/* ----------------------------------------------------------------------------
- -- USBDCD Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
- * @{
- */
-
-/* CONTROL Bit Fields */
-#define USBDCD_CONTROL_IACK_MASK 0x1u
-#define USBDCD_CONTROL_IACK_SHIFT 0
-#define USBDCD_CONTROL_IF_MASK 0x100u
-#define USBDCD_CONTROL_IF_SHIFT 8
-#define USBDCD_CONTROL_IE_MASK 0x10000u
-#define USBDCD_CONTROL_IE_SHIFT 16
-#define USBDCD_CONTROL_START_MASK 0x1000000u
-#define USBDCD_CONTROL_START_SHIFT 24
-#define USBDCD_CONTROL_SR_MASK 0x2000000u
-#define USBDCD_CONTROL_SR_SHIFT 25
-/* CLOCK Bit Fields */
-#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
-#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
-#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
-#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
-#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
-/* STATUS Bit Fields */
-#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
-#define USBDCD_STATUS_SEQ_RES_SHIFT 16
-#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
-#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
-#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
-#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
-#define USBDCD_STATUS_ERR_MASK 0x100000u
-#define USBDCD_STATUS_ERR_SHIFT 20
-#define USBDCD_STATUS_TO_MASK 0x200000u
-#define USBDCD_STATUS_TO_SHIFT 21
-#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
-#define USBDCD_STATUS_ACTIVE_SHIFT 22
-/* TIMER0 Bit Fields */
-#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
-#define USBDCD_TIMER0_TUNITCON_SHIFT 0
-#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
-#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
-#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
-#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
-/* TIMER1 Bit Fields */
-#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
-#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
-#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
-#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
-#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
-#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
-/* TIMER2 Bit Fields */
-#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
-#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
-#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
-#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
-#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
-#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
-
-/**
- * @}
- */ /* end of group USBDCD_Register_Masks */
-
-
-/* USBDCD - Peripheral instance base addresses */
-/** Peripheral USBDCD base address */
-#define USBDCD_BASE (0x40035000u)
-/** Peripheral USBDCD base pointer */
-#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
-
-/**
- * @}
- */ /* end of group USBDCD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- VREF Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
- * @{
- */
-
-/** VREF - Register Layout Typedef */
-typedef struct {
- __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
- __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type;
-
-/* ----------------------------------------------------------------------------
- -- VREF Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup VREF_Register_Masks VREF Register Masks
- * @{
- */
-
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK 0x3Fu
-#define VREF_TRM_TRIM_SHIFT 0
-#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK 0x40u
-#define VREF_TRM_CHOPEN_SHIFT 6
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK 0x3u
-#define VREF_SC_MODE_LV_SHIFT 0
-#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK 0x4u
-#define VREF_SC_VREFST_SHIFT 2
-#define VREF_SC_REGEN_MASK 0x40u
-#define VREF_SC_REGEN_SHIFT 6
-#define VREF_SC_VREFEN_MASK 0x80u
-#define VREF_SC_VREFEN_SHIFT 7
-
-/**
- * @}
- */ /* end of group VREF_Register_Masks */
-
-
-/* VREF - Peripheral instance base addresses */
-/** Peripheral VREF base address */
-#define VREF_BASE (0x40074000u)
-/** Peripheral VREF base pointer */
-#define VREF ((VREF_Type *)VREF_BASE)
-
-/**
- * @}
- */ /* end of group VREF_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- WDOG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
- * @{
- */
-
-/** WDOG - Register Layout Typedef */
-typedef struct {
- __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
- __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
- __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
- __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
- __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
- __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
- __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
- __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
- __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
- __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
- __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
- __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
-} WDOG_Type;
-
-/* ----------------------------------------------------------------------------
- -- WDOG Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup WDOG_Register_Masks WDOG Register Masks
- * @{
- */
-
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT 0
-#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT 1
-#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
-#define WDOG_STCTRLH_WINEN_MASK 0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT 3
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
-#define WDOG_STCTRLH_DBGEN_MASK 0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT 5
-#define WDOG_STCTRLH_STOPEN_MASK 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT 6
-#define WDOG_STCTRLH_WAITEN_MASK 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT 7
-#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
-#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT 11
-#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT 12
-#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT 15
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
-#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT 0
-#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT 0
-#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK 0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT 0
-#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
-#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
-#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
-#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
-#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT 0
-#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT 8
-#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
-
-/**
- * @}
- */ /* end of group WDOG_Register_Masks */
-
-
-/* WDOG - Peripheral instance base addresses */
-/** Peripheral WDOG base address */
-#define WDOG_BASE (0x40052000u)
-/** Peripheral WDOG base pointer */
-#define WDOG ((WDOG_Type *)WDOG_BASE)
-
-/**
- * @}
- */ /* end of group WDOG_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma pop
-#elif defined(__CWCC__)
- #pragma pop
-#elif defined(__GNUC__)
- /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=default
-#else
- #error Not supported compiler type
-#endif
-
-/**
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
- -- Backward Compatibility
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
- * @{
- */
-
-/* No backward compatibility issues. */
-
-/**
- * @}
- */ /* end of group Backward_Compatibility_Symbols */
-
-
-#endif /* #if !defined(MK20D5_H_) */
-
-/* MK20D5.h, eof. */
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct
deleted file mode 100644
index 8e8908c28..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct
+++ /dev/null
@@ -1,13 +0,0 @@
-
-LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
- ER_IROM1 0x00000000 0x40000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(112 vect * 4 bytes) = 8_byte_aligned(0x1C0) = 0x1C0
- ; 0x10000 - 0x1C0 = 0xFE40
- RW_IRAM1 0x1FFF81C0 0xFE40 {
- .ANY (+RW +ZI)
- }
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s
deleted file mode 100644
index cbbc94aaa..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s
+++ /dev/null
@@ -1,559 +0,0 @@
-;/*****************************************************************************
-; * @file: startup_MK20DX256.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
-; * MK20DX256
-; * @version: 1.0
-; * @date: 2011-12-15
-; *
-; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-;*
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-__initial_sp EQU 0x20008000 ; Top of RAM
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
- DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
- DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
- DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
- DCD DMA4_IRQHandler ; DMA channel 4 transfer complete interrupt
- DCD DMA5_IRQHandler ; DMA channel 5 transfer complete interrupt
- DCD DMA6_IRQHandler ; DMA channel 6 transfer complete interrupt
- DCD DMA7_IRQHandler ; DMA channel 7 transfer complete interrupt
- DCD DMA8_IRQHandler ; DMA channel 8 transfer complete interrupt
- DCD DMA9_IRQHandler ; DMA channel 9 transfer complete interrupt
- DCD DMA10_IRQHandler ; DMA channel 10 transfer complete interrupt
- DCD DMA11_IRQHandler ; DMA channel 11 transfer complete interrupt
- DCD DMA12_IRQHandler ; DMA channel 12 transfer complete interrupt
- DCD DMA13_IRQHandler ; DMA channel 13 transfer complete interrupt
- DCD DMA14_IRQHandler ; DMA channel 14 transfer complete interrupt
- DCD DMA15_IRQHandler ; DMA channel 15 transfer complete interrupt
- DCD DMA_Error_IRQHandler ; DMA error interrupt
- DCD Reserved33_IRQHandler ; Reserved interrupt 33
- DCD FTFL_IRQHandler ; FTFL interrupt
- DCD Read_Collision_IRQHandler ; Read collision interrupt
- DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
- DCD LLW_IRQHandler ; Low Leakage Wakeup
- DCD Watchdog_IRQHandler ; WDOG interrupt
- DCD Reserved39_IRQHandler ; Reserved interrupt 39
- DCD I2C0_IRQHandler ; I2C0 interrupt
- DCD I2C1_IRQHandler ; I2C1 interrupt
- DCD SPI0_IRQHandler ; SPI0 interrupt
- DCD SPI1_IRQHandler ; SPI1 interrupt
- DCD Reserved44_IRQHandler ; Reserved interrupt 44
- DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
- DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
- DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
- DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
- DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
- DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
- DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
- DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
- DCD Reserved53_IRQHandler ; Reserved interrupt 53
- DCD Reserved54_IRQHandler ; Reserved interrupt 54
- DCD Reserved55_IRQHandler ; Reserved interrupt 55
- DCD Reserved56_IRQHandler ; Reserved interrupt 56
- DCD Reserved57_IRQHandler ; Reserved interrupt 57
- DCD Reserved58_IRQHandler ; Reserved interrupt 58
- DCD Reserved59_IRQHandler ; Reserved interrupt 59
- DCD UART0_LON_IRQHandler ; UART0 LON interrupt
- DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
- DCD UART0_ERR_IRQHandler ; UART0 error interrupt
- DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
- DCD UART1_ERR_IRQHandler ; UART1 error interrupt
- DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
- DCD UART2_ERR_IRQHandler ; UART2 error interrupt
- DCD Reserved67_IRQHandler ; Reserved interrupt 67
- DCD Reserved68_IRQHandler ; Reserved interrupt 68
- DCD Reserved69_IRQHandler ; Reserved interrupt 69
- DCD Reserved70_IRQHandler ; Reserved interrupt 70
- DCD Reserved71_IRQHandler ; Reserved interrupt 71
- DCD Reserved72_IRQHandler ; Reserved interrupt 72
- DCD ADC0_IRQHandler ; ADC0 interrupt
- DCD ADC1_IRQHandler ; ADC1 interrupt
- DCD CMP0_IRQHandler ; CMP0 interrupt
- DCD CMP1_IRQHandler ; CMP1 interrupt
- DCD CMP2_IRQHandler ; CMP2 interrupt
- DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
- DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
- DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
- DCD CMT_IRQHandler ; CMT interrupt
- DCD RTC_IRQHandler ; RTC interrupt
- DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
- DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
- DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
- DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
- DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
- DCD PDB0_IRQHandler ; PDB0 interrupt
- DCD USB0_IRQHandler ; USB0 interrupt
- DCD USBDCD_IRQHandler ; USBDCD interrupt
- DCD Reserved91_IRQHandler ; Reserved interrupt 91
- DCD Reserved92_IRQHandler ; Reserved interrupt 92
- DCD Reserved93_IRQHandler ; Reserved interrupt 93
- DCD Reserved94_IRQHandler ; Reserved interrupt 94
- DCD Reserved95_IRQHandler ; Reserved interrupt 95
- DCD Reserved96_IRQHandler ; Reserved interrupt 96
- DCD DAC0_IRQHandler ; DAC0 interrupt
- DCD Reserved98_IRQHandler ; Reserved interrupt 98
- DCD TSI0_IRQHandler ; TSI0 interrupt
- DCD MCG_IRQHandler ; MCG interrupt
- DCD LPTimer_IRQHandler ; LPTimer interrupt
- DCD Reserved102_IRQHandler ; Reserved interrupt 102
- DCD PORTA_IRQHandler ; Port A interrupt
- DCD PORTB_IRQHandler ; Port B interrupt
- DCD PORTC_IRQHandler ; Port C interrupt
- DCD PORTD_IRQHandler ; Port D interrupt
- DCD PORTE_IRQHandler ; Port E interrupt
- DCD Reserved108_IRQHandler ; Reserved interrupt 108
- DCD Reserved109_IRQHandler ; Reserved interrupt 109
- DCD SWI_IRQHandler ; Software interrupt
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; <h> Flash Configuration
-; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
-; <i> and security information that allows the MCU to restrict acces to the FTFL module.
-; <h> Backdoor Comparison Key
-; <o0> Backdoor Key 0 <0x0-0xFF:2>
-; <o1> Backdoor Key 1 <0x0-0xFF:2>
-; <o2> Backdoor Key 2 <0x0-0xFF:2>
-; <o3> Backdoor Key 3 <0x0-0xFF:2>
-; <o4> Backdoor Key 4 <0x0-0xFF:2>
-; <o5> Backdoor Key 5 <0x0-0xFF:2>
-; <o6> Backdoor Key 6 <0x0-0xFF:2>
-; <o7> Backdoor Key 7 <0x0-0xFF:2>
-BackDoorK0 EQU 0xFF
-BackDoorK1 EQU 0xFF
-BackDoorK2 EQU 0xFF
-BackDoorK3 EQU 0xFF
-BackDoorK4 EQU 0xFF
-BackDoorK5 EQU 0xFF
-BackDoorK6 EQU 0xFF
-BackDoorK7 EQU 0xFF
-; </h>
-; <h> Program flash protection bytes (FPROT)
-; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-; <i> Each bit protects a 1/32 region of the program flash memory.
-; <h> FPROT0
-; <i> Program flash protection bytes
-; <i> 1/32 - 8/32 region
-; <o.0> FPROT0.0
-; <o.1> FPROT0.1
-; <o.2> FPROT0.2
-; <o.3> FPROT0.3
-; <o.4> FPROT0.4
-; <o.5> FPROT0.5
-; <o.6> FPROT0.6
-; <o.7> FPROT0.7
-nFPROT0 EQU 0x00
-FPROT0 EQU nFPROT0:EOR:0xFF
-; </h>
-; <h> FPROT1
-; <i> Program Flash Region Protect Register 1
-; <i> 9/32 - 16/32 region
-; <o.0> FPROT1.0
-; <o.1> FPROT1.1
-; <o.2> FPROT1.2
-; <o.3> FPROT1.3
-; <o.4> FPROT1.4
-; <o.5> FPROT1.5
-; <o.6> FPROT1.6
-; <o.7> FPROT1.7
-nFPROT1 EQU 0x00
-FPROT1 EQU nFPROT1:EOR:0xFF
-; </h>
-; <h> FPROT2
-; <i> Program Flash Region Protect Register 2
-; <i> 17/32 - 24/32 region
-; <o.0> FPROT2.0
-; <o.1> FPROT2.1
-; <o.2> FPROT2.2
-; <o.3> FPROT2.3
-; <o.4> FPROT2.4
-; <o.5> FPROT2.5
-; <o.6> FPROT2.6
-; <o.7> FPROT2.7
-nFPROT2 EQU 0x00
-FPROT2 EQU nFPROT2:EOR:0xFF
-; </h>
-; <h> FPROT3
-; <i> Program Flash Region Protect Register 3
-; <i> 25/32 - 32/32 region
-; <o.0> FPROT3.0
-; <o.1> FPROT3.1
-; <o.2> FPROT3.2
-; <o.3> FPROT3.3
-; <o.4> FPROT3.4
-; <o.5> FPROT3.5
-; <o.6> FPROT3.6
-; <o.7> FPROT3.7
-nFPROT3 EQU 0x00
-FPROT3 EQU nFPROT3:EOR:0xFF
-; </h>
-; </h>
-; <h> Data flash protection byte (FDPROT)
-; <i> Each bit protects a 1/8 region of the data flash memory.
-; <i> (Program flash only devices: Reserved)
-; <o.0> FDPROT.0
-; <o.1> FDPROT.1
-; <o.2> FDPROT.2
-; <o.3> FDPROT.3
-; <o.4> FDPROT.4
-; <o.5> FDPROT.5
-; <o.6> FDPROT.6
-; <o.7> FDPROT.7
-nFDPROT EQU 0x00
-FDPROT EQU nFDPROT:EOR:0xFF
-; </h>
-; <h> EEPROM protection byte (FEPROT)
-; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
-; <i> (Program flash only devices: Reserved)
-; <o.0> FEPROT.0
-; <o.1> FEPROT.1
-; <o.2> FEPROT.2
-; <o.3> FEPROT.3
-; <o.4> FEPROT.4
-; <o.5> FEPROT.5
-; <o.6> FEPROT.6
-; <o.7> FEPROT.7
-nFEPROT EQU 0x00
-FEPROT EQU nFEPROT:EOR:0xFF
-; </h>
-; <h> Flash nonvolatile option byte (FOPT)
-; <i> Allows the user to customize the operation of the MCU at boot time.
-; <o.0> LPBOOT
-; <0=> Low-power boot
-; <1=> normal boot
-; <o.1> EZPORT_DIS
-; <0=> EzPort operation is enabled
-; <1=> EzPort operation is disabled
-FOPT EQU 0xFF
-; </h>
-; <h> Flash security byte (FSEC)
-; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-; <o.0..1> SEC
-; <2=> MCU security status is unsecure
-; <3=> MCU security status is secure
-; <i> Flash Security
-; <i> This bits define the security state of the MCU.
-; <o.2..3> FSLACC
-; <2=> Freescale factory access denied
-; <3=> Freescale factory access granted
-; <i> Freescale Failure Analysis Access Code
-; <i> This bits define the security state of the MCU.
-; <o.4..5> MEEN
-; <2=> Mass erase is disabled
-; <3=> Mass erase is enabled
-; <i> Mass Erase Enable Bits
-; <i> Enables and disables mass erase capability of the FTFL module
-; <o.6..7> KEYEN
-; <2=> Backdoor key access enabled
-; <3=> Backdoor key access disabled
-; <i> Backdoor key Security Enable
-; <i> These bits enable and disable backdoor key access to the FTFL module.
-FSEC EQU 0xFE
-; </h>
-; </h>
- IF :LNOT::DEF:RAM_TARGET
- AREA |.ARM.__at_0x400|, CODE, READONLY
- DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
- DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
- DCB FPROT0, FPROT1, FPROT2, FPROT3
- DCB FSEC, FOPT, FEPROT, FDPROT
- ENDIF
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT DMA0_IRQHandler [WEAK]
- EXPORT DMA1_IRQHandler [WEAK]
- EXPORT DMA2_IRQHandler [WEAK]
- EXPORT DMA3_IRQHandler [WEAK]
- EXPORT DMA4_IRQHandler [WEAK]
- EXPORT DMA5_IRQHandler [WEAK]
- EXPORT DMA6_IRQHandler [WEAK]
- EXPORT DMA7_IRQHandler [WEAK]
- EXPORT DMA8_IRQHandler [WEAK]
- EXPORT DMA9_IRQHandler [WEAK]
- EXPORT DMA10_IRQHandler [WEAK]
- EXPORT DMA11_IRQHandler [WEAK]
- EXPORT DMA12_IRQHandler [WEAK]
- EXPORT DMA13_IRQHandler [WEAK]
- EXPORT DMA14_IRQHandler [WEAK]
- EXPORT DMA15_IRQHandler [WEAK]
- EXPORT DMA_Error_IRQHandler [WEAK]
- EXPORT Reserved33_IRQHandler [WEAK]
- EXPORT FTFL_IRQHandler [WEAK]
- EXPORT Read_Collision_IRQHandler [WEAK]
- EXPORT LVD_LVW_IRQHandler [WEAK]
- EXPORT LLW_IRQHandler [WEAK]
- EXPORT Watchdog_IRQHandler [WEAK]
- EXPORT Reserved39_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT Reserved44_IRQHandler [WEAK]
- EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
- EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
- EXPORT CAN0_Error_IRQHandler [WEAK]
- EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
- EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
- EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
- EXPORT I2S0_Tx_IRQHandler [WEAK]
- EXPORT I2S0_Rx_IRQHandler [WEAK]
- EXPORT Reserved53_IRQHandler [WEAK]
- EXPORT Reserved54_IRQHandler [WEAK]
- EXPORT Reserved55_IRQHandler [WEAK]
- EXPORT Reserved56_IRQHandler [WEAK]
- EXPORT Reserved57_IRQHandler [WEAK]
- EXPORT Reserved58_IRQHandler [WEAK]
- EXPORT Reserved59_IRQHandler [WEAK]
- EXPORT UART0_LON_IRQHandler [WEAK]
- EXPORT UART0_RX_TX_IRQHandler [WEAK]
- EXPORT UART0_ERR_IRQHandler [WEAK]
- EXPORT UART1_RX_TX_IRQHandler [WEAK]
- EXPORT UART1_ERR_IRQHandler [WEAK]
- EXPORT UART2_RX_TX_IRQHandler [WEAK]
- EXPORT UART2_ERR_IRQHandler [WEAK]
- EXPORT Reserved67_IRQHandler [WEAK]
- EXPORT Reserved68_IRQHandler [WEAK]
- EXPORT Reserved69_IRQHandler [WEAK]
- EXPORT Reserved70_IRQHandler [WEAK]
- EXPORT Reserved71_IRQHandler [WEAK]
- EXPORT Reserved72_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT CMP0_IRQHandler [WEAK]
- EXPORT CMP1_IRQHandler [WEAK]
- EXPORT CMP2_IRQHandler [WEAK]
- EXPORT FTM0_IRQHandler [WEAK]
- EXPORT FTM1_IRQHandler [WEAK]
- EXPORT FTM2_IRQHandler [WEAK]
- EXPORT CMT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT RTC_Seconds_IRQHandler [WEAK]
- EXPORT PIT0_IRQHandler [WEAK]
- EXPORT PIT1_IRQHandler [WEAK]
- EXPORT PIT2_IRQHandler [WEAK]
- EXPORT PIT3_IRQHandler [WEAK]
- EXPORT PDB0_IRQHandler [WEAK]
- EXPORT USB0_IRQHandler [WEAK]
- EXPORT USBDCD_IRQHandler [WEAK]
- EXPORT Reserved91_IRQHandler [WEAK]
- EXPORT Reserved92_IRQHandler [WEAK]
- EXPORT Reserved93_IRQHandler [WEAK]
- EXPORT Reserved94_IRQHandler [WEAK]
- EXPORT Reserved95_IRQHandler [WEAK]
- EXPORT Reserved96_IRQHandler [WEAK]
- EXPORT DAC0_IRQHandler [WEAK]
- EXPORT Reserved98_IRQHandler [WEAK]
- EXPORT TSI0_IRQHandler [WEAK]
- EXPORT MCG_IRQHandler [WEAK]
- EXPORT LPTimer_IRQHandler [WEAK]
- EXPORT Reserved102_IRQHandler [WEAK]
- EXPORT PORTA_IRQHandler [WEAK]
- EXPORT PORTB_IRQHandler [WEAK]
- EXPORT PORTC_IRQHandler [WEAK]
- EXPORT PORTD_IRQHandler [WEAK]
- EXPORT PORTE_IRQHandler [WEAK]
- EXPORT Reserved108_IRQHandler [WEAK]
- EXPORT Reserved109_IRQHandler [WEAK]
- EXPORT SWI_IRQHandler [WEAK]
- EXPORT DefaultISR [WEAK]
-
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-DMA4_IRQHandler
-DMA5_IRQHandler
-DMA6_IRQHandler
-DMA7_IRQHandler
-DMA8_IRQHandler
-DMA9_IRQHandler
-DMA10_IRQHandler
-DMA11_IRQHandler
-DMA12_IRQHandler
-DMA13_IRQHandler
-DMA14_IRQHandler
-DMA15_IRQHandler
-DMA_Error_IRQHandler
-Reserved33_IRQHandler
-FTFL_IRQHandler
-Read_Collision_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-Watchdog_IRQHandler
-Reserved39_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-Reserved44_IRQHandler
-CAN0_ORed_Message_buffer_IRQHandler
-CAN0_Bus_Off_IRQHandler
-CAN0_Error_IRQHandler
-CAN0_Tx_Warning_IRQHandler
-CAN0_Rx_Warning_IRQHandler
-CAN0_Wake_Up_IRQHandler
-I2S0_Tx_IRQHandler
-I2S0_Rx_IRQHandler
-Reserved53_IRQHandler
-Reserved54_IRQHandler
-Reserved55_IRQHandler
-Reserved56_IRQHandler
-Reserved57_IRQHandler
-Reserved58_IRQHandler
-Reserved59_IRQHandler
-UART0_LON_IRQHandler
-UART0_RX_TX_IRQHandler
-UART0_ERR_IRQHandler
-UART1_RX_TX_IRQHandler
-UART1_ERR_IRQHandler
-UART2_RX_TX_IRQHandler
-UART2_ERR_IRQHandler
-Reserved67_IRQHandler
-Reserved68_IRQHandler
-Reserved69_IRQHandler
-Reserved70_IRQHandler
-Reserved71_IRQHandler
-Reserved72_IRQHandler
-ADC0_IRQHandler
-ADC1_IRQHandler
-CMP0_IRQHandler
-CMP1_IRQHandler
-CMP2_IRQHandler
-FTM0_IRQHandler
-FTM1_IRQHandler
-FTM2_IRQHandler
-CMT_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT0_IRQHandler
-PIT1_IRQHandler
-PIT2_IRQHandler
-PIT3_IRQHandler
-PDB0_IRQHandler
-USB0_IRQHandler
-USBDCD_IRQHandler
-Reserved91_IRQHandler
-Reserved92_IRQHandler
-Reserved93_IRQHandler
-Reserved94_IRQHandler
-Reserved95_IRQHandler
-Reserved96_IRQHandler
-DAC0_IRQHandler
-Reserved98_IRQHandler
-TSI0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-Reserved102_IRQHandler
-PORTA_IRQHandler
-PORTB_IRQHandler
-PORTC_IRQHandler
-PORTD_IRQHandler
-PORTE_IRQHandler
-Reserved108_IRQHandler
-Reserved109_IRQHandler
-SWI_IRQHandler
-DefaultISR
-
- B .
-
- ENDP
-
-
- ALIGN
- END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp
deleted file mode 100644
index 3296df192..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp
+++ /dev/null
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld
deleted file mode 100644
index 3a40be864..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * K20DX256 ARM GCC linker script file
- */
-
-MEMORY
-{
- VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
- FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
- FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
- RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * _reset_init : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .isr_vector :
- {
- . = 0;
- __isr_vector = .;
- KEEP(*(.isr_vector))
- *(.text.Reset_Handler)
- *(.text.SystemInit)
- . = ALIGN(4);
- } > VECTORS
-
- .flash_protect :
- {
- KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
- } > FLASH_PROTECTION
-
- .text :
- {
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
-
- } > RAM
-
- .bss :
- {
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- __bss_end__ = .;
- } > RAM
-
- .heap :
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy :
- {
- *(.stack)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s
deleted file mode 100644
index e54559a4d..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s
+++ /dev/null
@@ -1,366 +0,0 @@
-/* File: startup_MK20DX256.s
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V1.3
- * Date: 08 Feb 2012
- *
- * Copyright (c) 2015, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of the ARM Limited nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- .syntax unified
- .arch armv7-m
-
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x400
-#endif
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0xC00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector
- .align 2
- .globl __isr_vector
-
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long DMA0_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA1_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA2_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA3_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA4_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA5_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA6_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA7_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA8_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA9_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA10_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA11_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA12_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA13_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA14_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA15_IRQHandler // DMA channel 0 transfer complete interrupt
- .long DMA_Error_IRQHandler // DMA error interrupt
- .long Reserved33_IRQHandler // Reserved interrupt 33
- .long FTFL_IRQHandler // FTFL interrupt
- .long Read_Collision_IRQHandler // Read collision interrupt
- .long LVD_LVW_IRQHandler // Low Voltage Detect, Low Voltage Warning
- .long LLW_IRQHandler // Low Leakage Wakeup
- .long Watchdog_IRQHandler // WDOG interrupt
- .long Reserved39_IRQHandler // Reserved interrupt 39
- .long I2C0_IRQHandler // I2C0 interrupt
- .long I2C1_IRQHandler // I2C1 interrupt
- .long SPI0_IRQHandler // SPI0 interrupt
- .long SPI1_IRQHandler // SPI1 interrupt
- .long Reserved44_IRQHandler // Reserved interrupt 44
- .long CAN0_ORed_Message_buffer_IRQHandler // CAN0 OR'd message buffers interrupt
- .long CAN0_Bus_Off_IRQHandler // CAN0 bus off interrupt
- .long CAN0_Error_IRQHandler // CAN0 error interrupt
- .long CAN0_Tx_Warning_IRQHandler // CAN0 Tx warning interrupt
- .long CAN0_Rx_Warning_IRQHandler // CAN0 Rx warning interrupt
- .long CAN0_Wake_Up_IRQHandler // CAN0 wake up interrupt
- .long I2S0_Tx_IRQHandler // I2S0 transmit interrupt
- .long I2S0_Rx_IRQHandler // I2S0 receive interrupt
- .long Reserved53_IRQHandler // Reserved interrupt 53
- .long Reserved54_IRQHandler // Reserved interrupt 54
- .long Reserved55_IRQHandler // Reserved interrupt 55
- .long Reserved56_IRQHandler // Reserved interrupt 56
- .long Reserved57_IRQHandler // Reserved interrupt 57
- .long Reserved58_IRQHandler // Reserved interrupt 58
- .long Reserved59_IRQHandler // Reserved interrupt 59
- .long UART0_LON_IRQHandler // UART0 LON interrupt
- .long UART0_RX_TX_IRQHandler // UART0 receive/transmit interrupt
- .long UART0_ERR_IRQHandler // UART0 error interrupt
- .long UART1_RX_TX_IRQHandler // UART1 receive/transmit interrupt
- .long UART1_ERR_IRQHandler // UART1 error interrupt
- .long UART2_RX_TX_IRQHandler // UART2 receive/transmit interrupt
- .long UART2_ERR_IRQHandler // UART2 error interrupt
- .long Reserved67_IRQHandler // Reserved interrupt 67
- .long Reserved68_IRQHandler // Reserved interrupt 68
- .long Reserved69_IRQHandler // Reserved interrupt 69
- .long Reserved70_IRQHandler // Reserved interrupt 70
- .long Reserved71_IRQHandler // Reserved interrupt 71
- .long Reserved72_IRQHandler // Reserved interrupt 72
- .long ADC0_IRQHandler // ADC0 interrupt
- .long ADC1_IRQHandler // ADC1 interrupt
- .long CMP0_IRQHandler // CMP0 interrupt
- .long CMP1_IRQHandler // CMP1 interrupt
- .long CMP2_IRQHandler // CMP2 interrupt
- .long FTM0_IRQHandler // FTM0 fault, overflow and channels interrupt
- .long FTM1_IRQHandler // FTM1 fault, overflow and channels interrupt
- .long FTM2_IRQHandler // FTM2 fault, overflow and channels interrupt
- .long CMT_IRQHandler // CMT interrupt
- .long RTC_IRQHandler // RTC interrupt
- .long RTC_Seconds_IRQHandler // RTC seconds interrupt
- .long PIT0_IRQHandler // PIT timer channel 0 interrupt
- .long PIT1_IRQHandler // PIT timer channel 1 interrupt
- .long PIT2_IRQHandler // PIT timer channel 2 interrupt
- .long PIT3_IRQHandler // PIT timer channel 3 interrupt
- .long PDB0_IRQHandler // PDB0 interrupt
- .long USB0_IRQHandler // USB0 interrupt
- .long USBDCD_IRQHandler // USBDCD interrupt
- .long Reserved91_IRQHandler // Reserved interrupt 91
- .long Reserved92_IRQHandler // Reserved interrupt 92
- .long Reserved93_IRQHandler // Reserved interrupt 93
- .long Reserved94_IRQHandler // Reserved interrupt 94
- .long Reserved95_IRQHandler // Reserved interrupt 95
- .long Reserved96_IRQHandler // Reserved interrupt 96
- .long DAC0_IRQHandler // DAC0 interrupt
- .long Reserved98_IRQHandler // Reserved interrupt 98
- .long TSI0_IRQHandler // TSI0 interrupt
- .long MCG_IRQHandler // MCG interrupt
- .long LPTimer_IRQHandler // LPTimer interrupt
- .long Reserved102_IRQHandler // Reserved interrupt 102
- .long PORTA_IRQHandler // Port A interrupt
- .long PORTB_IRQHandler // Port B interrupt
- .long PORTC_IRQHandler // Port C interrupt
- .long PORTD_IRQHandler // Port D interrupt
- .long PORTE_IRQHandler // Port E interrupt
- .long Reserved108_IRQHandler // Reserved interrupt 108
- .long Reserved109_IRQHandler // Reserved interrupt 109
- .long SWI_IRQHandler // Software interrupt
-
- .size __isr_vector, . - __isr_vector
-
- .section .text.Reset_Handler
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/*
- * Call SystemInit before loading the .data section to prevent the watchdog
- * from resetting the board.
- */
- ldr r0, =SystemInit
- blx r0
-
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.Lflash_to_ram_loop:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .Lflash_to_ram_loop
-
-.Lflash_to_ram_loop_end:
-
- ldr r0, =_start
- bx r0
- .pool
- .size Reset_Handler, . - Reset_Handler
-
- .text
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_default_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- .type \handler_name, %function
-\handler_name :
- b .
- .size \handler_name, . - \handler_name
- .endm
-
- def_default_handler NMI_Handler
- def_default_handler HardFault_Handler
- def_default_handler MemManage_Handler
- def_default_handler BusFault_Handler
- def_default_handler UsageFault_Handler
- def_default_handler SVC_Handler
- def_default_handler DebugMon_Handler
- def_default_handler PendSV_Handler
- def_default_handler SysTick_Handler
- def_default_handler Default_Handler
-
- .macro def_irq_default_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
-
-
- def_irq_default_handler DMA0_IRQHandler
- def_irq_default_handler DMA1_IRQHandler
- def_irq_default_handler DMA2_IRQHandler
- def_irq_default_handler DMA3_IRQHandler
- def_irq_default_handler DMA4_IRQHandler
- def_irq_default_handler DMA5_IRQHandler
- def_irq_default_handler DMA6_IRQHandler
- def_irq_default_handler DMA7_IRQHandler
- def_irq_default_handler DMA8_IRQHandler
- def_irq_default_handler DMA9_IRQHandler
- def_irq_default_handler DMA10_IRQHandler
- def_irq_default_handler DMA11_IRQHandler
- def_irq_default_handler DMA12_IRQHandler
- def_irq_default_handler DMA13_IRQHandler
- def_irq_default_handler DMA14_IRQHandler
- def_irq_default_handler DMA15_IRQHandler
- def_irq_default_handler DMA_Error_IRQHandler
- def_irq_default_handler Reserved33_IRQHandler
- def_irq_default_handler FTFL_IRQHandler
- def_irq_default_handler Read_Collision_IRQHandler
- def_irq_default_handler LVD_LVW_IRQHandler
- def_irq_default_handler LLW_IRQHandler
- def_irq_default_handler Watchdog_IRQHandler
- def_irq_default_handler Reserved39_IRQHandler
- def_irq_default_handler I2C0_IRQHandler
- def_irq_default_handler I2C1_IRQHandler
- def_irq_default_handler SPI0_IRQHandler
- def_irq_default_handler SPI1_IRQHandler
- def_irq_default_handler Reserved44_IRQHandler
- def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler
- def_irq_default_handler CAN0_Bus_Off_IRQHandler
- def_irq_default_handler CAN0_Error_IRQHandler
- def_irq_default_handler CAN0_Tx_Warning_IRQHandler
- def_irq_default_handler CAN0_Rx_Warning_IRQHandler
- def_irq_default_handler CAN0_Wake_Up_IRQHandler
- def_irq_default_handler I2S0_Tx_IRQHandler
- def_irq_default_handler I2S0_Rx_IRQHandler
- def_irq_default_handler Reserved53_IRQHandler
- def_irq_default_handler Reserved54_IRQHandler
- def_irq_default_handler Reserved55_IRQHandler
- def_irq_default_handler Reserved56_IRQHandler
- def_irq_default_handler Reserved57_IRQHandler
- def_irq_default_handler Reserved58_IRQHandler
- def_irq_default_handler Reserved59_IRQHandler
- def_irq_default_handler UART0_LON_IRQHandler
- def_irq_default_handler UART0_RX_TX_IRQHandler
- def_irq_default_handler UART0_ERR_IRQHandler
- def_irq_default_handler UART1_RX_TX_IRQHandler
- def_irq_default_handler UART1_ERR_IRQHandler
- def_irq_default_handler UART2_RX_TX_IRQHandler
- def_irq_default_handler UART2_ERR_IRQHandler
- def_irq_default_handler Reserved67_IRQHandler
- def_irq_default_handler Reserved68_IRQHandler
- def_irq_default_handler Reserved69_IRQHandler
- def_irq_default_handler Reserved70_IRQHandler
- def_irq_default_handler Reserved71_IRQHandler
- def_irq_default_handler Reserved72_IRQHandler
- def_irq_default_handler ADC0_IRQHandler
- def_irq_default_handler ADC1_IRQHandler
- def_irq_default_handler CMP0_IRQHandler
- def_irq_default_handler CMP1_IRQHandler
- def_irq_default_handler CMP2_IRQHandler
- def_irq_default_handler FTM0_IRQHandler
- def_irq_default_handler FTM1_IRQHandler
- def_irq_default_handler FTM2_IRQHandler
- def_irq_default_handler CMT_IRQHandler
- def_irq_default_handler RTC_IRQHandler
- def_irq_default_handler RTC_Seconds_IRQHandler
- def_irq_default_handler PIT0_IRQHandler
- def_irq_default_handler PIT1_IRQHandler
- def_irq_default_handler PIT2_IRQHandler
- def_irq_default_handler PIT3_IRQHandler
- def_irq_default_handler PDB0_IRQHandler
- def_irq_default_handler USB0_IRQHandler
- def_irq_default_handler USBDCD_IRQHandler
- def_irq_default_handler Reserved91_IRQHandler
- def_irq_default_handler Reserved92_IRQHandler
- def_irq_default_handler Reserved93_IRQHandler
- def_irq_default_handler Reserved94_IRQHandler
- def_irq_default_handler Reserved95_IRQHandler
- def_irq_default_handler Reserved96_IRQHandler
- def_irq_default_handler DAC0_IRQHandler
- def_irq_default_handler Reserved98_IRQHandler
- def_irq_default_handler TSI0_IRQHandler
- def_irq_default_handler MCG_IRQHandler
- def_irq_default_handler LPTimer_IRQHandler
- def_irq_default_handler Reserved102_IRQHandler
- def_irq_default_handler PORTA_IRQHandler
- def_irq_default_handler PORTB_IRQHandler
- def_irq_default_handler PORTC_IRQHandler
- def_irq_default_handler PORTD_IRQHandler
- def_irq_default_handler PORTE_IRQHandler
- def_irq_default_handler Reserved108_IRQHandler
- def_irq_default_handler Reserved109_IRQHandler
- def_irq_default_handler SWI_IRQHandler
- def_irq_default_handler DefaultISR
-
-/* Flash protection region, placed at 0x400 */
- .text
- .thumb
- .align 2
- .section .kinetis_flash_config_field,"a",%progbits
-kinetis_flash_config:
- .long 0xffffffff
- .long 0xffffffff
- .long 0xffffffff
- .long 0xfffffffe
-
- .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h
deleted file mode 100644
index 86440692b..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
- *
- * A generic CMSIS include header, pulling in LPC11U24 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "MK20DX256.h"
-#include "cmsis_nvic.h"
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c
deleted file mode 100644
index 8148ba87f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2012 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF8000) // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- uint32_t i;
-
- // Copy and switch to dynamic vectors if the first time called
- if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
- uint32_t *old_vectors = vectors;
- vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- for (i=0; i<NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
- }
- SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
- }
- vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- return vectors[IRQn + 16];
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h
deleted file mode 100644
index ce9de13c9..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2015 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c
deleted file mode 100644
index 4f34cc76c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
-** ###################################################################
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-**
-**
-** Version: rev. 1.0, 2011-12-15
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2011-12-15)
-** Initial version
-**
-** ###################################################################
-*/
-
-/**
- * @file MK20DX256
- * @version 1.0
- * @date 2011-12-15
- * @brief Device specific configuration file for MK20DX256 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "MK20DX256.h"
-
-#define DISABLE_WDOG 1
-
-#define CLOCK_SETUP 3
-/* Predefined clock setups
- 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
- Reference clock source for MCG module is the slow internal clock source 32.768kHz
- Core clock = 41.94MHz, BusClock = 41.94MHz
- This works on Teensy3.1
- 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
- Reference clock source for MCG module is an external crystal 8MHz
- Core clock = 48MHz, BusClock = 48MHz
- 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
- Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
- Core clock = 8MHz, BusClock = 8MHz
- 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
- Reference clock source for MCG module is an external crystal 16MHz
- Core clock = 72MHz, BusClock = 48MHz
- This is the default Teensy3.1 72Mhz set up
-*/
-
-/*----------------------------------------------------------------------------
- Define clock source values
- *----------------------------------------------------------------------------*/
-#if (CLOCK_SETUP == 0)
- #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
-#elif (CLOCK_SETUP == 1)
- #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
-#elif (CLOCK_SETUP == 2)
- #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
-#elif (CLOCK_SETUP == 3)
- #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
-#endif /* (CLOCK_SETUP == 2) */
-
-
-/* ----------------------------------------------------------------------------
- -- Core clock
- ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
- -- SystemInit()
- ---------------------------------------------------------------------------- */
-void SystemInit (void) {
- /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */
-
-#if (DISABLE_WDOG)
- /* Disable the WDOG module */
- /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
- WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
- /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
- WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
- /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
- WDOG->STCTRLH = (uint16_t)0x01D2u;
-#endif /* (DISABLE_WDOG) */
-
-#if (CLOCK_SETUP == 0)
- /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/
- SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
- /* Switch to FEI Mode */
- /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
- /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
- MCG->C2 = (uint8_t)0x00u;
- /* MCG_C4: DMX32=0,DRST_DRS=1 */
- MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
- /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
- MCG->C5 = (uint8_t)0x00u;
- /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x00u;
- while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */
- while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
-
-#elif (CLOCK_SETUP == 1)
- /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/
- SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
- /* Switch to FBE Mode */
- /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- OSC0->CR = (uint8_t)0x00u;
- /* MCG->C7: OSCSEL=0 */
- MCG->C7 = (uint8_t)0x00u;
- /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- MCG->C2 = MCG_C2_RANGE0(2);
- /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
- /* MCG->C4: DMX32=0,DRST_DRS=0 */
- MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
- /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
- MCG->C5 = MCG_C5_PRDIV0(3);
- /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x00u;
- while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
- while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
- /* Switch to PBE Mode */
- /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
- MCG->C5 = MCG_C5_PRDIV0(3);
- /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
- MCG->C6 = MCG_C6_PLLS_MASK;
- while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
- while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
- /* Switch to PEE Mode */
- /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
- while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
- while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
-
-#elif (CLOCK_SETUP == 2)
- /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/
- SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
- /* Switch to FBE Mode */
- /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- OSC0->CR = (uint8_t)0x00u;
- /* MCG->C7: OSCSEL=0 */
- MCG->C7 = (uint8_t)0x00u;
- /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
- /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
- /* MCG->C4: DMX32=0,DRST_DRS=0 */
- MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
- /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
- MCG->C5 = (uint8_t)0x00u;
- /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x00u;
- while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
- while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
- /* Switch to BLPE Mode */
- /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
-
-#elif (CLOCK_SETUP == 3)
- /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 72MHz system, 36MHz flash*/
- SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
- /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
- SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
- /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
- OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
- /* Switch to FBE Mode */
- /* MCG->C7: OSCSEL=0 */
- MCG->C7 = (uint8_t)0x00u;
- /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
- //MCG->C2 = (uint8_t)0x24u;
- /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
- /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
- MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
- /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
- MCG->C5 = MCG_C5_PRDIV0(7);
- /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
- MCG->C6 = (uint8_t)0x00u;
- while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
- while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
- /* Switch to PBE Mode */
- /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
- MCG->C5 = MCG_C5_PRDIV0(5);
- /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
- MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
- while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
- while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
- /* Switch to PEE Mode */
- /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
- while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
- while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
-#endif /* (CLOCK_SETUP) */
-}
-
-/* ----------------------------------------------------------------------------
- -- SystemCoreClockUpdate()
- ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
- uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
- uint8_t Divider;
-
- if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
- /* Output of FLL or PLL is selected */
- if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
- /* FLL is selected */
- if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
- /* External reference clock is selected */
- if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
- MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
- } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
- } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
- MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
- if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
- MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
- } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
- } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
- MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
- } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
- /* Select correct multiplier to calculate the MCG output clock */
- switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
- case 0x0u:
- MCGOUTClock *= 640u;
- break;
- case 0x20u:
- MCGOUTClock *= 1280u;
- break;
- case 0x40u:
- MCGOUTClock *= 1920u;
- break;
- case 0x60u:
- MCGOUTClock *= 2560u;
- break;
- case 0x80u:
- MCGOUTClock *= 732u;
- break;
- case 0xA0u:
- MCGOUTClock *= 1464u;
- break;
- case 0xC0u:
- MCGOUTClock *= 2197u;
- break;
- case 0xE0u:
- MCGOUTClock *= 2929u;
- break;
- default:
- break;
- }
- } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
- /* PLL is selected */
- Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
- MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
- Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
- MCGOUTClock *= Divider; /* Calculate the MCG output clock */
- } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
- } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
- /* Internal reference clock is selected */
- if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
- MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
- } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
- MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
- } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
- } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
- /* External reference clock is selected */
- if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
- MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
- } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
- } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
- } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
- /* Reserved value */
- return;
- } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
- SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h
deleted file mode 100644
index 3c916d038..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
-** ###################################################################
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-**
-**
-** Version: rev. 2.0, 2012-03-19
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2011-12-15)
-** Initial version
-** - rev. 2.0 (2012-03-19)
-** PDB Peripheral register structure updated.
-** DMA Registers and bits for unsupported DMA channels removed.
-**
-** ###################################################################
-*/
-
-/**
- * @file MK20DX256
- * @version 2.0
- * @date 2012-03-19
- * @brief Device specific configuration file for MK20DX256 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef SYSTEM_MK20DX256_H_
-#define SYSTEM_MK20DX256_H_ /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #if !defined(SYSTEM_MK20DX256_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h
deleted file mode 100644
index fd48b0f8c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h
+++ /dev/null
@@ -1,10137 +0,0 @@
-/*
-** ###################################################################
-** Compilers: Keil ARM C/C++ Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
-** Version: rev. 2.5, 2014-05-06
-** Build: b140604
-**
-** Abstract:
-** CMSIS Peripheral Access Layer for MK22F51212
-**
-** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2013-07-23)
-** Initial version.
-** - rev. 1.1 (2013-09-17)
-** RM rev. 0.4 update.
-** - rev. 2.0 (2013-10-29)
-** Register accessor macros added to the memory map.
-** Symbols for Processor Expert memory map compatibility added to the memory map.
-** Startup file for gcc has been updated according to CMSIS 3.2.
-** System initialization updated.
-** - rev. 2.1 (2013-10-30)
-** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
-** - rev. 2.2 (2013-12-20)
-** Update according to reference manual rev. 0.6,
-** - rev. 2.3 (2014-01-13)
-** Update according to reference manual rev. 0.61,
-** - rev. 2.4 (2014-02-10)
-** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
-** - rev. 2.5 (2014-05-06)
-** Update according to reference manual rev. 1.0,
-** Update of system and startup files.
-** Module access macro module_BASES replaced by module_BASE_PTRS.
-**
-** ###################################################################
-*/
-
-/*!
- * @file MK22F51212.h
- * @version 2.5
- * @date 2014-05-06
- * @brief CMSIS Peripheral Access Layer for MK22F51212
- *
- * CMSIS Peripheral Access Layer for MK22F51212
- */
-
-
-/* ----------------------------------------------------------------------------
- -- MCU activation
- ---------------------------------------------------------------------------- */
-
-/* Prevention from multiple including the same memory map */
-#if !defined(MK22F51212_H_) /* Check if memory map has not been already included */
-#define MK22F51212_H_
-#define MCU_MK22F51212
-
-/* Check if another memory map has not been also included */
-#if (defined(MCU_ACTIVE))
- #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included.
-#endif /* (defined(MCU_ACTIVE)) */
-#define MCU_ACTIVE
-
-#include <stdint.h>
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0200u
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0005u
-
-/**
- * @brief Macro to calculate address of an aliased word in the peripheral
- * bitband area for a peripheral register and bit (bit band region 0x40000000 to
- * 0x400FFFFF).
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Address of the aliased word in the peripheral bitband area.
- */
-#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
- * be used for peripherals with 32bit access allowed.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
- * be used for peripherals with 16bit access allowed.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
- * be used for peripherals with 8bit access allowed.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-
-/* ----------------------------------------------------------------------------
- -- Interrupt vector numbers
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
-
-typedef enum IRQn {
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
-
- /* Device specific interrupts */
- DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
- DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
- DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
- DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
- DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
- DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
- DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
- DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
- DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
- DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
- DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
- DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
- DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
- DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
- DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
- DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
- DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
- MCM_IRQn = 17, /**< Normal Interrupt */
- FTF_IRQn = 18, /**< FTFA Command complete interrupt */
- Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
- LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
- LLW_IRQn = 21, /**< Low Leakage Wakeup */
- Watchdog_IRQn = 22, /**< WDOG Interrupt */
- RNG_IRQn = 23, /**< RNG Interrupt */
- I2C0_IRQn = 24, /**< I2C0 interrupt */
- I2C1_IRQn = 25, /**< I2C1 interrupt */
- SPI0_IRQn = 26, /**< SPI0 Interrupt */
- SPI1_IRQn = 27, /**< SPI1 Interrupt */
- I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
- I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
- LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
- UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
- UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
- UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
- UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
- UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
- UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
- Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
- Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
- ADC0_IRQn = 39, /**< ADC0 interrupt */
- CMP0_IRQn = 40, /**< CMP0 interrupt */
- CMP1_IRQn = 41, /**< CMP1 interrupt */
- FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
- FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
- FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
- Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
- RTC_IRQn = 46, /**< RTC interrupt */
- RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
- PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
- PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
- PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
- PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
- PDB0_IRQn = 52, /**< PDB0 Interrupt */
- USB0_IRQn = 53, /**< USB0 interrupt */
- Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
- Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
- DAC0_IRQn = 56, /**< DAC0 interrupt */
- MCG_IRQn = 57, /**< MCG Interrupt */
- LPTimer_IRQn = 58, /**< LPTimer interrupt */
- PORTA_IRQn = 59, /**< Port A interrupt */
- PORTB_IRQn = 60, /**< Port B interrupt */
- PORTC_IRQn = 61, /**< Port C interrupt */
- PORTD_IRQn = 62, /**< Port D interrupt */
- PORTE_IRQn = 63, /**< Port E interrupt */
- SWI_IRQn = 64, /**< Software interrupt */
- Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
- Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
- Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
- Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
- Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
- Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
- FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
- DAC1_IRQn = 72, /**< DAC1 interrupt */
- ADC1_IRQn = 73, /**< ADC1 interrupt */
- Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
- Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */
- Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */
- Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */
- Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */
- Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */
- Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */
- Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
- Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
- Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
- Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
- Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */
-} IRQn_Type;
-
-/*!
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
- -- Cortex M4 Core Configuration
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
- * @{
- */
-
-#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
-
-#include "core_cm4.h" /* Core Peripheral Access Layer */
-#include "system_MK22F51212.h" /* Device specific configuration file */
-
-/*!
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
- -- Device Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
- -- ADC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
- __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
- __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
- __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
- __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
- __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
- __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
- __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
- __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
- __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
- __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
- __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
- __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
- __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
- __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
- __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
- __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
- __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
- __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
- __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
- __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
- __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
- __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
- __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type, *ADC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register accessors */
-#define ADC_SC1_REG(base,index) ((base)->SC1[index])
-#define ADC_CFG1_REG(base) ((base)->CFG1)
-#define ADC_CFG2_REG(base) ((base)->CFG2)
-#define ADC_R_REG(base,index) ((base)->R[index])
-#define ADC_CV1_REG(base) ((base)->CV1)
-#define ADC_CV2_REG(base) ((base)->CV2)
-#define ADC_SC2_REG(base) ((base)->SC2)
-#define ADC_SC3_REG(base) ((base)->SC3)
-#define ADC_OFS_REG(base) ((base)->OFS)
-#define ADC_PG_REG(base) ((base)->PG)
-#define ADC_MG_REG(base) ((base)->MG)
-#define ADC_CLPD_REG(base) ((base)->CLPD)
-#define ADC_CLPS_REG(base) ((base)->CLPS)
-#define ADC_CLP4_REG(base) ((base)->CLP4)
-#define ADC_CLP3_REG(base) ((base)->CLP3)
-#define ADC_CLP2_REG(base) ((base)->CLP2)
-#define ADC_CLP1_REG(base) ((base)->CLP1)
-#define ADC_CLP0_REG(base) ((base)->CLP0)
-#define ADC_CLMD_REG(base) ((base)->CLMD)
-#define ADC_CLMS_REG(base) ((base)->CLMS)
-#define ADC_CLM4_REG(base) ((base)->CLM4)
-#define ADC_CLM3_REG(base) ((base)->CLM3)
-#define ADC_CLM2_REG(base) ((base)->CLM2)
-#define ADC_CLM1_REG(base) ((base)->CLM1)
-#define ADC_CLM0_REG(base) ((base)->CLM0)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- ADC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x4003B000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-#define ADC0_BASE_PTR (ADC0)
-/** Peripheral ADC1 base address */
-#define ADC1_BASE (0x40027000u)
-/** Peripheral ADC1 base pointer */
-#define ADC1 ((ADC_Type *)ADC1_BASE)
-#define ADC1_BASE_PTR (ADC1)
-/** Array initializer of ADC peripheral base addresses */
-#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASE_PTRS { ADC0, ADC1 }
-/** Interrupt vectors for the ADC peripheral type */
-#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register instance definitions */
-/* ADC0 */
-#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
-#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
-#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
-#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
-#define ADC0_RA ADC_R_REG(ADC0,0)
-#define ADC0_RB ADC_R_REG(ADC0,1)
-#define ADC0_CV1 ADC_CV1_REG(ADC0)
-#define ADC0_CV2 ADC_CV2_REG(ADC0)
-#define ADC0_SC2 ADC_SC2_REG(ADC0)
-#define ADC0_SC3 ADC_SC3_REG(ADC0)
-#define ADC0_OFS ADC_OFS_REG(ADC0)
-#define ADC0_PG ADC_PG_REG(ADC0)
-#define ADC0_MG ADC_MG_REG(ADC0)
-#define ADC0_CLPD ADC_CLPD_REG(ADC0)
-#define ADC0_CLPS ADC_CLPS_REG(ADC0)
-#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
-#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
-#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
-#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
-#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
-#define ADC0_CLMD ADC_CLMD_REG(ADC0)
-#define ADC0_CLMS ADC_CLMS_REG(ADC0)
-#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
-#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
-#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
-#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
-#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
-/* ADC1 */
-#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
-#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
-#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
-#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
-#define ADC1_RA ADC_R_REG(ADC1,0)
-#define ADC1_RB ADC_R_REG(ADC1,1)
-#define ADC1_CV1 ADC_CV1_REG(ADC1)
-#define ADC1_CV2 ADC_CV2_REG(ADC1)
-#define ADC1_SC2 ADC_SC2_REG(ADC1)
-#define ADC1_SC3 ADC_SC3_REG(ADC1)
-#define ADC1_OFS ADC_OFS_REG(ADC1)
-#define ADC1_PG ADC_PG_REG(ADC1)
-#define ADC1_MG ADC_MG_REG(ADC1)
-#define ADC1_CLPD ADC_CLPD_REG(ADC1)
-#define ADC1_CLPS ADC_CLPS_REG(ADC1)
-#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
-#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
-#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
-#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
-#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
-#define ADC1_CLMD ADC_CLMD_REG(ADC1)
-#define ADC1_CLMS ADC_CLMS_REG(ADC1)
-#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
-#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
-#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
-#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
-#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
-
-/* ADC - Register array accessors */
-#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
-#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
-#define ADC0_R(index) ADC_R_REG(ADC0,index)
-#define ADC1_R(index) ADC_R_REG(ADC1,index)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
- * @{
- */
-
-/** CMP - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
- __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
- __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
- __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
- __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
- __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type, *CMP_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register accessors */
-#define CMP_CR0_REG(base) ((base)->CR0)
-#define CMP_CR1_REG(base) ((base)->CR1)
-#define CMP_FPR_REG(base) ((base)->FPR)
-#define CMP_SCR_REG(base) ((base)->SCR)
-#define CMP_DACCR_REG(base) ((base)->DACCR)
-#define CMP_MUXCR_REG(base) ((base)->MUXCR)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Masks CMP Register Masks
- * @{
- */
-
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_TRIGM_MASK 0x20u
-#define CMP_CR1_TRIGM_SHIFT 5
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Masks */
-
-
-/* CMP - Peripheral instance base addresses */
-/** Peripheral CMP0 base address */
-#define CMP0_BASE (0x40073000u)
-/** Peripheral CMP0 base pointer */
-#define CMP0 ((CMP_Type *)CMP0_BASE)
-#define CMP0_BASE_PTR (CMP0)
-/** Peripheral CMP1 base address */
-#define CMP1_BASE (0x40073008u)
-/** Peripheral CMP1 base pointer */
-#define CMP1 ((CMP_Type *)CMP1_BASE)
-#define CMP1_BASE_PTR (CMP1)
-/** Array initializer of CMP peripheral base addresses */
-#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
-/** Array initializer of CMP peripheral base pointers */
-#define CMP_BASE_PTRS { CMP0, CMP1 }
-/** Interrupt vectors for the CMP peripheral type */
-#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register instance definitions */
-/* CMP0 */
-#define CMP0_CR0 CMP_CR0_REG(CMP0)
-#define CMP0_CR1 CMP_CR1_REG(CMP0)
-#define CMP0_FPR CMP_FPR_REG(CMP0)
-#define CMP0_SCR CMP_SCR_REG(CMP0)
-#define CMP0_DACCR CMP_DACCR_REG(CMP0)
-#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
-/* CMP1 */
-#define CMP1_CR0 CMP_CR0_REG(CMP1)
-#define CMP1_CR1 CMP_CR1_REG(CMP1)
-#define CMP1_FPR CMP_FPR_REG(CMP1)
-#define CMP1_SCR CMP_SCR_REG(CMP1)
-#define CMP1_DACCR CMP_DACCR_REG(CMP1)
-#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group CMP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CRC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
- * @{
- */
-
-/** CRC - Register Layout Typedef */
-typedef struct {
- union { /* offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
- __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
- } ACCESS16BIT;
- __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
- __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
- __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
- __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
- } ACCESS8BIT;
- };
- union { /* offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
- __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
- } GPOLY_ACCESS16BIT;
- __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
- __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
- __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
- __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
- } GPOLY_ACCESS8BIT;
- };
- union { /* offset: 0x8 */
- __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
- struct { /* offset: 0x8 */
- uint8_t RESERVED_0[3];
- __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
- } CTRL_ACCESS8BIT;
- };
-} CRC_Type, *CRC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register accessors */
-#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
-#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
-#define CRC_DATA_REG(base) ((base)->DATA)
-#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
-#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
-#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
-#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
-#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
-#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
-#define CRC_GPOLY_REG(base) ((base)->GPOLY)
-#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
-#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
-#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
-#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
-#define CRC_CTRL_REG(base) ((base)->CTRL)
-#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- CRC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Masks CRC Register Masks
- * @{
- */
-
-/* DATAL Bit Fields */
-#define CRC_DATAL_DATAL_MASK 0xFFFFu
-#define CRC_DATAL_DATAL_SHIFT 0
-#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
-/* DATAH Bit Fields */
-#define CRC_DATAH_DATAH_MASK 0xFFFFu
-#define CRC_DATAH_DATAH_SHIFT 0
-#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
-/* DATA Bit Fields */
-#define CRC_DATA_LL_MASK 0xFFu
-#define CRC_DATA_LL_SHIFT 0
-#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
-#define CRC_DATA_LU_MASK 0xFF00u
-#define CRC_DATA_LU_SHIFT 8
-#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
-#define CRC_DATA_HL_MASK 0xFF0000u
-#define CRC_DATA_HL_SHIFT 16
-#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
-#define CRC_DATA_HU_MASK 0xFF000000u
-#define CRC_DATA_HU_SHIFT 24
-#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
-/* DATALL Bit Fields */
-#define CRC_DATALL_DATALL_MASK 0xFFu
-#define CRC_DATALL_DATALL_SHIFT 0
-#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
-/* DATALU Bit Fields */
-#define CRC_DATALU_DATALU_MASK 0xFFu
-#define CRC_DATALU_DATALU_SHIFT 0
-#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
-/* DATAHL Bit Fields */
-#define CRC_DATAHL_DATAHL_MASK 0xFFu
-#define CRC_DATAHL_DATAHL_SHIFT 0
-#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
-/* DATAHU Bit Fields */
-#define CRC_DATAHU_DATAHU_MASK 0xFFu
-#define CRC_DATAHU_DATAHU_SHIFT 0
-#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT 0
-#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT 0
-#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK 0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT 0
-#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT 16
-#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
-#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
-#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
-#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
-#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK 0x1000000u
-#define CRC_CTRL_TCRC_SHIFT 24
-#define CRC_CTRL_WAS_MASK 0x2000000u
-#define CRC_CTRL_WAS_SHIFT 25
-#define CRC_CTRL_FXOR_MASK 0x4000000u
-#define CRC_CTRL_FXOR_SHIFT 26
-#define CRC_CTRL_TOTR_MASK 0x30000000u
-#define CRC_CTRL_TOTR_SHIFT 28
-#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK 0xC0000000u
-#define CRC_CTRL_TOT_SHIFT 30
-#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK 0x1u
-#define CRC_CTRLHU_TCRC_SHIFT 0
-#define CRC_CTRLHU_WAS_MASK 0x2u
-#define CRC_CTRLHU_WAS_SHIFT 1
-#define CRC_CTRLHU_FXOR_MASK 0x4u
-#define CRC_CTRLHU_FXOR_SHIFT 2
-#define CRC_CTRLHU_TOTR_MASK 0x30u
-#define CRC_CTRLHU_TOTR_SHIFT 4
-#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK 0xC0u
-#define CRC_CTRLHU_TOT_SHIFT 6
-#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Masks */
-
-
-/* CRC - Peripheral instance base addresses */
-/** Peripheral CRC base address */
-#define CRC_BASE (0x40032000u)
-/** Peripheral CRC base pointer */
-#define CRC0 ((CRC_Type *)CRC_BASE)
-#define CRC_BASE_PTR (CRC0)
-/** Array initializer of CRC peripheral base addresses */
-#define CRC_BASE_ADDRS { CRC_BASE }
-/** Array initializer of CRC peripheral base pointers */
-#define CRC_BASE_PTRS { CRC0 }
-
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register instance definitions */
-/* CRC */
-#define CRC_DATA CRC_DATA_REG(CRC0)
-#define CRC_DATAL CRC_DATAL_REG(CRC0)
-#define CRC_DATALL CRC_DATALL_REG(CRC0)
-#define CRC_DATALU CRC_DATALU_REG(CRC0)
-#define CRC_DATAH CRC_DATAH_REG(CRC0)
-#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
-#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
-#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
-#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
-#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
-#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
-#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
-#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
-#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
-#define CRC_CTRL CRC_CTRL_REG(CRC0)
-#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group CRC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DAC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
- * @{
- */
-
-/** DAC - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x2 */
- __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
- __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
- } DAT[16];
- __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
- __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
- __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
- __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type, *DAC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register accessors */
-#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
-#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
-#define DAC_SR_REG(base) ((base)->SR)
-#define DAC_C0_REG(base) ((base)->C0)
-#define DAC_C1_REG(base) ((base)->C1)
-#define DAC_C2_REG(base) ((base)->C2)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- DAC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Masks DAC Register Masks
- * @{
- */
-
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-#define DAC_SR_DACBFWMF_MASK 0x4u
-#define DAC_SR_DACBFWMF_SHIFT 2
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_DACBWIEN_MASK 0x4u
-#define DAC_C0_DACBWIEN_SHIFT 2
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFMD_MASK 0x6u
-#define DAC_C1_DACBFMD_SHIFT 1
-#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
-#define DAC_C1_DACBFWM_MASK 0x18u
-#define DAC_C1_DACBFWM_SHIFT 3
-#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0xFu
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
-#define DAC_C2_DACBFRP_MASK 0xF0u
-#define DAC_C2_DACBFRP_SHIFT 4
-#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Masks */
-
-
-/* DAC - Peripheral instance base addresses */
-/** Peripheral DAC0 base address */
-#define DAC0_BASE (0x4003F000u)
-/** Peripheral DAC0 base pointer */
-#define DAC0 ((DAC_Type *)DAC0_BASE)
-#define DAC0_BASE_PTR (DAC0)
-/** Peripheral DAC1 base address */
-#define DAC1_BASE (0x40028000u)
-/** Peripheral DAC1 base pointer */
-#define DAC1 ((DAC_Type *)DAC1_BASE)
-#define DAC1_BASE_PTR (DAC1)
-/** Array initializer of DAC peripheral base addresses */
-#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
-/** Array initializer of DAC peripheral base pointers */
-#define DAC_BASE_PTRS { DAC0, DAC1 }
-/** Interrupt vectors for the DAC peripheral type */
-#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register instance definitions */
-/* DAC0 */
-#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
-#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
-#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
-#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
-#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
-#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
-#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
-#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
-#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
-#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
-#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
-#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
-#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
-#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
-#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
-#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
-#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
-#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
-#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
-#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
-#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
-#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
-#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
-#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
-#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
-#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
-#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
-#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
-#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
-#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
-#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
-#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
-#define DAC0_SR DAC_SR_REG(DAC0)
-#define DAC0_C0 DAC_C0_REG(DAC0)
-#define DAC0_C1 DAC_C1_REG(DAC0)
-#define DAC0_C2 DAC_C2_REG(DAC0)
-/* DAC1 */
-#define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
-#define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
-#define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
-#define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
-#define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
-#define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
-#define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
-#define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
-#define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
-#define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
-#define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
-#define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
-#define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
-#define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
-#define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
-#define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
-#define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
-#define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
-#define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
-#define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
-#define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
-#define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
-#define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
-#define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
-#define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
-#define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
-#define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
-#define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
-#define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
-#define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
-#define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
-#define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
-#define DAC1_SR DAC_SR_REG(DAC1)
-#define DAC1_C0 DAC_C0_REG(DAC1)
-#define DAC1_C1 DAC_C1_REG(DAC1)
-#define DAC1_C2 DAC_C2_REG(DAC1)
-
-/* DAC - Register array accessors */
-#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
-#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
-#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
-#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group DAC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CR; /**< Control Register, offset: 0x0 */
- __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
- uint8_t RESERVED_0[4];
- __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
- uint8_t RESERVED_1[4];
- __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
- __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
- __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
- __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
- __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
- __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
- __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
- __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
- __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
- uint8_t RESERVED_2[4];
- __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
- uint8_t RESERVED_3[4];
- __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
- uint8_t RESERVED_4[4];
- __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
- uint8_t RESERVED_5[12];
- __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
- uint8_t RESERVED_6[184];
- __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
- __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
- __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
- __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
- __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
- __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
- __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
- __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
- __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
- __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
- __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
- __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
- __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
- __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
- __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
- __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
- uint8_t RESERVED_7[3824];
- struct { /* offset: 0x1000, array step: 0x20 */
- __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
- __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
- __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
- union { /* offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
- };
- __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
- __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
- __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
- union { /* offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
- };
- __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
- __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
- union { /* offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
- };
- } TCD[16];
-} DMA_Type, *DMA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register accessors */
-#define DMA_CR_REG(base) ((base)->CR)
-#define DMA_ES_REG(base) ((base)->ES)
-#define DMA_ERQ_REG(base) ((base)->ERQ)
-#define DMA_EEI_REG(base) ((base)->EEI)
-#define DMA_CEEI_REG(base) ((base)->CEEI)
-#define DMA_SEEI_REG(base) ((base)->SEEI)
-#define DMA_CERQ_REG(base) ((base)->CERQ)
-#define DMA_SERQ_REG(base) ((base)->SERQ)
-#define DMA_CDNE_REG(base) ((base)->CDNE)
-#define DMA_SSRT_REG(base) ((base)->SSRT)
-#define DMA_CERR_REG(base) ((base)->CERR)
-#define DMA_CINT_REG(base) ((base)->CINT)
-#define DMA_INT_REG(base) ((base)->INT)
-#define DMA_ERR_REG(base) ((base)->ERR)
-#define DMA_HRS_REG(base) ((base)->HRS)
-#define DMA_EARS_REG(base) ((base)->EARS)
-#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
-#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
-#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
-#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
-#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
-#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
-#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
-#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
-#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
-#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
-#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
-#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
-#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
-#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
-#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
-#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
-#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
-#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
-#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
-#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
-#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
-#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
-#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
-#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
-#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
-#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
-#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
-#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
-#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
-#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
-#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK 0x2u
-#define DMA_CR_EDBG_SHIFT 1
-#define DMA_CR_ERCA_MASK 0x4u
-#define DMA_CR_ERCA_SHIFT 2
-#define DMA_CR_HOE_MASK 0x10u
-#define DMA_CR_HOE_SHIFT 4
-#define DMA_CR_HALT_MASK 0x20u
-#define DMA_CR_HALT_SHIFT 5
-#define DMA_CR_CLM_MASK 0x40u
-#define DMA_CR_CLM_SHIFT 6
-#define DMA_CR_EMLM_MASK 0x80u
-#define DMA_CR_EMLM_SHIFT 7
-#define DMA_CR_ECX_MASK 0x10000u
-#define DMA_CR_ECX_SHIFT 16
-#define DMA_CR_CX_MASK 0x20000u
-#define DMA_CR_CX_SHIFT 17
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK 0x1u
-#define DMA_ES_DBE_SHIFT 0
-#define DMA_ES_SBE_MASK 0x2u
-#define DMA_ES_SBE_SHIFT 1
-#define DMA_ES_SGE_MASK 0x4u
-#define DMA_ES_SGE_SHIFT 2
-#define DMA_ES_NCE_MASK 0x8u
-#define DMA_ES_NCE_SHIFT 3
-#define DMA_ES_DOE_MASK 0x10u
-#define DMA_ES_DOE_SHIFT 4
-#define DMA_ES_DAE_MASK 0x20u
-#define DMA_ES_DAE_SHIFT 5
-#define DMA_ES_SOE_MASK 0x40u
-#define DMA_ES_SOE_SHIFT 6
-#define DMA_ES_SAE_MASK 0x80u
-#define DMA_ES_SAE_SHIFT 7
-#define DMA_ES_ERRCHN_MASK 0xF00u
-#define DMA_ES_ERRCHN_SHIFT 8
-#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK 0x4000u
-#define DMA_ES_CPE_SHIFT 14
-#define DMA_ES_ECX_MASK 0x10000u
-#define DMA_ES_ECX_SHIFT 16
-#define DMA_ES_VLD_MASK 0x80000000u
-#define DMA_ES_VLD_SHIFT 31
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK 0x1u
-#define DMA_ERQ_ERQ0_SHIFT 0
-#define DMA_ERQ_ERQ1_MASK 0x2u
-#define DMA_ERQ_ERQ1_SHIFT 1
-#define DMA_ERQ_ERQ2_MASK 0x4u
-#define DMA_ERQ_ERQ2_SHIFT 2
-#define DMA_ERQ_ERQ3_MASK 0x8u
-#define DMA_ERQ_ERQ3_SHIFT 3
-#define DMA_ERQ_ERQ4_MASK 0x10u
-#define DMA_ERQ_ERQ4_SHIFT 4
-#define DMA_ERQ_ERQ5_MASK 0x20u
-#define DMA_ERQ_ERQ5_SHIFT 5
-#define DMA_ERQ_ERQ6_MASK 0x40u
-#define DMA_ERQ_ERQ6_SHIFT 6
-#define DMA_ERQ_ERQ7_MASK 0x80u
-#define DMA_ERQ_ERQ7_SHIFT 7
-#define DMA_ERQ_ERQ8_MASK 0x100u
-#define DMA_ERQ_ERQ8_SHIFT 8
-#define DMA_ERQ_ERQ9_MASK 0x200u
-#define DMA_ERQ_ERQ9_SHIFT 9
-#define DMA_ERQ_ERQ10_MASK 0x400u
-#define DMA_ERQ_ERQ10_SHIFT 10
-#define DMA_ERQ_ERQ11_MASK 0x800u
-#define DMA_ERQ_ERQ11_SHIFT 11
-#define DMA_ERQ_ERQ12_MASK 0x1000u
-#define DMA_ERQ_ERQ12_SHIFT 12
-#define DMA_ERQ_ERQ13_MASK 0x2000u
-#define DMA_ERQ_ERQ13_SHIFT 13
-#define DMA_ERQ_ERQ14_MASK 0x4000u
-#define DMA_ERQ_ERQ14_SHIFT 14
-#define DMA_ERQ_ERQ15_MASK 0x8000u
-#define DMA_ERQ_ERQ15_SHIFT 15
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK 0x1u
-#define DMA_EEI_EEI0_SHIFT 0
-#define DMA_EEI_EEI1_MASK 0x2u
-#define DMA_EEI_EEI1_SHIFT 1
-#define DMA_EEI_EEI2_MASK 0x4u
-#define DMA_EEI_EEI2_SHIFT 2
-#define DMA_EEI_EEI3_MASK 0x8u
-#define DMA_EEI_EEI3_SHIFT 3
-#define DMA_EEI_EEI4_MASK 0x10u
-#define DMA_EEI_EEI4_SHIFT 4
-#define DMA_EEI_EEI5_MASK 0x20u
-#define DMA_EEI_EEI5_SHIFT 5
-#define DMA_EEI_EEI6_MASK 0x40u
-#define DMA_EEI_EEI6_SHIFT 6
-#define DMA_EEI_EEI7_MASK 0x80u
-#define DMA_EEI_EEI7_SHIFT 7
-#define DMA_EEI_EEI8_MASK 0x100u
-#define DMA_EEI_EEI8_SHIFT 8
-#define DMA_EEI_EEI9_MASK 0x200u
-#define DMA_EEI_EEI9_SHIFT 9
-#define DMA_EEI_EEI10_MASK 0x400u
-#define DMA_EEI_EEI10_SHIFT 10
-#define DMA_EEI_EEI11_MASK 0x800u
-#define DMA_EEI_EEI11_SHIFT 11
-#define DMA_EEI_EEI12_MASK 0x1000u
-#define DMA_EEI_EEI12_SHIFT 12
-#define DMA_EEI_EEI13_MASK 0x2000u
-#define DMA_EEI_EEI13_SHIFT 13
-#define DMA_EEI_EEI14_MASK 0x4000u
-#define DMA_EEI_EEI14_SHIFT 14
-#define DMA_EEI_EEI15_MASK 0x8000u
-#define DMA_EEI_EEI15_SHIFT 15
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK 0xFu
-#define DMA_CEEI_CEEI_SHIFT 0
-#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK 0x40u
-#define DMA_CEEI_CAEE_SHIFT 6
-#define DMA_CEEI_NOP_MASK 0x80u
-#define DMA_CEEI_NOP_SHIFT 7
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK 0xFu
-#define DMA_SEEI_SEEI_SHIFT 0
-#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK 0x40u
-#define DMA_SEEI_SAEE_SHIFT 6
-#define DMA_SEEI_NOP_MASK 0x80u
-#define DMA_SEEI_NOP_SHIFT 7
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK 0xFu
-#define DMA_CERQ_CERQ_SHIFT 0
-#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK 0x40u
-#define DMA_CERQ_CAER_SHIFT 6
-#define DMA_CERQ_NOP_MASK 0x80u
-#define DMA_CERQ_NOP_SHIFT 7
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK 0xFu
-#define DMA_SERQ_SERQ_SHIFT 0
-#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK 0x40u
-#define DMA_SERQ_SAER_SHIFT 6
-#define DMA_SERQ_NOP_MASK 0x80u
-#define DMA_SERQ_NOP_SHIFT 7
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK 0xFu
-#define DMA_CDNE_CDNE_SHIFT 0
-#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK 0x40u
-#define DMA_CDNE_CADN_SHIFT 6
-#define DMA_CDNE_NOP_MASK 0x80u
-#define DMA_CDNE_NOP_SHIFT 7
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK 0xFu
-#define DMA_SSRT_SSRT_SHIFT 0
-#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK 0x40u
-#define DMA_SSRT_SAST_SHIFT 6
-#define DMA_SSRT_NOP_MASK 0x80u
-#define DMA_SSRT_NOP_SHIFT 7
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK 0xFu
-#define DMA_CERR_CERR_SHIFT 0
-#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK 0x40u
-#define DMA_CERR_CAEI_SHIFT 6
-#define DMA_CERR_NOP_MASK 0x80u
-#define DMA_CERR_NOP_SHIFT 7
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK 0xFu
-#define DMA_CINT_CINT_SHIFT 0
-#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK 0x40u
-#define DMA_CINT_CAIR_SHIFT 6
-#define DMA_CINT_NOP_MASK 0x80u
-#define DMA_CINT_NOP_SHIFT 7
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK 0x1u
-#define DMA_INT_INT0_SHIFT 0
-#define DMA_INT_INT1_MASK 0x2u
-#define DMA_INT_INT1_SHIFT 1
-#define DMA_INT_INT2_MASK 0x4u
-#define DMA_INT_INT2_SHIFT 2
-#define DMA_INT_INT3_MASK 0x8u
-#define DMA_INT_INT3_SHIFT 3
-#define DMA_INT_INT4_MASK 0x10u
-#define DMA_INT_INT4_SHIFT 4
-#define DMA_INT_INT5_MASK 0x20u
-#define DMA_INT_INT5_SHIFT 5
-#define DMA_INT_INT6_MASK 0x40u
-#define DMA_INT_INT6_SHIFT 6
-#define DMA_INT_INT7_MASK 0x80u
-#define DMA_INT_INT7_SHIFT 7
-#define DMA_INT_INT8_MASK 0x100u
-#define DMA_INT_INT8_SHIFT 8
-#define DMA_INT_INT9_MASK 0x200u
-#define DMA_INT_INT9_SHIFT 9
-#define DMA_INT_INT10_MASK 0x400u
-#define DMA_INT_INT10_SHIFT 10
-#define DMA_INT_INT11_MASK 0x800u
-#define DMA_INT_INT11_SHIFT 11
-#define DMA_INT_INT12_MASK 0x1000u
-#define DMA_INT_INT12_SHIFT 12
-#define DMA_INT_INT13_MASK 0x2000u
-#define DMA_INT_INT13_SHIFT 13
-#define DMA_INT_INT14_MASK 0x4000u
-#define DMA_INT_INT14_SHIFT 14
-#define DMA_INT_INT15_MASK 0x8000u
-#define DMA_INT_INT15_SHIFT 15
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK 0x1u
-#define DMA_ERR_ERR0_SHIFT 0
-#define DMA_ERR_ERR1_MASK 0x2u
-#define DMA_ERR_ERR1_SHIFT 1
-#define DMA_ERR_ERR2_MASK 0x4u
-#define DMA_ERR_ERR2_SHIFT 2
-#define DMA_ERR_ERR3_MASK 0x8u
-#define DMA_ERR_ERR3_SHIFT 3
-#define DMA_ERR_ERR4_MASK 0x10u
-#define DMA_ERR_ERR4_SHIFT 4
-#define DMA_ERR_ERR5_MASK 0x20u
-#define DMA_ERR_ERR5_SHIFT 5
-#define DMA_ERR_ERR6_MASK 0x40u
-#define DMA_ERR_ERR6_SHIFT 6
-#define DMA_ERR_ERR7_MASK 0x80u
-#define DMA_ERR_ERR7_SHIFT 7
-#define DMA_ERR_ERR8_MASK 0x100u
-#define DMA_ERR_ERR8_SHIFT 8
-#define DMA_ERR_ERR9_MASK 0x200u
-#define DMA_ERR_ERR9_SHIFT 9
-#define DMA_ERR_ERR10_MASK 0x400u
-#define DMA_ERR_ERR10_SHIFT 10
-#define DMA_ERR_ERR11_MASK 0x800u
-#define DMA_ERR_ERR11_SHIFT 11
-#define DMA_ERR_ERR12_MASK 0x1000u
-#define DMA_ERR_ERR12_SHIFT 12
-#define DMA_ERR_ERR13_MASK 0x2000u
-#define DMA_ERR_ERR13_SHIFT 13
-#define DMA_ERR_ERR14_MASK 0x4000u
-#define DMA_ERR_ERR14_SHIFT 14
-#define DMA_ERR_ERR15_MASK 0x8000u
-#define DMA_ERR_ERR15_SHIFT 15
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK 0x1u
-#define DMA_HRS_HRS0_SHIFT 0
-#define DMA_HRS_HRS1_MASK 0x2u
-#define DMA_HRS_HRS1_SHIFT 1
-#define DMA_HRS_HRS2_MASK 0x4u
-#define DMA_HRS_HRS2_SHIFT 2
-#define DMA_HRS_HRS3_MASK 0x8u
-#define DMA_HRS_HRS3_SHIFT 3
-#define DMA_HRS_HRS4_MASK 0x10u
-#define DMA_HRS_HRS4_SHIFT 4
-#define DMA_HRS_HRS5_MASK 0x20u
-#define DMA_HRS_HRS5_SHIFT 5
-#define DMA_HRS_HRS6_MASK 0x40u
-#define DMA_HRS_HRS6_SHIFT 6
-#define DMA_HRS_HRS7_MASK 0x80u
-#define DMA_HRS_HRS7_SHIFT 7
-#define DMA_HRS_HRS8_MASK 0x100u
-#define DMA_HRS_HRS8_SHIFT 8
-#define DMA_HRS_HRS9_MASK 0x200u
-#define DMA_HRS_HRS9_SHIFT 9
-#define DMA_HRS_HRS10_MASK 0x400u
-#define DMA_HRS_HRS10_SHIFT 10
-#define DMA_HRS_HRS11_MASK 0x800u
-#define DMA_HRS_HRS11_SHIFT 11
-#define DMA_HRS_HRS12_MASK 0x1000u
-#define DMA_HRS_HRS12_SHIFT 12
-#define DMA_HRS_HRS13_MASK 0x2000u
-#define DMA_HRS_HRS13_SHIFT 13
-#define DMA_HRS_HRS14_MASK 0x4000u
-#define DMA_HRS_HRS14_SHIFT 14
-#define DMA_HRS_HRS15_MASK 0x8000u
-#define DMA_HRS_HRS15_SHIFT 15
-/* EARS Bit Fields */
-#define DMA_EARS_EDREQ_0_MASK 0x1u
-#define DMA_EARS_EDREQ_0_SHIFT 0
-#define DMA_EARS_EDREQ_1_MASK 0x2u
-#define DMA_EARS_EDREQ_1_SHIFT 1
-#define DMA_EARS_EDREQ_2_MASK 0x4u
-#define DMA_EARS_EDREQ_2_SHIFT 2
-#define DMA_EARS_EDREQ_3_MASK 0x8u
-#define DMA_EARS_EDREQ_3_SHIFT 3
-#define DMA_EARS_EDREQ_4_MASK 0x10u
-#define DMA_EARS_EDREQ_4_SHIFT 4
-#define DMA_EARS_EDREQ_5_MASK 0x20u
-#define DMA_EARS_EDREQ_5_SHIFT 5
-#define DMA_EARS_EDREQ_6_MASK 0x40u
-#define DMA_EARS_EDREQ_6_SHIFT 6
-#define DMA_EARS_EDREQ_7_MASK 0x80u
-#define DMA_EARS_EDREQ_7_SHIFT 7
-#define DMA_EARS_EDREQ_8_MASK 0x100u
-#define DMA_EARS_EDREQ_8_SHIFT 8
-#define DMA_EARS_EDREQ_9_MASK 0x200u
-#define DMA_EARS_EDREQ_9_SHIFT 9
-#define DMA_EARS_EDREQ_10_MASK 0x400u
-#define DMA_EARS_EDREQ_10_SHIFT 10
-#define DMA_EARS_EDREQ_11_MASK 0x800u
-#define DMA_EARS_EDREQ_11_SHIFT 11
-#define DMA_EARS_EDREQ_12_MASK 0x1000u
-#define DMA_EARS_EDREQ_12_SHIFT 12
-#define DMA_EARS_EDREQ_13_MASK 0x2000u
-#define DMA_EARS_EDREQ_13_SHIFT 13
-#define DMA_EARS_EDREQ_14_MASK 0x4000u
-#define DMA_EARS_EDREQ_14_SHIFT 14
-#define DMA_EARS_EDREQ_15_MASK 0x8000u
-#define DMA_EARS_EDREQ_15_SHIFT 15
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK 0xFu
-#define DMA_DCHPRI3_CHPRI_SHIFT 0
-#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK 0x40u
-#define DMA_DCHPRI3_DPA_SHIFT 6
-#define DMA_DCHPRI3_ECP_MASK 0x80u
-#define DMA_DCHPRI3_ECP_SHIFT 7
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK 0xFu
-#define DMA_DCHPRI2_CHPRI_SHIFT 0
-#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK 0x40u
-#define DMA_DCHPRI2_DPA_SHIFT 6
-#define DMA_DCHPRI2_ECP_MASK 0x80u
-#define DMA_DCHPRI2_ECP_SHIFT 7
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK 0xFu
-#define DMA_DCHPRI1_CHPRI_SHIFT 0
-#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK 0x40u
-#define DMA_DCHPRI1_DPA_SHIFT 6
-#define DMA_DCHPRI1_ECP_MASK 0x80u
-#define DMA_DCHPRI1_ECP_SHIFT 7
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK 0xFu
-#define DMA_DCHPRI0_CHPRI_SHIFT 0
-#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK 0x40u
-#define DMA_DCHPRI0_DPA_SHIFT 6
-#define DMA_DCHPRI0_ECP_MASK 0x80u
-#define DMA_DCHPRI0_ECP_SHIFT 7
-/* DCHPRI7 Bit Fields */
-#define DMA_DCHPRI7_CHPRI_MASK 0xFu
-#define DMA_DCHPRI7_CHPRI_SHIFT 0
-#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
-#define DMA_DCHPRI7_DPA_MASK 0x40u
-#define DMA_DCHPRI7_DPA_SHIFT 6
-#define DMA_DCHPRI7_ECP_MASK 0x80u
-#define DMA_DCHPRI7_ECP_SHIFT 7
-/* DCHPRI6 Bit Fields */
-#define DMA_DCHPRI6_CHPRI_MASK 0xFu
-#define DMA_DCHPRI6_CHPRI_SHIFT 0
-#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
-#define DMA_DCHPRI6_DPA_MASK 0x40u
-#define DMA_DCHPRI6_DPA_SHIFT 6
-#define DMA_DCHPRI6_ECP_MASK 0x80u
-#define DMA_DCHPRI6_ECP_SHIFT 7
-/* DCHPRI5 Bit Fields */
-#define DMA_DCHPRI5_CHPRI_MASK 0xFu
-#define DMA_DCHPRI5_CHPRI_SHIFT 0
-#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
-#define DMA_DCHPRI5_DPA_MASK 0x40u
-#define DMA_DCHPRI5_DPA_SHIFT 6
-#define DMA_DCHPRI5_ECP_MASK 0x80u
-#define DMA_DCHPRI5_ECP_SHIFT 7
-/* DCHPRI4 Bit Fields */
-#define DMA_DCHPRI4_CHPRI_MASK 0xFu
-#define DMA_DCHPRI4_CHPRI_SHIFT 0
-#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
-#define DMA_DCHPRI4_DPA_MASK 0x40u
-#define DMA_DCHPRI4_DPA_SHIFT 6
-#define DMA_DCHPRI4_ECP_MASK 0x80u
-#define DMA_DCHPRI4_ECP_SHIFT 7
-/* DCHPRI11 Bit Fields */
-#define DMA_DCHPRI11_CHPRI_MASK 0xFu
-#define DMA_DCHPRI11_CHPRI_SHIFT 0
-#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
-#define DMA_DCHPRI11_DPA_MASK 0x40u
-#define DMA_DCHPRI11_DPA_SHIFT 6
-#define DMA_DCHPRI11_ECP_MASK 0x80u
-#define DMA_DCHPRI11_ECP_SHIFT 7
-/* DCHPRI10 Bit Fields */
-#define DMA_DCHPRI10_CHPRI_MASK 0xFu
-#define DMA_DCHPRI10_CHPRI_SHIFT 0
-#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
-#define DMA_DCHPRI10_DPA_MASK 0x40u
-#define DMA_DCHPRI10_DPA_SHIFT 6
-#define DMA_DCHPRI10_ECP_MASK 0x80u
-#define DMA_DCHPRI10_ECP_SHIFT 7
-/* DCHPRI9 Bit Fields */
-#define DMA_DCHPRI9_CHPRI_MASK 0xFu
-#define DMA_DCHPRI9_CHPRI_SHIFT 0
-#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
-#define DMA_DCHPRI9_DPA_MASK 0x40u
-#define DMA_DCHPRI9_DPA_SHIFT 6
-#define DMA_DCHPRI9_ECP_MASK 0x80u
-#define DMA_DCHPRI9_ECP_SHIFT 7
-/* DCHPRI8 Bit Fields */
-#define DMA_DCHPRI8_CHPRI_MASK 0xFu
-#define DMA_DCHPRI8_CHPRI_SHIFT 0
-#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
-#define DMA_DCHPRI8_DPA_MASK 0x40u
-#define DMA_DCHPRI8_DPA_SHIFT 6
-#define DMA_DCHPRI8_ECP_MASK 0x80u
-#define DMA_DCHPRI8_ECP_SHIFT 7
-/* DCHPRI15 Bit Fields */
-#define DMA_DCHPRI15_CHPRI_MASK 0xFu
-#define DMA_DCHPRI15_CHPRI_SHIFT 0
-#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
-#define DMA_DCHPRI15_DPA_MASK 0x40u
-#define DMA_DCHPRI15_DPA_SHIFT 6
-#define DMA_DCHPRI15_ECP_MASK 0x80u
-#define DMA_DCHPRI15_ECP_SHIFT 7
-/* DCHPRI14 Bit Fields */
-#define DMA_DCHPRI14_CHPRI_MASK 0xFu
-#define DMA_DCHPRI14_CHPRI_SHIFT 0
-#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
-#define DMA_DCHPRI14_DPA_MASK 0x40u
-#define DMA_DCHPRI14_DPA_SHIFT 6
-#define DMA_DCHPRI14_ECP_MASK 0x80u
-#define DMA_DCHPRI14_ECP_SHIFT 7
-/* DCHPRI13 Bit Fields */
-#define DMA_DCHPRI13_CHPRI_MASK 0xFu
-#define DMA_DCHPRI13_CHPRI_SHIFT 0
-#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
-#define DMA_DCHPRI13_DPA_MASK 0x40u
-#define DMA_DCHPRI13_DPA_SHIFT 6
-#define DMA_DCHPRI13_ECP_MASK 0x80u
-#define DMA_DCHPRI13_ECP_SHIFT 7
-/* DCHPRI12 Bit Fields */
-#define DMA_DCHPRI12_CHPRI_MASK 0xFu
-#define DMA_DCHPRI12_CHPRI_SHIFT 0
-#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
-#define DMA_DCHPRI12_DPA_MASK 0x40u
-#define DMA_DCHPRI12_DPA_SHIFT 6
-#define DMA_DCHPRI12_ECP_MASK 0x80u
-#define DMA_DCHPRI12_ECP_SHIFT 7
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT 0
-#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK 0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT 0
-#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK 0x7u
-#define DMA_ATTR_DSIZE_SHIFT 0
-#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK 0xF8u
-#define DMA_ATTR_DMOD_SHIFT 3
-#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK 0x700u
-#define DMA_ATTR_SSIZE_SHIFT 8
-#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK 0xF800u
-#define DMA_ATTR_SMOD_SHIFT 11
-#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
-#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT 0
-#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT 0
-#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK 0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT 0
-#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT 0
-#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT 0
-#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
-#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK 0x1u
-#define DMA_CSR_START_SHIFT 0
-#define DMA_CSR_INTMAJOR_MASK 0x2u
-#define DMA_CSR_INTMAJOR_SHIFT 1
-#define DMA_CSR_INTHALF_MASK 0x4u
-#define DMA_CSR_INTHALF_SHIFT 2
-#define DMA_CSR_DREQ_MASK 0x8u
-#define DMA_CSR_DREQ_SHIFT 3
-#define DMA_CSR_ESG_MASK 0x10u
-#define DMA_CSR_ESG_SHIFT 4
-#define DMA_CSR_MAJORELINK_MASK 0x20u
-#define DMA_CSR_MAJORELINK_SHIFT 5
-#define DMA_CSR_ACTIVE_MASK 0x40u
-#define DMA_CSR_ACTIVE_SHIFT 6
-#define DMA_CSR_DONE_MASK 0x80u
-#define DMA_CSR_DONE_SHIFT 7
-#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
-#define DMA_CSR_MAJORLINKCH_SHIFT 8
-#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK 0xC000u
-#define DMA_CSR_BWC_SHIFT 14
-#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT 0
-#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT 0
-#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
-
-/*!
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA base address */
-#define DMA_BASE (0x40008000u)
-/** Peripheral DMA base pointer */
-#define DMA0 ((DMA_Type *)DMA_BASE)
-#define DMA_BASE_PTR (DMA0)
-/** Array initializer of DMA peripheral base addresses */
-#define DMA_BASE_ADDRS { DMA_BASE }
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASE_PTRS { DMA0 }
-/** Interrupt vectors for the DMA peripheral type */
-#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
-#define DMA_ERROR_IRQS { DMA_Error_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register instance definitions */
-/* DMA */
-#define DMA_CR DMA_CR_REG(DMA0)
-#define DMA_ES DMA_ES_REG(DMA0)
-#define DMA_ERQ DMA_ERQ_REG(DMA0)
-#define DMA_EEI DMA_EEI_REG(DMA0)
-#define DMA_CEEI DMA_CEEI_REG(DMA0)
-#define DMA_SEEI DMA_SEEI_REG(DMA0)
-#define DMA_CERQ DMA_CERQ_REG(DMA0)
-#define DMA_SERQ DMA_SERQ_REG(DMA0)
-#define DMA_CDNE DMA_CDNE_REG(DMA0)
-#define DMA_SSRT DMA_SSRT_REG(DMA0)
-#define DMA_CERR DMA_CERR_REG(DMA0)
-#define DMA_CINT DMA_CINT_REG(DMA0)
-#define DMA_INT DMA_INT_REG(DMA0)
-#define DMA_ERR DMA_ERR_REG(DMA0)
-#define DMA_HRS DMA_HRS_REG(DMA0)
-#define DMA_EARS DMA_EARS_REG(DMA0)
-#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
-#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
-#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
-#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
-#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
-#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
-#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
-#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
-#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
-#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
-#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
-#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
-#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
-#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
-#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
-#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
-#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
-#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
-#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
-#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
-#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
-#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
-#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
-#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
-#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
-#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
-#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
-#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
-#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
-#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
-#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
-#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
-#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
-#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
-#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
-#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
-#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
-#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
-#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
-#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
-#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
-#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
-#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
-#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
-#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
-#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
-#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
-#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
-#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
-#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
-#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
-#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
-#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
-#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
-#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
-#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
-#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
-#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
-#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
-#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
-#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
-#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
-#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
-#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
-#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
-#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
-#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
-#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
-#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
-#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
-#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
-#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
-#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
-#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
-#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
-#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
-#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
-#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
-#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
-#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
-#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
-#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
-#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
-#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
-#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
-#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
-#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
-#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
-#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
-#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
-#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
-#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
-#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
-#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
-#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
-#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
-#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
-#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
-#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
-#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
-#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
-#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
-#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
-#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
-#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
-#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
-#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
-#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
-#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
-#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
-#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
-#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
-#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
-#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
-
-/* DMA - Register array accessors */
-#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
-#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
-#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
-#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
-#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
-#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
-#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
-#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
-#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
-#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
-#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
-#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
-#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
- * @{
- */
-
-/** DMAMUX - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type, *DMAMUX_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register accessors */
-#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
- * @{
- */
-
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Masks */
-
-
-/* DMAMUX - Peripheral instance base addresses */
-/** Peripheral DMAMUX base address */
-#define DMAMUX_BASE (0x40021000u)
-/** Peripheral DMAMUX base pointer */
-#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
-#define DMAMUX_BASE_PTR (DMAMUX)
-/** Array initializer of DMAMUX peripheral base addresses */
-#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
-/** Array initializer of DMAMUX peripheral base pointers */
-#define DMAMUX_BASE_PTRS { DMAMUX }
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register instance definitions */
-/* DMAMUX */
-#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
-#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
-#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
-#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
-#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
-#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
-#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
-#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
-#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
-#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
-#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
-#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
-#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
-#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
-#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
-#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
-
-/* DMAMUX - Register array accessors */
-#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group DMAMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- EWM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
- * @{
- */
-
-/** EWM - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
- __O uint8_t SERV; /**< Service Register, offset: 0x1 */
- __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
- __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
- uint8_t RESERVED_0[1];
- __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
-} EWM_Type, *EWM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register accessors */
-#define EWM_CTRL_REG(base) ((base)->CTRL)
-#define EWM_SERV_REG(base) ((base)->SERV)
-#define EWM_CMPL_REG(base) ((base)->CMPL)
-#define EWM_CMPH_REG(base) ((base)->CMPH)
-#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- EWM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
-
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK 0x1u
-#define EWM_CTRL_EWMEN_SHIFT 0
-#define EWM_CTRL_ASSIN_MASK 0x2u
-#define EWM_CTRL_ASSIN_SHIFT 1
-#define EWM_CTRL_INEN_MASK 0x4u
-#define EWM_CTRL_INEN_SHIFT 2
-#define EWM_CTRL_INTEN_MASK 0x8u
-#define EWM_CTRL_INTEN_SHIFT 3
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK 0xFFu
-#define EWM_SERV_SERVICE_SHIFT 0
-#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK 0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT 0
-#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK 0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT 0
-#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
-/* CLKPRESCALER Bit Fields */
-#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
-#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
-#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Masks */
-
-
-/* EWM - Peripheral instance base addresses */
-/** Peripheral EWM base address */
-#define EWM_BASE (0x40061000u)
-/** Peripheral EWM base pointer */
-#define EWM ((EWM_Type *)EWM_BASE)
-#define EWM_BASE_PTR (EWM)
-/** Array initializer of EWM peripheral base addresses */
-#define EWM_BASE_ADDRS { EWM_BASE }
-/** Array initializer of EWM peripheral base pointers */
-#define EWM_BASE_PTRS { EWM }
-/** Interrupt vectors for the EWM peripheral type */
-#define EWM_IRQS { Watchdog_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register instance definitions */
-/* EWM */
-#define EWM_CTRL EWM_CTRL_REG(EWM)
-#define EWM_SERV EWM_SERV_REG(EWM)
-#define EWM_CMPL EWM_CMPL_REG(EWM)
-#define EWM_CMPH EWM_CMPH_REG(EWM)
-#define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group EWM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
- * @{
- */
-
-/** FB - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0xC */
- __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
- __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
- __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
- } CS[6];
- uint8_t RESERVED_0[24];
- __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
-} FB_Type, *FB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register accessors */
-#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
-#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
-#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
-#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FB Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Masks FB Register Masks
- * @{
- */
-
-/* CSAR Bit Fields */
-#define FB_CSAR_BA_MASK 0xFFFF0000u
-#define FB_CSAR_BA_SHIFT 16
-#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
-/* CSMR Bit Fields */
-#define FB_CSMR_V_MASK 0x1u
-#define FB_CSMR_V_SHIFT 0
-#define FB_CSMR_WP_MASK 0x100u
-#define FB_CSMR_WP_SHIFT 8
-#define FB_CSMR_BAM_MASK 0xFFFF0000u
-#define FB_CSMR_BAM_SHIFT 16
-#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
-/* CSCR Bit Fields */
-#define FB_CSCR_BSTW_MASK 0x8u
-#define FB_CSCR_BSTW_SHIFT 3
-#define FB_CSCR_BSTR_MASK 0x10u
-#define FB_CSCR_BSTR_SHIFT 4
-#define FB_CSCR_BEM_MASK 0x20u
-#define FB_CSCR_BEM_SHIFT 5
-#define FB_CSCR_PS_MASK 0xC0u
-#define FB_CSCR_PS_SHIFT 6
-#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
-#define FB_CSCR_AA_MASK 0x100u
-#define FB_CSCR_AA_SHIFT 8
-#define FB_CSCR_BLS_MASK 0x200u
-#define FB_CSCR_BLS_SHIFT 9
-#define FB_CSCR_WS_MASK 0xFC00u
-#define FB_CSCR_WS_SHIFT 10
-#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
-#define FB_CSCR_WRAH_MASK 0x30000u
-#define FB_CSCR_WRAH_SHIFT 16
-#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
-#define FB_CSCR_RDAH_MASK 0xC0000u
-#define FB_CSCR_RDAH_SHIFT 18
-#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
-#define FB_CSCR_ASET_MASK 0x300000u
-#define FB_CSCR_ASET_SHIFT 20
-#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
-#define FB_CSCR_EXTS_MASK 0x400000u
-#define FB_CSCR_EXTS_SHIFT 22
-#define FB_CSCR_SWSEN_MASK 0x800000u
-#define FB_CSCR_SWSEN_SHIFT 23
-#define FB_CSCR_SWS_MASK 0xFC000000u
-#define FB_CSCR_SWS_SHIFT 26
-#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
-/* CSPMCR Bit Fields */
-#define FB_CSPMCR_GROUP5_MASK 0xF000u
-#define FB_CSPMCR_GROUP5_SHIFT 12
-#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
-#define FB_CSPMCR_GROUP4_MASK 0xF0000u
-#define FB_CSPMCR_GROUP4_SHIFT 16
-#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
-#define FB_CSPMCR_GROUP3_MASK 0xF00000u
-#define FB_CSPMCR_GROUP3_SHIFT 20
-#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
-#define FB_CSPMCR_GROUP2_MASK 0xF000000u
-#define FB_CSPMCR_GROUP2_SHIFT 24
-#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
-#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
-#define FB_CSPMCR_GROUP1_SHIFT 28
-#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
-
-/*!
- * @}
- */ /* end of group FB_Register_Masks */
-
-
-/* FB - Peripheral instance base addresses */
-/** Peripheral FB base address */
-#define FB_BASE (0x4000C000u)
-/** Peripheral FB base pointer */
-#define FB ((FB_Type *)FB_BASE)
-#define FB_BASE_PTR (FB)
-/** Array initializer of FB peripheral base addresses */
-#define FB_BASE_ADDRS { FB_BASE }
-/** Array initializer of FB peripheral base pointers */
-#define FB_BASE_PTRS { FB }
-
-/* ----------------------------------------------------------------------------
- -- FB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register instance definitions */
-/* FB */
-#define FB_CSAR0 FB_CSAR_REG(FB,0)
-#define FB_CSMR0 FB_CSMR_REG(FB,0)
-#define FB_CSCR0 FB_CSCR_REG(FB,0)
-#define FB_CSAR1 FB_CSAR_REG(FB,1)
-#define FB_CSMR1 FB_CSMR_REG(FB,1)
-#define FB_CSCR1 FB_CSCR_REG(FB,1)
-#define FB_CSAR2 FB_CSAR_REG(FB,2)
-#define FB_CSMR2 FB_CSMR_REG(FB,2)
-#define FB_CSCR2 FB_CSCR_REG(FB,2)
-#define FB_CSAR3 FB_CSAR_REG(FB,3)
-#define FB_CSMR3 FB_CSMR_REG(FB,3)
-#define FB_CSCR3 FB_CSCR_REG(FB,3)
-#define FB_CSAR4 FB_CSAR_REG(FB,4)
-#define FB_CSMR4 FB_CSMR_REG(FB,4)
-#define FB_CSCR4 FB_CSCR_REG(FB,4)
-#define FB_CSAR5 FB_CSAR_REG(FB,5)
-#define FB_CSMR5 FB_CSMR_REG(FB,5)
-#define FB_CSCR5 FB_CSCR_REG(FB,5)
-#define FB_CSPMCR FB_CSPMCR_REG(FB)
-
-/* FB - Register array accessors */
-#define FB_CSAR(index) FB_CSAR_REG(FB,index)
-#define FB_CSMR(index) FB_CSMR_REG(FB,index)
-#define FB_CSCR(index) FB_CSCR_REG(FB,index)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
- * @{
- */
-
-/** FMC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
- __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
- __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
- uint8_t RESERVED_0[244];
- __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
- __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
- __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
- __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
- uint8_t RESERVED_1[128];
- struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
- __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
- __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
- } SET[4][8];
-} FMC_Type, *FMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register accessors */
-#define FMC_PFAPR_REG(base) ((base)->PFAPR)
-#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
-#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
-#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
-#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
-#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
-#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
-#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
-#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Masks FMC Register Masks
- * @{
- */
-
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK 0x3u
-#define FMC_PFAPR_M0AP_SHIFT 0
-#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK 0xCu
-#define FMC_PFAPR_M1AP_SHIFT 2
-#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK 0x30u
-#define FMC_PFAPR_M2AP_SHIFT 4
-#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK 0xC0u
-#define FMC_PFAPR_M3AP_SHIFT 6
-#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M4AP_MASK 0x300u
-#define FMC_PFAPR_M4AP_SHIFT 8
-#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
-#define FMC_PFAPR_M5AP_MASK 0xC00u
-#define FMC_PFAPR_M5AP_SHIFT 10
-#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
-#define FMC_PFAPR_M6AP_MASK 0x3000u
-#define FMC_PFAPR_M6AP_SHIFT 12
-#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
-#define FMC_PFAPR_M7AP_MASK 0xC000u
-#define FMC_PFAPR_M7AP_SHIFT 14
-#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK 0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT 16
-#define FMC_PFAPR_M1PFD_MASK 0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT 17
-#define FMC_PFAPR_M2PFD_MASK 0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT 18
-#define FMC_PFAPR_M3PFD_MASK 0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT 19
-#define FMC_PFAPR_M4PFD_MASK 0x100000u
-#define FMC_PFAPR_M4PFD_SHIFT 20
-#define FMC_PFAPR_M5PFD_MASK 0x200000u
-#define FMC_PFAPR_M5PFD_SHIFT 21
-#define FMC_PFAPR_M6PFD_MASK 0x400000u
-#define FMC_PFAPR_M6PFD_SHIFT 22
-#define FMC_PFAPR_M7PFD_MASK 0x800000u
-#define FMC_PFAPR_M7PFD_SHIFT 23
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK 0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT 0
-#define FMC_PFB0CR_B0IPE_MASK 0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT 1
-#define FMC_PFB0CR_B0DPE_MASK 0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT 2
-#define FMC_PFB0CR_B0ICE_MASK 0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT 3
-#define FMC_PFB0CR_B0DCE_MASK 0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT 4
-#define FMC_PFB0CR_CRC_MASK 0xE0u
-#define FMC_PFB0CR_CRC_SHIFT 5
-#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK 0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT 17
-#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT 19
-#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT 20
-#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
-#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT 28
-#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* PFB1CR Bit Fields */
-#define FMC_PFB1CR_B1SEBE_MASK 0x1u
-#define FMC_PFB1CR_B1SEBE_SHIFT 0
-#define FMC_PFB1CR_B1IPE_MASK 0x2u
-#define FMC_PFB1CR_B1IPE_SHIFT 1
-#define FMC_PFB1CR_B1DPE_MASK 0x4u
-#define FMC_PFB1CR_B1DPE_SHIFT 2
-#define FMC_PFB1CR_B1ICE_MASK 0x8u
-#define FMC_PFB1CR_B1ICE_SHIFT 3
-#define FMC_PFB1CR_B1DCE_MASK 0x10u
-#define FMC_PFB1CR_B1DCE_SHIFT 4
-#define FMC_PFB1CR_B1MW_MASK 0x60000u
-#define FMC_PFB1CR_B1MW_SHIFT 17
-#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
-#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
-#define FMC_PFB1CR_B1RWSC_SHIFT 28
-#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
-/* TAGVDW0S Bit Fields */
-#define FMC_TAGVDW0S_valid_MASK 0x1u
-#define FMC_TAGVDW0S_valid_SHIFT 0
-#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW0S_tag_SHIFT 5
-#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
-/* TAGVDW1S Bit Fields */
-#define FMC_TAGVDW1S_valid_MASK 0x1u
-#define FMC_TAGVDW1S_valid_SHIFT 0
-#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW1S_tag_SHIFT 5
-#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
-/* TAGVDW2S Bit Fields */
-#define FMC_TAGVDW2S_valid_MASK 0x1u
-#define FMC_TAGVDW2S_valid_SHIFT 0
-#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW2S_tag_SHIFT 5
-#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
-/* TAGVDW3S Bit Fields */
-#define FMC_TAGVDW3S_valid_MASK 0x1u
-#define FMC_TAGVDW3S_valid_SHIFT 0
-#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW3S_tag_SHIFT 5
-#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
-/* DATA_U Bit Fields */
-#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_U_data_SHIFT 0
-#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
-/* DATA_L Bit Fields */
-#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_L_data_SHIFT 0
-#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Masks */
-
-
-/* FMC - Peripheral instance base addresses */
-/** Peripheral FMC base address */
-#define FMC_BASE (0x4001F000u)
-/** Peripheral FMC base pointer */
-#define FMC ((FMC_Type *)FMC_BASE)
-#define FMC_BASE_PTR (FMC)
-/** Array initializer of FMC peripheral base addresses */
-#define FMC_BASE_ADDRS { FMC_BASE }
-/** Array initializer of FMC peripheral base pointers */
-#define FMC_BASE_PTRS { FMC }
-
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register instance definitions */
-/* FMC */
-#define FMC_PFAPR FMC_PFAPR_REG(FMC)
-#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
-#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
-#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
-#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
-#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
-#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
-#define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
-#define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
-#define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
-#define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
-#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
-#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
-#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
-#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
-#define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
-#define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
-#define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
-#define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
-#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
-#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
-#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
-#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
-#define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
-#define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
-#define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
-#define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
-#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
-#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
-#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
-#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
-#define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
-#define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
-#define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
-#define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
-#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
-#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
-#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
-#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
-#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
-#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
-#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
-#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
-#define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
-#define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
-#define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
-#define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
-#define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
-#define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
-#define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
-#define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
-#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
-#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
-#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
-#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
-#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
-#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
-#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
-#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
-#define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
-#define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
-#define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
-#define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
-#define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
-#define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
-#define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
-#define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
-#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
-#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
-#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
-#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
-#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
-#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
-#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
-#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
-#define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
-#define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
-#define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
-#define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
-#define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
-#define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
-#define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
-#define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
-#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
-#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
-#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
-#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
-#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
-#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
-#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
-#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
-#define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
-#define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
-#define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
-#define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
-#define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
-#define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
-#define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
-#define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
-
-/* FMC - Register array accessors */
-#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
-#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
-#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
-#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
-#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
-#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
- * @{
- */
-
-/** FTFA - Register Layout Typedef */
-typedef struct {
- __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
- __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
- __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
- __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
- __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
- __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
- __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
- __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
- __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
- __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
- __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
- __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
- __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
- __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
- __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
- __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
- __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
- __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
- __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
- __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
- uint8_t RESERVED_0[4];
- __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
- __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
- __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
- __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
- __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
- __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
- __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
- __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
- __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
- __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
- __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
- __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
- __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
- __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
- __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
- __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
- __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
- uint8_t RESERVED_1[2];
- __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
-} FTFA_Type, *FTFA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTFA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
- * @{
- */
-
-
-/* FTFA - Register accessors */
-#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
-#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
-#define FTFA_FSEC_REG(base) ((base)->FSEC)
-#define FTFA_FOPT_REG(base) ((base)->FOPT)
-#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
-#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
-#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
-#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
-#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
-#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
-#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
-#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
-#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
-#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
-#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
-#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
-#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
-#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
-#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
-#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
-#define FTFA_XACCH3_REG(base) ((base)->XACCH3)
-#define FTFA_XACCH2_REG(base) ((base)->XACCH2)
-#define FTFA_XACCH1_REG(base) ((base)->XACCH1)
-#define FTFA_XACCH0_REG(base) ((base)->XACCH0)
-#define FTFA_XACCL3_REG(base) ((base)->XACCL3)
-#define FTFA_XACCL2_REG(base) ((base)->XACCL2)
-#define FTFA_XACCL1_REG(base) ((base)->XACCL1)
-#define FTFA_XACCL0_REG(base) ((base)->XACCL0)
-#define FTFA_SACCH3_REG(base) ((base)->SACCH3)
-#define FTFA_SACCH2_REG(base) ((base)->SACCH2)
-#define FTFA_SACCH1_REG(base) ((base)->SACCH1)
-#define FTFA_SACCH0_REG(base) ((base)->SACCH0)
-#define FTFA_SACCL3_REG(base) ((base)->SACCL3)
-#define FTFA_SACCL2_REG(base) ((base)->SACCL2)
-#define FTFA_SACCL1_REG(base) ((base)->SACCL1)
-#define FTFA_SACCL0_REG(base) ((base)->SACCL0)
-#define FTFA_FACSS_REG(base) ((base)->FACSS)
-#define FTFA_FACSN_REG(base) ((base)->FACSN)
-
-/*!
- * @}
- */ /* end of group FTFA_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFA Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Register_Masks FTFA Register Masks
- * @{
- */
-
-/* FSTAT Bit Fields */
-#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFA_FSTAT_MGSTAT0_SHIFT 0
-#define FTFA_FSTAT_FPVIOL_MASK 0x10u
-#define FTFA_FSTAT_FPVIOL_SHIFT 4
-#define FTFA_FSTAT_ACCERR_MASK 0x20u
-#define FTFA_FSTAT_ACCERR_SHIFT 5
-#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFA_FSTAT_RDCOLERR_SHIFT 6
-#define FTFA_FSTAT_CCIF_MASK 0x80u
-#define FTFA_FSTAT_CCIF_SHIFT 7
-/* FCNFG Bit Fields */
-#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFA_FCNFG_ERSSUSP_SHIFT 4
-#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFA_FCNFG_ERSAREQ_SHIFT 5
-#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFA_FCNFG_CCIE_MASK 0x80u
-#define FTFA_FCNFG_CCIE_SHIFT 7
-/* FSEC Bit Fields */
-#define FTFA_FSEC_SEC_MASK 0x3u
-#define FTFA_FSEC_SEC_SHIFT 0
-#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
-#define FTFA_FSEC_FSLACC_MASK 0xCu
-#define FTFA_FSEC_FSLACC_SHIFT 2
-#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
-#define FTFA_FSEC_MEEN_MASK 0x30u
-#define FTFA_FSEC_MEEN_SHIFT 4
-#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
-#define FTFA_FSEC_KEYEN_MASK 0xC0u
-#define FTFA_FSEC_KEYEN_SHIFT 6
-#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFA_FOPT_OPT_MASK 0xFFu
-#define FTFA_FOPT_OPT_SHIFT 0
-#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB3_CCOBn_SHIFT 0
-#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB2_CCOBn_SHIFT 0
-#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB1_CCOBn_SHIFT 0
-#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB0_CCOBn_SHIFT 0
-#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB7_CCOBn_SHIFT 0
-#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB6_CCOBn_SHIFT 0
-#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB5_CCOBn_SHIFT 0
-#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB4_CCOBn_SHIFT 0
-#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBB_CCOBn_SHIFT 0
-#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBA_CCOBn_SHIFT 0
-#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB9_CCOBn_SHIFT 0
-#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB8_CCOBn_SHIFT 0
-#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFA_FPROT3_PROT_MASK 0xFFu
-#define FTFA_FPROT3_PROT_SHIFT 0
-#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFA_FPROT2_PROT_MASK 0xFFu
-#define FTFA_FPROT2_PROT_SHIFT 0
-#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFA_FPROT1_PROT_MASK 0xFFu
-#define FTFA_FPROT1_PROT_SHIFT 0
-#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFA_FPROT0_PROT_MASK 0xFFu
-#define FTFA_FPROT0_PROT_SHIFT 0
-#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
-/* XACCH3 Bit Fields */
-#define FTFA_XACCH3_XA_MASK 0xFFu
-#define FTFA_XACCH3_XA_SHIFT 0
-#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
-/* XACCH2 Bit Fields */
-#define FTFA_XACCH2_XA_MASK 0xFFu
-#define FTFA_XACCH2_XA_SHIFT 0
-#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
-/* XACCH1 Bit Fields */
-#define FTFA_XACCH1_XA_MASK 0xFFu
-#define FTFA_XACCH1_XA_SHIFT 0
-#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
-/* XACCH0 Bit Fields */
-#define FTFA_XACCH0_XA_MASK 0xFFu
-#define FTFA_XACCH0_XA_SHIFT 0
-#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
-/* XACCL3 Bit Fields */
-#define FTFA_XACCL3_XA_MASK 0xFFu
-#define FTFA_XACCL3_XA_SHIFT 0
-#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
-/* XACCL2 Bit Fields */
-#define FTFA_XACCL2_XA_MASK 0xFFu
-#define FTFA_XACCL2_XA_SHIFT 0
-#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
-/* XACCL1 Bit Fields */
-#define FTFA_XACCL1_XA_MASK 0xFFu
-#define FTFA_XACCL1_XA_SHIFT 0
-#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
-/* XACCL0 Bit Fields */
-#define FTFA_XACCL0_XA_MASK 0xFFu
-#define FTFA_XACCL0_XA_SHIFT 0
-#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
-/* SACCH3 Bit Fields */
-#define FTFA_SACCH3_SA_MASK 0xFFu
-#define FTFA_SACCH3_SA_SHIFT 0
-#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
-/* SACCH2 Bit Fields */
-#define FTFA_SACCH2_SA_MASK 0xFFu
-#define FTFA_SACCH2_SA_SHIFT 0
-#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
-/* SACCH1 Bit Fields */
-#define FTFA_SACCH1_SA_MASK 0xFFu
-#define FTFA_SACCH1_SA_SHIFT 0
-#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
-/* SACCH0 Bit Fields */
-#define FTFA_SACCH0_SA_MASK 0xFFu
-#define FTFA_SACCH0_SA_SHIFT 0
-#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
-/* SACCL3 Bit Fields */
-#define FTFA_SACCL3_SA_MASK 0xFFu
-#define FTFA_SACCL3_SA_SHIFT 0
-#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
-/* SACCL2 Bit Fields */
-#define FTFA_SACCL2_SA_MASK 0xFFu
-#define FTFA_SACCL2_SA_SHIFT 0
-#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
-/* SACCL1 Bit Fields */
-#define FTFA_SACCL1_SA_MASK 0xFFu
-#define FTFA_SACCL1_SA_SHIFT 0
-#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
-/* SACCL0 Bit Fields */
-#define FTFA_SACCL0_SA_MASK 0xFFu
-#define FTFA_SACCL0_SA_SHIFT 0
-#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
-/* FACSS Bit Fields */
-#define FTFA_FACSS_SGSIZE_MASK 0xFFu
-#define FTFA_FACSS_SGSIZE_SHIFT 0
-#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
-/* FACSN Bit Fields */
-#define FTFA_FACSN_NUMSG_MASK 0xFFu
-#define FTFA_FACSN_NUMSG_SHIFT 0
-#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
-
-/*!
- * @}
- */ /* end of group FTFA_Register_Masks */
-
-
-/* FTFA - Peripheral instance base addresses */
-/** Peripheral FTFA base address */
-#define FTFA_BASE (0x40020000u)
-/** Peripheral FTFA base pointer */
-#define FTFA ((FTFA_Type *)FTFA_BASE)
-#define FTFA_BASE_PTR (FTFA)
-/** Array initializer of FTFA peripheral base addresses */
-#define FTFA_BASE_ADDRS { FTFA_BASE }
-/** Array initializer of FTFA peripheral base pointers */
-#define FTFA_BASE_PTRS { FTFA }
-/** Interrupt vectors for the FTFA peripheral type */
-#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
-#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- FTFA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
- * @{
- */
-
-
-/* FTFA - Register instance definitions */
-/* FTFA */
-#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
-#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
-#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
-#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
-#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
-#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
-#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
-#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
-#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
-#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
-#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
-#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
-#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
-#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
-#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
-#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
-#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
-#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
-#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
-#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
-#define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
-#define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
-#define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
-#define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
-#define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
-#define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
-#define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
-#define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
-#define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
-#define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
-#define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
-#define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
-#define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
-#define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
-#define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
-#define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
-#define FTFA_FACSS FTFA_FACSS_REG(FTFA)
-#define FTFA_FACSN FTFA_FACSN_REG(FTFA)
-
-/*!
- * @}
- */ /* end of group FTFA_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FTFA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
- * @{
- */
-
-/** FTM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
- __IO uint32_t CNT; /**< Counter, offset: 0x4 */
- __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
- struct { /* offset: 0xC, array step: 0x8 */
- __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
- __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
- } CONTROLS[8];
- __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
- __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
- __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
- __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
- __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
- __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
- __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
- __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
- __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
- __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
- __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
- __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
- __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
- __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
- __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
- __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
- __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
- __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
- __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
- __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type, *FTM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register accessors */
-#define FTM_SC_REG(base) ((base)->SC)
-#define FTM_CNT_REG(base) ((base)->CNT)
-#define FTM_MOD_REG(base) ((base)->MOD)
-#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
-#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
-#define FTM_CNTIN_REG(base) ((base)->CNTIN)
-#define FTM_STATUS_REG(base) ((base)->STATUS)
-#define FTM_MODE_REG(base) ((base)->MODE)
-#define FTM_SYNC_REG(base) ((base)->SYNC)
-#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
-#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
-#define FTM_COMBINE_REG(base) ((base)->COMBINE)
-#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
-#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
-#define FTM_POL_REG(base) ((base)->POL)
-#define FTM_FMS_REG(base) ((base)->FMS)
-#define FTM_FILTER_REG(base) ((base)->FILTER)
-#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
-#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
-#define FTM_CONF_REG(base) ((base)->CONF)
-#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
-#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
-#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
-#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
-#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FTM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Masks FTM Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK 0x7u
-#define FTM_SC_PS_SHIFT 0
-#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK 0x18u
-#define FTM_SC_CLKS_SHIFT 3
-#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK 0x20u
-#define FTM_SC_CPWMS_SHIFT 5
-#define FTM_SC_TOIE_MASK 0x40u
-#define FTM_SC_TOIE_SHIFT 6
-#define FTM_SC_TOF_MASK 0x80u
-#define FTM_SC_TOF_SHIFT 7
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK 0xFFFFu
-#define FTM_CNT_COUNT_SHIFT 0
-#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK 0xFFFFu
-#define FTM_MOD_MOD_SHIFT 0
-#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK 0x1u
-#define FTM_CnSC_DMA_SHIFT 0
-#define FTM_CnSC_ICRST_MASK 0x2u
-#define FTM_CnSC_ICRST_SHIFT 1
-#define FTM_CnSC_ELSA_MASK 0x4u
-#define FTM_CnSC_ELSA_SHIFT 2
-#define FTM_CnSC_ELSB_MASK 0x8u
-#define FTM_CnSC_ELSB_SHIFT 3
-#define FTM_CnSC_MSA_MASK 0x10u
-#define FTM_CnSC_MSA_SHIFT 4
-#define FTM_CnSC_MSB_MASK 0x20u
-#define FTM_CnSC_MSB_SHIFT 5
-#define FTM_CnSC_CHIE_MASK 0x40u
-#define FTM_CnSC_CHIE_SHIFT 6
-#define FTM_CnSC_CHF_MASK 0x80u
-#define FTM_CnSC_CHF_SHIFT 7
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK 0xFFFFu
-#define FTM_CnV_VAL_SHIFT 0
-#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK 0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT 0
-#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK 0x1u
-#define FTM_STATUS_CH0F_SHIFT 0
-#define FTM_STATUS_CH1F_MASK 0x2u
-#define FTM_STATUS_CH1F_SHIFT 1
-#define FTM_STATUS_CH2F_MASK 0x4u
-#define FTM_STATUS_CH2F_SHIFT 2
-#define FTM_STATUS_CH3F_MASK 0x8u
-#define FTM_STATUS_CH3F_SHIFT 3
-#define FTM_STATUS_CH4F_MASK 0x10u
-#define FTM_STATUS_CH4F_SHIFT 4
-#define FTM_STATUS_CH5F_MASK 0x20u
-#define FTM_STATUS_CH5F_SHIFT 5
-#define FTM_STATUS_CH6F_MASK 0x40u
-#define FTM_STATUS_CH6F_SHIFT 6
-#define FTM_STATUS_CH7F_MASK 0x80u
-#define FTM_STATUS_CH7F_SHIFT 7
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK 0x1u
-#define FTM_MODE_FTMEN_SHIFT 0
-#define FTM_MODE_INIT_MASK 0x2u
-#define FTM_MODE_INIT_SHIFT 1
-#define FTM_MODE_WPDIS_MASK 0x4u
-#define FTM_MODE_WPDIS_SHIFT 2
-#define FTM_MODE_PWMSYNC_MASK 0x8u
-#define FTM_MODE_PWMSYNC_SHIFT 3
-#define FTM_MODE_CAPTEST_MASK 0x10u
-#define FTM_MODE_CAPTEST_SHIFT 4
-#define FTM_MODE_FAULTM_MASK 0x60u
-#define FTM_MODE_FAULTM_SHIFT 5
-#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK 0x80u
-#define FTM_MODE_FAULTIE_SHIFT 7
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK 0x1u
-#define FTM_SYNC_CNTMIN_SHIFT 0
-#define FTM_SYNC_CNTMAX_MASK 0x2u
-#define FTM_SYNC_CNTMAX_SHIFT 1
-#define FTM_SYNC_REINIT_MASK 0x4u
-#define FTM_SYNC_REINIT_SHIFT 2
-#define FTM_SYNC_SYNCHOM_MASK 0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT 3
-#define FTM_SYNC_TRIG0_MASK 0x10u
-#define FTM_SYNC_TRIG0_SHIFT 4
-#define FTM_SYNC_TRIG1_MASK 0x20u
-#define FTM_SYNC_TRIG1_SHIFT 5
-#define FTM_SYNC_TRIG2_MASK 0x40u
-#define FTM_SYNC_TRIG2_SHIFT 6
-#define FTM_SYNC_SWSYNC_MASK 0x80u
-#define FTM_SYNC_SWSYNC_SHIFT 7
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK 0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT 0
-#define FTM_OUTINIT_CH1OI_MASK 0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT 1
-#define FTM_OUTINIT_CH2OI_MASK 0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT 2
-#define FTM_OUTINIT_CH3OI_MASK 0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT 3
-#define FTM_OUTINIT_CH4OI_MASK 0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT 4
-#define FTM_OUTINIT_CH5OI_MASK 0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT 5
-#define FTM_OUTINIT_CH6OI_MASK 0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT 6
-#define FTM_OUTINIT_CH7OI_MASK 0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT 7
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK 0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT 0
-#define FTM_OUTMASK_CH1OM_MASK 0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT 1
-#define FTM_OUTMASK_CH2OM_MASK 0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT 2
-#define FTM_OUTMASK_CH3OM_MASK 0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT 3
-#define FTM_OUTMASK_CH4OM_MASK 0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT 4
-#define FTM_OUTMASK_CH5OM_MASK 0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT 5
-#define FTM_OUTMASK_CH6OM_MASK 0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT 6
-#define FTM_OUTMASK_CH7OM_MASK 0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT 7
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK 0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT 0
-#define FTM_COMBINE_COMP0_MASK 0x2u
-#define FTM_COMBINE_COMP0_SHIFT 1
-#define FTM_COMBINE_DECAPEN0_MASK 0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT 2
-#define FTM_COMBINE_DECAP0_MASK 0x8u
-#define FTM_COMBINE_DECAP0_SHIFT 3
-#define FTM_COMBINE_DTEN0_MASK 0x10u
-#define FTM_COMBINE_DTEN0_SHIFT 4
-#define FTM_COMBINE_SYNCEN0_MASK 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT 5
-#define FTM_COMBINE_FAULTEN0_MASK 0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT 6
-#define FTM_COMBINE_COMBINE1_MASK 0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT 8
-#define FTM_COMBINE_COMP1_MASK 0x200u
-#define FTM_COMBINE_COMP1_SHIFT 9
-#define FTM_COMBINE_DECAPEN1_MASK 0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT 10
-#define FTM_COMBINE_DECAP1_MASK 0x800u
-#define FTM_COMBINE_DECAP1_SHIFT 11
-#define FTM_COMBINE_DTEN1_MASK 0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT 12
-#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT 13
-#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT 14
-#define FTM_COMBINE_COMBINE2_MASK 0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT 16
-#define FTM_COMBINE_COMP2_MASK 0x20000u
-#define FTM_COMBINE_COMP2_SHIFT 17
-#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT 18
-#define FTM_COMBINE_DECAP2_MASK 0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT 19
-#define FTM_COMBINE_DTEN2_MASK 0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT 20
-#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT 21
-#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT 22
-#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT 24
-#define FTM_COMBINE_COMP3_MASK 0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT 25
-#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT 26
-#define FTM_COMBINE_DECAP3_MASK 0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT 27
-#define FTM_COMBINE_DTEN3_MASK 0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT 28
-#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT 29
-#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT 30
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT 0
-#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK 0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT 6
-#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
-#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
-#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
-#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
-#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
-#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
-#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
-#define FTM_EXTTRIG_TRIGF_MASK 0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT 7
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK 0x1u
-#define FTM_POL_POL0_SHIFT 0
-#define FTM_POL_POL1_MASK 0x2u
-#define FTM_POL_POL1_SHIFT 1
-#define FTM_POL_POL2_MASK 0x4u
-#define FTM_POL_POL2_SHIFT 2
-#define FTM_POL_POL3_MASK 0x8u
-#define FTM_POL_POL3_SHIFT 3
-#define FTM_POL_POL4_MASK 0x10u
-#define FTM_POL_POL4_SHIFT 4
-#define FTM_POL_POL5_MASK 0x20u
-#define FTM_POL_POL5_SHIFT 5
-#define FTM_POL_POL6_MASK 0x40u
-#define FTM_POL_POL6_SHIFT 6
-#define FTM_POL_POL7_MASK 0x80u
-#define FTM_POL_POL7_SHIFT 7
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK 0x1u
-#define FTM_FMS_FAULTF0_SHIFT 0
-#define FTM_FMS_FAULTF1_MASK 0x2u
-#define FTM_FMS_FAULTF1_SHIFT 1
-#define FTM_FMS_FAULTF2_MASK 0x4u
-#define FTM_FMS_FAULTF2_SHIFT 2
-#define FTM_FMS_FAULTF3_MASK 0x8u
-#define FTM_FMS_FAULTF3_SHIFT 3
-#define FTM_FMS_FAULTIN_MASK 0x20u
-#define FTM_FMS_FAULTIN_SHIFT 5
-#define FTM_FMS_WPEN_MASK 0x40u
-#define FTM_FMS_WPEN_SHIFT 6
-#define FTM_FMS_FAULTF_MASK 0x80u
-#define FTM_FMS_FAULTF_SHIFT 7
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK 0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT 0
-#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK 0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT 4
-#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK 0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT 8
-#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK 0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT 12
-#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
-#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
-#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
-#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
-#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
-#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
-#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
-#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
-#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT 8
-#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK 0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT 0
-#define FTM_QDCTRL_TOFDIR_MASK 0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT 1
-#define FTM_QDCTRL_QUADIR_MASK 0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT 2
-#define FTM_QDCTRL_QUADMODE_MASK 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT 3
-#define FTM_QDCTRL_PHBPOL_MASK 0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT 4
-#define FTM_QDCTRL_PHAPOL_MASK 0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT 5
-#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
-#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK 0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT 0
-#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK 0xC0u
-#define FTM_CONF_BDMMODE_SHIFT 6
-#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK 0x200u
-#define FTM_CONF_GTBEEN_SHIFT 9
-#define FTM_CONF_GTBEOUT_MASK 0x400u
-#define FTM_CONF_GTBEOUT_SHIFT 10
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK 0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT 0
-#define FTM_FLTPOL_FLT1POL_MASK 0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT 1
-#define FTM_FLTPOL_FLT2POL_MASK 0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT 2
-#define FTM_FLTPOL_FLT3POL_MASK 0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT 3
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
-#define FTM_SYNCONF_CNTINC_MASK 0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT 2
-#define FTM_SYNCONF_INVC_MASK 0x10u
-#define FTM_SYNCONF_INVC_SHIFT 4
-#define FTM_SYNCONF_SWOC_MASK 0x20u
-#define FTM_SYNCONF_SWOC_SHIFT 5
-#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT 7
-#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
-#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT 9
-#define FTM_SYNCONF_SWOM_MASK 0x400u
-#define FTM_SYNCONF_SWOM_SHIFT 10
-#define FTM_SYNCONF_SWINVC_MASK 0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT 11
-#define FTM_SYNCONF_SWSOC_MASK 0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT 12
-#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
-#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT 17
-#define FTM_SYNCONF_HWOM_MASK 0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT 18
-#define FTM_SYNCONF_HWINVC_MASK 0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT 19
-#define FTM_SYNCONF_HWSOC_MASK 0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT 20
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK 0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT 0
-#define FTM_INVCTRL_INV1EN_MASK 0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT 1
-#define FTM_INVCTRL_INV2EN_MASK 0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT 2
-#define FTM_INVCTRL_INV3EN_MASK 0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT 3
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK 0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT 0
-#define FTM_SWOCTRL_CH1OC_MASK 0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT 1
-#define FTM_SWOCTRL_CH2OC_MASK 0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT 2
-#define FTM_SWOCTRL_CH3OC_MASK 0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT 3
-#define FTM_SWOCTRL_CH4OC_MASK 0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT 4
-#define FTM_SWOCTRL_CH5OC_MASK 0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT 5
-#define FTM_SWOCTRL_CH6OC_MASK 0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT 6
-#define FTM_SWOCTRL_CH7OC_MASK 0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT 7
-#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT 8
-#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT 9
-#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT 10
-#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT 11
-#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT 12
-#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT 13
-#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT 14
-#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT 15
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT 0
-#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT 1
-#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT 2
-#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT 3
-#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT 4
-#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT 5
-#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT 6
-#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT 7
-#define FTM_PWMLOAD_LDOK_MASK 0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT 9
-
-/*!
- * @}
- */ /* end of group FTM_Register_Masks */
-
-
-/* FTM - Peripheral instance base addresses */
-/** Peripheral FTM0 base address */
-#define FTM0_BASE (0x40038000u)
-/** Peripheral FTM0 base pointer */
-#define FTM0 ((FTM_Type *)FTM0_BASE)
-#define FTM0_BASE_PTR (FTM0)
-/** Peripheral FTM1 base address */
-#define FTM1_BASE (0x40039000u)
-/** Peripheral FTM1 base pointer */
-#define FTM1 ((FTM_Type *)FTM1_BASE)
-#define FTM1_BASE_PTR (FTM1)
-/** Peripheral FTM2 base address */
-#define FTM2_BASE (0x4003A000u)
-/** Peripheral FTM2 base pointer */
-#define FTM2 ((FTM_Type *)FTM2_BASE)
-#define FTM2_BASE_PTR (FTM2)
-/** Peripheral FTM3 base address */
-#define FTM3_BASE (0x40026000u)
-/** Peripheral FTM3 base pointer */
-#define FTM3 ((FTM_Type *)FTM3_BASE)
-#define FTM3_BASE_PTR (FTM3)
-/** Array initializer of FTM peripheral base addresses */
-#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
-/** Array initializer of FTM peripheral base pointers */
-#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
-/** Interrupt vectors for the FTM peripheral type */
-#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register instance definitions */
-/* FTM0 */
-#define FTM0_SC FTM_SC_REG(FTM0)
-#define FTM0_CNT FTM_CNT_REG(FTM0)
-#define FTM0_MOD FTM_MOD_REG(FTM0)
-#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
-#define FTM0_C0V FTM_CnV_REG(FTM0,0)
-#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
-#define FTM0_C1V FTM_CnV_REG(FTM0,1)
-#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
-#define FTM0_C2V FTM_CnV_REG(FTM0,2)
-#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
-#define FTM0_C3V FTM_CnV_REG(FTM0,3)
-#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
-#define FTM0_C4V FTM_CnV_REG(FTM0,4)
-#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
-#define FTM0_C5V FTM_CnV_REG(FTM0,5)
-#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
-#define FTM0_C6V FTM_CnV_REG(FTM0,6)
-#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
-#define FTM0_C7V FTM_CnV_REG(FTM0,7)
-#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
-#define FTM0_STATUS FTM_STATUS_REG(FTM0)
-#define FTM0_MODE FTM_MODE_REG(FTM0)
-#define FTM0_SYNC FTM_SYNC_REG(FTM0)
-#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
-#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
-#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
-#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
-#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
-#define FTM0_POL FTM_POL_REG(FTM0)
-#define FTM0_FMS FTM_FMS_REG(FTM0)
-#define FTM0_FILTER FTM_FILTER_REG(FTM0)
-#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
-#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
-#define FTM0_CONF FTM_CONF_REG(FTM0)
-#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
-#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
-#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
-#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
-#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
-/* FTM1 */
-#define FTM1_SC FTM_SC_REG(FTM1)
-#define FTM1_CNT FTM_CNT_REG(FTM1)
-#define FTM1_MOD FTM_MOD_REG(FTM1)
-#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
-#define FTM1_C0V FTM_CnV_REG(FTM1,0)
-#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
-#define FTM1_C1V FTM_CnV_REG(FTM1,1)
-#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
-#define FTM1_STATUS FTM_STATUS_REG(FTM1)
-#define FTM1_MODE FTM_MODE_REG(FTM1)
-#define FTM1_SYNC FTM_SYNC_REG(FTM1)
-#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
-#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
-#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
-#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
-#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
-#define FTM1_POL FTM_POL_REG(FTM1)
-#define FTM1_FMS FTM_FMS_REG(FTM1)
-#define FTM1_FILTER FTM_FILTER_REG(FTM1)
-#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
-#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
-#define FTM1_CONF FTM_CONF_REG(FTM1)
-#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
-#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
-#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
-#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
-#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
-/* FTM2 */
-#define FTM2_SC FTM_SC_REG(FTM2)
-#define FTM2_CNT FTM_CNT_REG(FTM2)
-#define FTM2_MOD FTM_MOD_REG(FTM2)
-#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
-#define FTM2_C0V FTM_CnV_REG(FTM2,0)
-#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
-#define FTM2_C1V FTM_CnV_REG(FTM2,1)
-#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
-#define FTM2_STATUS FTM_STATUS_REG(FTM2)
-#define FTM2_MODE FTM_MODE_REG(FTM2)
-#define FTM2_SYNC FTM_SYNC_REG(FTM2)
-#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
-#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
-#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
-#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
-#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
-#define FTM2_POL FTM_POL_REG(FTM2)
-#define FTM2_FMS FTM_FMS_REG(FTM2)
-#define FTM2_FILTER FTM_FILTER_REG(FTM2)
-#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
-#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
-#define FTM2_CONF FTM_CONF_REG(FTM2)
-#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
-#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
-#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
-#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
-#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
-/* FTM3 */
-#define FTM3_SC FTM_SC_REG(FTM3)
-#define FTM3_CNT FTM_CNT_REG(FTM3)
-#define FTM3_MOD FTM_MOD_REG(FTM3)
-#define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
-#define FTM3_C0V FTM_CnV_REG(FTM3,0)
-#define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
-#define FTM3_C1V FTM_CnV_REG(FTM3,1)
-#define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
-#define FTM3_C2V FTM_CnV_REG(FTM3,2)
-#define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
-#define FTM3_C3V FTM_CnV_REG(FTM3,3)
-#define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
-#define FTM3_C4V FTM_CnV_REG(FTM3,4)
-#define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
-#define FTM3_C5V FTM_CnV_REG(FTM3,5)
-#define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
-#define FTM3_C6V FTM_CnV_REG(FTM3,6)
-#define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
-#define FTM3_C7V FTM_CnV_REG(FTM3,7)
-#define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
-#define FTM3_STATUS FTM_STATUS_REG(FTM3)
-#define FTM3_MODE FTM_MODE_REG(FTM3)
-#define FTM3_SYNC FTM_SYNC_REG(FTM3)
-#define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
-#define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
-#define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
-#define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
-#define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
-#define FTM3_POL FTM_POL_REG(FTM3)
-#define FTM3_FMS FTM_FMS_REG(FTM3)
-#define FTM3_FILTER FTM_FILTER_REG(FTM3)
-#define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
-#define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
-#define FTM3_CONF FTM_CONF_REG(FTM3)
-#define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
-#define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
-#define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
-#define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
-#define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
-
-/* FTM - Register array accessors */
-#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
-#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
-#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
-#define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
-#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
-#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
-#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
-#define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FTM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type, *GPIO_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register accessors */
-#define GPIO_PDOR_REG(base) ((base)->PDOR)
-#define GPIO_PSOR_REG(base) ((base)->PSOR)
-#define GPIO_PCOR_REG(base) ((base)->PCOR)
-#define GPIO_PTOR_REG(base) ((base)->PTOR)
-#define GPIO_PDIR_REG(base) ((base)->PDIR)
-#define GPIO_PDDR_REG(base) ((base)->PDDR)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-#define PTA_BASE_PTR (PTA)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-#define PTB_BASE_PTR (PTB)
-/** Peripheral PTC base address */
-#define PTC_BASE (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC ((GPIO_Type *)PTC_BASE)
-#define PTC_BASE_PTR (PTC)
-/** Peripheral PTD base address */
-#define PTD_BASE (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD ((GPIO_Type *)PTD_BASE)
-#define PTD_BASE_PTR (PTD)
-/** Peripheral PTE base address */
-#define PTE_BASE (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE ((GPIO_Type *)PTE_BASE)
-#define PTE_BASE_PTR (PTE)
-/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
-
-/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register instance definitions */
-/* PTA */
-#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
-#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
-#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
-#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
-#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
-#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
-/* PTB */
-#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
-#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
-#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
-#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
-#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
-#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
-/* PTC */
-#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
-#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
-#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
-#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
-#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
-#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
-/* PTD */
-#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
-#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
-#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
-#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
-#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
-#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
-/* PTE */
-#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
-#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
-#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
-#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
-#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
-#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
- __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
- __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
- __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
- __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
- __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
- __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
- __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
- __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
- __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
- __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
- __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
- __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type, *I2C_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register accessors */
-#define I2C_A1_REG(base) ((base)->A1)
-#define I2C_F_REG(base) ((base)->F)
-#define I2C_C1_REG(base) ((base)->C1)
-#define I2C_S_REG(base) ((base)->S)
-#define I2C_D_REG(base) ((base)->D)
-#define I2C_C2_REG(base) ((base)->C2)
-#define I2C_FLT_REG(base) ((base)->FLT)
-#define I2C_RA_REG(base) ((base)->RA)
-#define I2C_SMB_REG(base) ((base)->SMB)
-#define I2C_A2_REG(base) ((base)->A2)
-#define I2C_SLTH_REG(base) ((base)->SLTH)
-#define I2C_SLTL_REG(base) ((base)->SLTL)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0xFu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STARTF_MASK 0x10u
-#define I2C_FLT_STARTF_SHIFT 4
-#define I2C_FLT_SSIE_MASK 0x20u
-#define I2C_FLT_SSIE_SHIFT 5
-#define I2C_FLT_STOPF_MASK 0x40u
-#define I2C_FLT_STOPF_SHIFT 6
-#define I2C_FLT_SHEN_MASK 0x80u
-#define I2C_FLT_SHEN_SHIFT 7
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40066000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-#define I2C0_BASE_PTR (I2C0)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE (0x40067000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1 ((I2C_Type *)I2C1_BASE)
-#define I2C1_BASE_PTR (I2C1)
-/** Array initializer of I2C peripheral base addresses */
-#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASE_PTRS { I2C0, I2C1 }
-/** Interrupt vectors for the I2C peripheral type */
-#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register instance definitions */
-/* I2C0 */
-#define I2C0_A1 I2C_A1_REG(I2C0)
-#define I2C0_F I2C_F_REG(I2C0)
-#define I2C0_C1 I2C_C1_REG(I2C0)
-#define I2C0_S I2C_S_REG(I2C0)
-#define I2C0_D I2C_D_REG(I2C0)
-#define I2C0_C2 I2C_C2_REG(I2C0)
-#define I2C0_FLT I2C_FLT_REG(I2C0)
-#define I2C0_RA I2C_RA_REG(I2C0)
-#define I2C0_SMB I2C_SMB_REG(I2C0)
-#define I2C0_A2 I2C_A2_REG(I2C0)
-#define I2C0_SLTH I2C_SLTH_REG(I2C0)
-#define I2C0_SLTL I2C_SLTL_REG(I2C0)
-/* I2C1 */
-#define I2C1_A1 I2C_A1_REG(I2C1)
-#define I2C1_F I2C_F_REG(I2C1)
-#define I2C1_C1 I2C_C1_REG(I2C1)
-#define I2C1_S I2C_S_REG(I2C1)
-#define I2C1_D I2C_D_REG(I2C1)
-#define I2C1_C2 I2C_C2_REG(I2C1)
-#define I2C1_FLT I2C_FLT_REG(I2C1)
-#define I2C1_RA I2C_RA_REG(I2C1)
-#define I2C1_SMB I2C_SMB_REG(I2C1)
-#define I2C1_A2 I2C_A2_REG(I2C1)
-#define I2C1_SLTH I2C_SLTH_REG(I2C1)
-#define I2C1_SLTL I2C_SLTL_REG(I2C1)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2S Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
- * @{
- */
-
-/** I2S - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
- __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
- __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
- __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
- __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
- __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
- uint8_t RESERVED_0[8];
- __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[28];
- __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_2[28];
- __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
- uint8_t RESERVED_3[28];
- __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
- __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
- __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
- __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
- __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
- __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
- uint8_t RESERVED_4[8];
- __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
- uint8_t RESERVED_5[28];
- __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_6[28];
- __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
- uint8_t RESERVED_7[28];
- __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
- __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
-} I2S_Type, *I2S_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register accessors */
-#define I2S_TCSR_REG(base) ((base)->TCSR)
-#define I2S_TCR1_REG(base) ((base)->TCR1)
-#define I2S_TCR2_REG(base) ((base)->TCR2)
-#define I2S_TCR3_REG(base) ((base)->TCR3)
-#define I2S_TCR4_REG(base) ((base)->TCR4)
-#define I2S_TCR5_REG(base) ((base)->TCR5)
-#define I2S_TDR_REG(base,index) ((base)->TDR[index])
-#define I2S_TFR_REG(base,index) ((base)->TFR[index])
-#define I2S_TMR_REG(base) ((base)->TMR)
-#define I2S_RCSR_REG(base) ((base)->RCSR)
-#define I2S_RCR1_REG(base) ((base)->RCR1)
-#define I2S_RCR2_REG(base) ((base)->RCR2)
-#define I2S_RCR3_REG(base) ((base)->RCR3)
-#define I2S_RCR4_REG(base) ((base)->RCR4)
-#define I2S_RCR5_REG(base) ((base)->RCR5)
-#define I2S_RDR_REG(base,index) ((base)->RDR[index])
-#define I2S_RFR_REG(base,index) ((base)->RFR[index])
-#define I2S_RMR_REG(base) ((base)->RMR)
-#define I2S_MCR_REG(base) ((base)->MCR)
-#define I2S_MDR_REG(base) ((base)->MDR)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- I2S Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Masks I2S Register Masks
- * @{
- */
-
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK 0x1u
-#define I2S_TCSR_FRDE_SHIFT 0
-#define I2S_TCSR_FWDE_MASK 0x2u
-#define I2S_TCSR_FWDE_SHIFT 1
-#define I2S_TCSR_FRIE_MASK 0x100u
-#define I2S_TCSR_FRIE_SHIFT 8
-#define I2S_TCSR_FWIE_MASK 0x200u
-#define I2S_TCSR_FWIE_SHIFT 9
-#define I2S_TCSR_FEIE_MASK 0x400u
-#define I2S_TCSR_FEIE_SHIFT 10
-#define I2S_TCSR_SEIE_MASK 0x800u
-#define I2S_TCSR_SEIE_SHIFT 11
-#define I2S_TCSR_WSIE_MASK 0x1000u
-#define I2S_TCSR_WSIE_SHIFT 12
-#define I2S_TCSR_FRF_MASK 0x10000u
-#define I2S_TCSR_FRF_SHIFT 16
-#define I2S_TCSR_FWF_MASK 0x20000u
-#define I2S_TCSR_FWF_SHIFT 17
-#define I2S_TCSR_FEF_MASK 0x40000u
-#define I2S_TCSR_FEF_SHIFT 18
-#define I2S_TCSR_SEF_MASK 0x80000u
-#define I2S_TCSR_SEF_SHIFT 19
-#define I2S_TCSR_WSF_MASK 0x100000u
-#define I2S_TCSR_WSF_SHIFT 20
-#define I2S_TCSR_SR_MASK 0x1000000u
-#define I2S_TCSR_SR_SHIFT 24
-#define I2S_TCSR_FR_MASK 0x2000000u
-#define I2S_TCSR_FR_SHIFT 25
-#define I2S_TCSR_BCE_MASK 0x10000000u
-#define I2S_TCSR_BCE_SHIFT 28
-#define I2S_TCSR_DBGE_MASK 0x20000000u
-#define I2S_TCSR_DBGE_SHIFT 29
-#define I2S_TCSR_STOPE_MASK 0x40000000u
-#define I2S_TCSR_STOPE_SHIFT 30
-#define I2S_TCSR_TE_MASK 0x80000000u
-#define I2S_TCSR_TE_SHIFT 31
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK 0x7u
-#define I2S_TCR1_TFW_SHIFT 0
-#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK 0xFFu
-#define I2S_TCR2_DIV_SHIFT 0
-#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK 0x1000000u
-#define I2S_TCR2_BCD_SHIFT 24
-#define I2S_TCR2_BCP_MASK 0x2000000u
-#define I2S_TCR2_BCP_SHIFT 25
-#define I2S_TCR2_MSEL_MASK 0xC000000u
-#define I2S_TCR2_MSEL_SHIFT 26
-#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK 0x10000000u
-#define I2S_TCR2_BCI_SHIFT 28
-#define I2S_TCR2_BCS_MASK 0x20000000u
-#define I2S_TCR2_BCS_SHIFT 29
-#define I2S_TCR2_SYNC_MASK 0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT 30
-#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK 0xFu
-#define I2S_TCR3_WDFL_SHIFT 0
-#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK 0x10000u
-#define I2S_TCR3_TCE_SHIFT 16
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK 0x1u
-#define I2S_TCR4_FSD_SHIFT 0
-#define I2S_TCR4_FSP_MASK 0x2u
-#define I2S_TCR4_FSP_SHIFT 1
-#define I2S_TCR4_ONDEM_MASK 0x4u
-#define I2S_TCR4_ONDEM_SHIFT 2
-#define I2S_TCR4_FSE_MASK 0x8u
-#define I2S_TCR4_FSE_SHIFT 3
-#define I2S_TCR4_MF_MASK 0x10u
-#define I2S_TCR4_MF_SHIFT 4
-#define I2S_TCR4_SYWD_MASK 0x1F00u
-#define I2S_TCR4_SYWD_SHIFT 8
-#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK 0xF0000u
-#define I2S_TCR4_FRSZ_SHIFT 16
-#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-#define I2S_TCR4_FPACK_MASK 0x3000000u
-#define I2S_TCR4_FPACK_SHIFT 24
-#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
-#define I2S_TCR4_FCONT_MASK 0x10000000u
-#define I2S_TCR4_FCONT_SHIFT 28
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK 0x1F00u
-#define I2S_TCR5_FBT_SHIFT 8
-#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK 0x1F0000u
-#define I2S_TCR5_W0W_SHIFT 16
-#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK 0x1F000000u
-#define I2S_TCR5_WNW_SHIFT 24
-#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT 0
-#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK 0xFu
-#define I2S_TFR_RFP_SHIFT 0
-#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK 0xF0000u
-#define I2S_TFR_WFP_SHIFT 16
-#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK 0xFFFFu
-#define I2S_TMR_TWM_SHIFT 0
-#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK 0x1u
-#define I2S_RCSR_FRDE_SHIFT 0
-#define I2S_RCSR_FWDE_MASK 0x2u
-#define I2S_RCSR_FWDE_SHIFT 1
-#define I2S_RCSR_FRIE_MASK 0x100u
-#define I2S_RCSR_FRIE_SHIFT 8
-#define I2S_RCSR_FWIE_MASK 0x200u
-#define I2S_RCSR_FWIE_SHIFT 9
-#define I2S_RCSR_FEIE_MASK 0x400u
-#define I2S_RCSR_FEIE_SHIFT 10
-#define I2S_RCSR_SEIE_MASK 0x800u
-#define I2S_RCSR_SEIE_SHIFT 11
-#define I2S_RCSR_WSIE_MASK 0x1000u
-#define I2S_RCSR_WSIE_SHIFT 12
-#define I2S_RCSR_FRF_MASK 0x10000u
-#define I2S_RCSR_FRF_SHIFT 16
-#define I2S_RCSR_FWF_MASK 0x20000u
-#define I2S_RCSR_FWF_SHIFT 17
-#define I2S_RCSR_FEF_MASK 0x40000u
-#define I2S_RCSR_FEF_SHIFT 18
-#define I2S_RCSR_SEF_MASK 0x80000u
-#define I2S_RCSR_SEF_SHIFT 19
-#define I2S_RCSR_WSF_MASK 0x100000u
-#define I2S_RCSR_WSF_SHIFT 20
-#define I2S_RCSR_SR_MASK 0x1000000u
-#define I2S_RCSR_SR_SHIFT 24
-#define I2S_RCSR_FR_MASK 0x2000000u
-#define I2S_RCSR_FR_SHIFT 25
-#define I2S_RCSR_BCE_MASK 0x10000000u
-#define I2S_RCSR_BCE_SHIFT 28
-#define I2S_RCSR_DBGE_MASK 0x20000000u
-#define I2S_RCSR_DBGE_SHIFT 29
-#define I2S_RCSR_STOPE_MASK 0x40000000u
-#define I2S_RCSR_STOPE_SHIFT 30
-#define I2S_RCSR_RE_MASK 0x80000000u
-#define I2S_RCSR_RE_SHIFT 31
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK 0x7u
-#define I2S_RCR1_RFW_SHIFT 0
-#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK 0xFFu
-#define I2S_RCR2_DIV_SHIFT 0
-#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK 0x1000000u
-#define I2S_RCR2_BCD_SHIFT 24
-#define I2S_RCR2_BCP_MASK 0x2000000u
-#define I2S_RCR2_BCP_SHIFT 25
-#define I2S_RCR2_MSEL_MASK 0xC000000u
-#define I2S_RCR2_MSEL_SHIFT 26
-#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK 0x10000000u
-#define I2S_RCR2_BCI_SHIFT 28
-#define I2S_RCR2_BCS_MASK 0x20000000u
-#define I2S_RCR2_BCS_SHIFT 29
-#define I2S_RCR2_SYNC_MASK 0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT 30
-#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK 0xFu
-#define I2S_RCR3_WDFL_SHIFT 0
-#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK 0x10000u
-#define I2S_RCR3_RCE_SHIFT 16
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK 0x1u
-#define I2S_RCR4_FSD_SHIFT 0
-#define I2S_RCR4_FSP_MASK 0x2u
-#define I2S_RCR4_FSP_SHIFT 1
-#define I2S_RCR4_ONDEM_MASK 0x4u
-#define I2S_RCR4_ONDEM_SHIFT 2
-#define I2S_RCR4_FSE_MASK 0x8u
-#define I2S_RCR4_FSE_SHIFT 3
-#define I2S_RCR4_MF_MASK 0x10u
-#define I2S_RCR4_MF_SHIFT 4
-#define I2S_RCR4_SYWD_MASK 0x1F00u
-#define I2S_RCR4_SYWD_SHIFT 8
-#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK 0xF0000u
-#define I2S_RCR4_FRSZ_SHIFT 16
-#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-#define I2S_RCR4_FPACK_MASK 0x3000000u
-#define I2S_RCR4_FPACK_SHIFT 24
-#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
-#define I2S_RCR4_FCONT_MASK 0x10000000u
-#define I2S_RCR4_FCONT_SHIFT 28
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK 0x1F00u
-#define I2S_RCR5_FBT_SHIFT 8
-#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK 0x1F0000u
-#define I2S_RCR5_W0W_SHIFT 16
-#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK 0x1F000000u
-#define I2S_RCR5_WNW_SHIFT 24
-#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT 0
-#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK 0xFu
-#define I2S_RFR_RFP_SHIFT 0
-#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK 0xF0000u
-#define I2S_RFR_WFP_SHIFT 16
-#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK 0xFFFFu
-#define I2S_RMR_RWM_SHIFT 0
-#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK 0x3000000u
-#define I2S_MCR_MICS_SHIFT 24
-#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK 0x40000000u
-#define I2S_MCR_MOE_SHIFT 30
-#define I2S_MCR_DUF_MASK 0x80000000u
-#define I2S_MCR_DUF_SHIFT 31
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK 0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT 0
-#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK 0xFF000u
-#define I2S_MDR_FRACT_SHIFT 12
-#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Masks */
-
-
-/* I2S - Peripheral instance base addresses */
-/** Peripheral I2S0 base address */
-#define I2S0_BASE (0x4002F000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0 ((I2S_Type *)I2S0_BASE)
-#define I2S0_BASE_PTR (I2S0)
-/** Array initializer of I2S peripheral base addresses */
-#define I2S_BASE_ADDRS { I2S0_BASE }
-/** Array initializer of I2S peripheral base pointers */
-#define I2S_BASE_PTRS { I2S0 }
-/** Interrupt vectors for the I2S peripheral type */
-#define I2S_RX_IRQS { I2S0_Rx_IRQn }
-#define I2S_TX_IRQS { I2S0_Tx_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register instance definitions */
-/* I2S0 */
-#define I2S0_TCSR I2S_TCSR_REG(I2S0)
-#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
-#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
-#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
-#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
-#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
-#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
-#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
-#define I2S0_TMR I2S_TMR_REG(I2S0)
-#define I2S0_RCSR I2S_RCSR_REG(I2S0)
-#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
-#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
-#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
-#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
-#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
-#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
-#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
-#define I2S0_RMR I2S_RMR_REG(I2S0)
-#define I2S0_MCR I2S_MCR_REG(I2S0)
-#define I2S0_MDR I2S_MDR_REG(I2S0)
-
-/* I2S - Register array accessors */
-#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
-#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
-#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
-#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group I2S_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
- * @{
- */
-
-/** LLWU - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
- __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
- __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
- __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
- __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
- __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
- __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
- __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
- __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
- __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
-} LLWU_Type, *LLWU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register accessors */
-#define LLWU_PE1_REG(base) ((base)->PE1)
-#define LLWU_PE2_REG(base) ((base)->PE2)
-#define LLWU_PE3_REG(base) ((base)->PE3)
-#define LLWU_PE4_REG(base) ((base)->PE4)
-#define LLWU_ME_REG(base) ((base)->ME)
-#define LLWU_F1_REG(base) ((base)->F1)
-#define LLWU_F2_REG(base) ((base)->F2)
-#define LLWU_F3_REG(base) ((base)->F3)
-#define LLWU_FILT1_REG(base) ((base)->FILT1)
-#define LLWU_FILT2_REG(base) ((base)->FILT2)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Masks LLWU Register Masks
- * @{
- */
-
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Masks */
-
-
-/* LLWU - Peripheral instance base addresses */
-/** Peripheral LLWU base address */
-#define LLWU_BASE (0x4007C000u)
-/** Peripheral LLWU base pointer */
-#define LLWU ((LLWU_Type *)LLWU_BASE)
-#define LLWU_BASE_PTR (LLWU)
-/** Array initializer of LLWU peripheral base addresses */
-#define LLWU_BASE_ADDRS { LLWU_BASE }
-/** Array initializer of LLWU peripheral base pointers */
-#define LLWU_BASE_PTRS { LLWU }
-/** Interrupt vectors for the LLWU peripheral type */
-#define LLWU_IRQS { LLW_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register instance definitions */
-/* LLWU */
-#define LLWU_PE1 LLWU_PE1_REG(LLWU)
-#define LLWU_PE2 LLWU_PE2_REG(LLWU)
-#define LLWU_PE3 LLWU_PE3_REG(LLWU)
-#define LLWU_PE4 LLWU_PE4_REG(LLWU)
-#define LLWU_ME LLWU_ME_REG(LLWU)
-#define LLWU_F1 LLWU_F1_REG(LLWU)
-#define LLWU_F2 LLWU_F2_REG(LLWU)
-#define LLWU_F3 LLWU_F3_REG(LLWU)
-#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
-#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group LLWU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
- * @{
- */
-
-/** LPTMR - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
- __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
- __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
- __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type, *LPTMR_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register accessors */
-#define LPTMR_CSR_REG(base) ((base)->CSR)
-#define LPTMR_PSR_REG(base) ((base)->PSR)
-#define LPTMR_CMR_REG(base) ((base)->CMR)
-#define LPTMR_CNR_REG(base) ((base)->CNR)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
- * @{
- */
-
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Masks */
-
-
-/* LPTMR - Peripheral instance base addresses */
-/** Peripheral LPTMR0 base address */
-#define LPTMR0_BASE (0x40040000u)
-/** Peripheral LPTMR0 base pointer */
-#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-#define LPTMR0_BASE_PTR (LPTMR0)
-/** Array initializer of LPTMR peripheral base addresses */
-#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
-/** Array initializer of LPTMR peripheral base pointers */
-#define LPTMR_BASE_PTRS { LPTMR0 }
-/** Interrupt vectors for the LPTMR peripheral type */
-#define LPTMR_IRQS { LPTimer_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register instance definitions */
-/* LPTMR0 */
-#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
-#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
-#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
-#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group LPTMR_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LPUART Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
- * @{
- */
-
-/** LPUART - Register Layout Typedef */
-typedef struct {
- __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
- __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
- __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
- __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
- __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
- __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
-} LPUART_Type, *LPUART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPUART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
- * @{
- */
-
-
-/* LPUART - Register accessors */
-#define LPUART_BAUD_REG(base) ((base)->BAUD)
-#define LPUART_STAT_REG(base) ((base)->STAT)
-#define LPUART_CTRL_REG(base) ((base)->CTRL)
-#define LPUART_DATA_REG(base) ((base)->DATA)
-#define LPUART_MATCH_REG(base) ((base)->MATCH)
-#define LPUART_MODIR_REG(base) ((base)->MODIR)
-
-/*!
- * @}
- */ /* end of group LPUART_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- LPUART Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Register_Masks LPUART Register Masks
- * @{
- */
-
-/* BAUD Bit Fields */
-#define LPUART_BAUD_SBR_MASK 0x1FFFu
-#define LPUART_BAUD_SBR_SHIFT 0
-#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
-#define LPUART_BAUD_SBNS_MASK 0x2000u
-#define LPUART_BAUD_SBNS_SHIFT 13
-#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
-#define LPUART_BAUD_RXEDGIE_SHIFT 14
-#define LPUART_BAUD_LBKDIE_MASK 0x8000u
-#define LPUART_BAUD_LBKDIE_SHIFT 15
-#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
-#define LPUART_BAUD_RESYNCDIS_SHIFT 16
-#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
-#define LPUART_BAUD_BOTHEDGE_SHIFT 17
-#define LPUART_BAUD_MATCFG_MASK 0xC0000u
-#define LPUART_BAUD_MATCFG_SHIFT 18
-#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
-#define LPUART_BAUD_RDMAE_MASK 0x200000u
-#define LPUART_BAUD_RDMAE_SHIFT 21
-#define LPUART_BAUD_TDMAE_MASK 0x800000u
-#define LPUART_BAUD_TDMAE_SHIFT 23
-#define LPUART_BAUD_OSR_MASK 0x1F000000u
-#define LPUART_BAUD_OSR_SHIFT 24
-#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
-#define LPUART_BAUD_M10_MASK 0x20000000u
-#define LPUART_BAUD_M10_SHIFT 29
-#define LPUART_BAUD_MAEN2_MASK 0x40000000u
-#define LPUART_BAUD_MAEN2_SHIFT 30
-#define LPUART_BAUD_MAEN1_MASK 0x80000000u
-#define LPUART_BAUD_MAEN1_SHIFT 31
-/* STAT Bit Fields */
-#define LPUART_STAT_MA2F_MASK 0x4000u
-#define LPUART_STAT_MA2F_SHIFT 14
-#define LPUART_STAT_MA1F_MASK 0x8000u
-#define LPUART_STAT_MA1F_SHIFT 15
-#define LPUART_STAT_PF_MASK 0x10000u
-#define LPUART_STAT_PF_SHIFT 16
-#define LPUART_STAT_FE_MASK 0x20000u
-#define LPUART_STAT_FE_SHIFT 17
-#define LPUART_STAT_NF_MASK 0x40000u
-#define LPUART_STAT_NF_SHIFT 18
-#define LPUART_STAT_OR_MASK 0x80000u
-#define LPUART_STAT_OR_SHIFT 19
-#define LPUART_STAT_IDLE_MASK 0x100000u
-#define LPUART_STAT_IDLE_SHIFT 20
-#define LPUART_STAT_RDRF_MASK 0x200000u
-#define LPUART_STAT_RDRF_SHIFT 21
-#define LPUART_STAT_TC_MASK 0x400000u
-#define LPUART_STAT_TC_SHIFT 22
-#define LPUART_STAT_TDRE_MASK 0x800000u
-#define LPUART_STAT_TDRE_SHIFT 23
-#define LPUART_STAT_RAF_MASK 0x1000000u
-#define LPUART_STAT_RAF_SHIFT 24
-#define LPUART_STAT_LBKDE_MASK 0x2000000u
-#define LPUART_STAT_LBKDE_SHIFT 25
-#define LPUART_STAT_BRK13_MASK 0x4000000u
-#define LPUART_STAT_BRK13_SHIFT 26
-#define LPUART_STAT_RWUID_MASK 0x8000000u
-#define LPUART_STAT_RWUID_SHIFT 27
-#define LPUART_STAT_RXINV_MASK 0x10000000u
-#define LPUART_STAT_RXINV_SHIFT 28
-#define LPUART_STAT_MSBF_MASK 0x20000000u
-#define LPUART_STAT_MSBF_SHIFT 29
-#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
-#define LPUART_STAT_RXEDGIF_SHIFT 30
-#define LPUART_STAT_LBKDIF_MASK 0x80000000u
-#define LPUART_STAT_LBKDIF_SHIFT 31
-/* CTRL Bit Fields */
-#define LPUART_CTRL_PT_MASK 0x1u
-#define LPUART_CTRL_PT_SHIFT 0
-#define LPUART_CTRL_PE_MASK 0x2u
-#define LPUART_CTRL_PE_SHIFT 1
-#define LPUART_CTRL_ILT_MASK 0x4u
-#define LPUART_CTRL_ILT_SHIFT 2
-#define LPUART_CTRL_WAKE_MASK 0x8u
-#define LPUART_CTRL_WAKE_SHIFT 3
-#define LPUART_CTRL_M_MASK 0x10u
-#define LPUART_CTRL_M_SHIFT 4
-#define LPUART_CTRL_RSRC_MASK 0x20u
-#define LPUART_CTRL_RSRC_SHIFT 5
-#define LPUART_CTRL_DOZEEN_MASK 0x40u
-#define LPUART_CTRL_DOZEEN_SHIFT 6
-#define LPUART_CTRL_LOOPS_MASK 0x80u
-#define LPUART_CTRL_LOOPS_SHIFT 7
-#define LPUART_CTRL_IDLECFG_MASK 0x700u
-#define LPUART_CTRL_IDLECFG_SHIFT 8
-#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
-#define LPUART_CTRL_MA2IE_MASK 0x4000u
-#define LPUART_CTRL_MA2IE_SHIFT 14
-#define LPUART_CTRL_MA1IE_MASK 0x8000u
-#define LPUART_CTRL_MA1IE_SHIFT 15
-#define LPUART_CTRL_SBK_MASK 0x10000u
-#define LPUART_CTRL_SBK_SHIFT 16
-#define LPUART_CTRL_RWU_MASK 0x20000u
-#define LPUART_CTRL_RWU_SHIFT 17
-#define LPUART_CTRL_RE_MASK 0x40000u
-#define LPUART_CTRL_RE_SHIFT 18
-#define LPUART_CTRL_TE_MASK 0x80000u
-#define LPUART_CTRL_TE_SHIFT 19
-#define LPUART_CTRL_ILIE_MASK 0x100000u
-#define LPUART_CTRL_ILIE_SHIFT 20
-#define LPUART_CTRL_RIE_MASK 0x200000u
-#define LPUART_CTRL_RIE_SHIFT 21
-#define LPUART_CTRL_TCIE_MASK 0x400000u
-#define LPUART_CTRL_TCIE_SHIFT 22
-#define LPUART_CTRL_TIE_MASK 0x800000u
-#define LPUART_CTRL_TIE_SHIFT 23
-#define LPUART_CTRL_PEIE_MASK 0x1000000u
-#define LPUART_CTRL_PEIE_SHIFT 24
-#define LPUART_CTRL_FEIE_MASK 0x2000000u
-#define LPUART_CTRL_FEIE_SHIFT 25
-#define LPUART_CTRL_NEIE_MASK 0x4000000u
-#define LPUART_CTRL_NEIE_SHIFT 26
-#define LPUART_CTRL_ORIE_MASK 0x8000000u
-#define LPUART_CTRL_ORIE_SHIFT 27
-#define LPUART_CTRL_TXINV_MASK 0x10000000u
-#define LPUART_CTRL_TXINV_SHIFT 28
-#define LPUART_CTRL_TXDIR_MASK 0x20000000u
-#define LPUART_CTRL_TXDIR_SHIFT 29
-#define LPUART_CTRL_R9T8_MASK 0x40000000u
-#define LPUART_CTRL_R9T8_SHIFT 30
-#define LPUART_CTRL_R8T9_MASK 0x80000000u
-#define LPUART_CTRL_R8T9_SHIFT 31
-/* DATA Bit Fields */
-#define LPUART_DATA_R0T0_MASK 0x1u
-#define LPUART_DATA_R0T0_SHIFT 0
-#define LPUART_DATA_R1T1_MASK 0x2u
-#define LPUART_DATA_R1T1_SHIFT 1
-#define LPUART_DATA_R2T2_MASK 0x4u
-#define LPUART_DATA_R2T2_SHIFT 2
-#define LPUART_DATA_R3T3_MASK 0x8u
-#define LPUART_DATA_R3T3_SHIFT 3
-#define LPUART_DATA_R4T4_MASK 0x10u
-#define LPUART_DATA_R4T4_SHIFT 4
-#define LPUART_DATA_R5T5_MASK 0x20u
-#define LPUART_DATA_R5T5_SHIFT 5
-#define LPUART_DATA_R6T6_MASK 0x40u
-#define LPUART_DATA_R6T6_SHIFT 6
-#define LPUART_DATA_R7T7_MASK 0x80u
-#define LPUART_DATA_R7T7_SHIFT 7
-#define LPUART_DATA_R8T8_MASK 0x100u
-#define LPUART_DATA_R8T8_SHIFT 8
-#define LPUART_DATA_R9T9_MASK 0x200u
-#define LPUART_DATA_R9T9_SHIFT 9
-#define LPUART_DATA_IDLINE_MASK 0x800u
-#define LPUART_DATA_IDLINE_SHIFT 11
-#define LPUART_DATA_RXEMPT_MASK 0x1000u
-#define LPUART_DATA_RXEMPT_SHIFT 12
-#define LPUART_DATA_FRETSC_MASK 0x2000u
-#define LPUART_DATA_FRETSC_SHIFT 13
-#define LPUART_DATA_PARITYE_MASK 0x4000u
-#define LPUART_DATA_PARITYE_SHIFT 14
-#define LPUART_DATA_NOISY_MASK 0x8000u
-#define LPUART_DATA_NOISY_SHIFT 15
-/* MATCH Bit Fields */
-#define LPUART_MATCH_MA1_MASK 0x3FFu
-#define LPUART_MATCH_MA1_SHIFT 0
-#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
-#define LPUART_MATCH_MA2_MASK 0x3FF0000u
-#define LPUART_MATCH_MA2_SHIFT 16
-#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
-/* MODIR Bit Fields */
-#define LPUART_MODIR_TXCTSE_MASK 0x1u
-#define LPUART_MODIR_TXCTSE_SHIFT 0
-#define LPUART_MODIR_TXRTSE_MASK 0x2u
-#define LPUART_MODIR_TXRTSE_SHIFT 1
-#define LPUART_MODIR_TXRTSPOL_MASK 0x4u
-#define LPUART_MODIR_TXRTSPOL_SHIFT 2
-#define LPUART_MODIR_RXRTSE_MASK 0x8u
-#define LPUART_MODIR_RXRTSE_SHIFT 3
-#define LPUART_MODIR_TXCTSC_MASK 0x10u
-#define LPUART_MODIR_TXCTSC_SHIFT 4
-#define LPUART_MODIR_TXCTSSRC_MASK 0x20u
-#define LPUART_MODIR_TXCTSSRC_SHIFT 5
-#define LPUART_MODIR_TNP_MASK 0x30000u
-#define LPUART_MODIR_TNP_SHIFT 16
-#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
-#define LPUART_MODIR_IREN_MASK 0x40000u
-#define LPUART_MODIR_IREN_SHIFT 18
-
-/*!
- * @}
- */ /* end of group LPUART_Register_Masks */
-
-
-/* LPUART - Peripheral instance base addresses */
-/** Peripheral LPUART0 base address */
-#define LPUART0_BASE (0x4002A000u)
-/** Peripheral LPUART0 base pointer */
-#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
-#define LPUART0_BASE_PTR (LPUART0)
-/** Array initializer of LPUART peripheral base addresses */
-#define LPUART_BASE_ADDRS { LPUART0_BASE }
-/** Array initializer of LPUART peripheral base pointers */
-#define LPUART_BASE_PTRS { LPUART0 }
-/** Interrupt vectors for the LPUART peripheral type */
-#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
-#define LPUART_ERR_IRQS { LPUART0_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- LPUART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
- * @{
- */
-
-
-/* LPUART - Register instance definitions */
-/* LPUART0 */
-#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
-#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
-#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
-#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
-#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
-#define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
-
-/*!
- * @}
- */ /* end of group LPUART_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group LPUART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
- * @{
- */
-
-/** MCG - Register Layout Typedef */
-typedef struct {
- __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
- __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
- __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
- __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
- __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
- __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
- __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
- uint8_t RESERVED_0[1];
- __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
- uint8_t RESERVED_1[1];
- __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
- __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
- __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
- __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
-} MCG_Type, *MCG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register accessors */
-#define MCG_C1_REG(base) ((base)->C1)
-#define MCG_C2_REG(base) ((base)->C2)
-#define MCG_C3_REG(base) ((base)->C3)
-#define MCG_C4_REG(base) ((base)->C4)
-#define MCG_C5_REG(base) ((base)->C5)
-#define MCG_C6_REG(base) ((base)->C6)
-#define MCG_S_REG(base) ((base)->S)
-#define MCG_SC_REG(base) ((base)->SC)
-#define MCG_ATCVH_REG(base) ((base)->ATCVH)
-#define MCG_ATCVL_REG(base) ((base)->ATCVL)
-#define MCG_C7_REG(base) ((base)->C7)
-#define MCG_C8_REG(base) ((base)->C8)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Masks MCG Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_EREFS_MASK 0x4u
-#define MCG_C2_EREFS_SHIFT 2
-#define MCG_C2_HGO_MASK 0x8u
-#define MCG_C2_HGO_SHIFT 3
-#define MCG_C2_RANGE_MASK 0x30u
-#define MCG_C2_RANGE_SHIFT 4
-#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
-#define MCG_C2_FCFTRIM_MASK 0x40u
-#define MCG_C2_FCFTRIM_SHIFT 6
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK 0x1Fu
-#define MCG_C5_PRDIV0_SHIFT 0
-#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK 0x20u
-#define MCG_C5_PLLSTEN0_SHIFT 5
-#define MCG_C5_PLLCLKEN0_MASK 0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT 6
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK 0x1Fu
-#define MCG_C6_VDIV0_SHIFT 0
-#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK 0x20u
-#define MCG_C6_CME0_SHIFT 5
-#define MCG_C6_PLLS_MASK 0x40u
-#define MCG_C6_PLLS_SHIFT 6
-#define MCG_C6_LOLIE0_MASK 0x80u
-#define MCG_C6_LOLIE0_SHIFT 7
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_PLLST_MASK 0x20u
-#define MCG_S_PLLST_SHIFT 5
-#define MCG_S_LOCK0_MASK 0x40u
-#define MCG_S_LOCK0_SHIFT 6
-#define MCG_S_LOLS0_MASK 0x80u
-#define MCG_S_LOLS0_SHIFT 7
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK 0x3u
-#define MCG_C7_OSCSEL_SHIFT 0
-#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK 0x1u
-#define MCG_C8_LOCS1_SHIFT 0
-#define MCG_C8_CME1_MASK 0x20u
-#define MCG_C8_CME1_SHIFT 5
-#define MCG_C8_LOLRE_MASK 0x40u
-#define MCG_C8_LOLRE_SHIFT 6
-#define MCG_C8_LOCRE1_MASK 0x80u
-#define MCG_C8_LOCRE1_SHIFT 7
-
-/*!
- * @}
- */ /* end of group MCG_Register_Masks */
-
-
-/* MCG - Peripheral instance base addresses */
-/** Peripheral MCG base address */
-#define MCG_BASE (0x40064000u)
-/** Peripheral MCG base pointer */
-#define MCG ((MCG_Type *)MCG_BASE)
-#define MCG_BASE_PTR (MCG)
-/** Array initializer of MCG peripheral base addresses */
-#define MCG_BASE_ADDRS { MCG_BASE }
-/** Array initializer of MCG peripheral base pointers */
-#define MCG_BASE_PTRS { MCG }
-
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register instance definitions */
-/* MCG */
-#define MCG_C1 MCG_C1_REG(MCG)
-#define MCG_C2 MCG_C2_REG(MCG)
-#define MCG_C3 MCG_C3_REG(MCG)
-#define MCG_C4 MCG_C4_REG(MCG)
-#define MCG_C5 MCG_C5_REG(MCG)
-#define MCG_C6 MCG_C6_REG(MCG)
-#define MCG_S MCG_S_REG(MCG)
-#define MCG_SC MCG_SC_REG(MCG)
-#define MCG_ATCVH MCG_ATCVH_REG(MCG)
-#define MCG_ATCVL MCG_ATCVL_REG(MCG)
-#define MCG_C7 MCG_C7_REG(MCG)
-#define MCG_C8 MCG_C8_REG(MCG)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group MCG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
- * @{
- */
-
-/** MCM - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[8];
- __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
- __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
- __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
- __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
- uint8_t RESERVED_1[44];
- __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
-} MCM_Type, *MCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register accessors */
-#define MCM_PLASC_REG(base) ((base)->PLASC)
-#define MCM_PLAMC_REG(base) ((base)->PLAMC)
-#define MCM_PLACR_REG(base) ((base)->PLACR)
-#define MCM_ISCR_REG(base) ((base)->ISCR)
-#define MCM_CPO_REG(base) ((base)->CPO)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- MCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Masks MCM Register Masks
- * @{
- */
-
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK 0xFFu
-#define MCM_PLASC_ASC_SHIFT 0
-#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK 0xFFu
-#define MCM_PLAMC_AMC_SHIFT 0
-#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* PLACR Bit Fields */
-#define MCM_PLACR_ARB_MASK 0x200u
-#define MCM_PLACR_ARB_SHIFT 9
-/* ISCR Bit Fields */
-#define MCM_ISCR_FIOC_MASK 0x100u
-#define MCM_ISCR_FIOC_SHIFT 8
-#define MCM_ISCR_FDZC_MASK 0x200u
-#define MCM_ISCR_FDZC_SHIFT 9
-#define MCM_ISCR_FOFC_MASK 0x400u
-#define MCM_ISCR_FOFC_SHIFT 10
-#define MCM_ISCR_FUFC_MASK 0x800u
-#define MCM_ISCR_FUFC_SHIFT 11
-#define MCM_ISCR_FIXC_MASK 0x1000u
-#define MCM_ISCR_FIXC_SHIFT 12
-#define MCM_ISCR_FIDC_MASK 0x8000u
-#define MCM_ISCR_FIDC_SHIFT 15
-#define MCM_ISCR_FIOCE_MASK 0x1000000u
-#define MCM_ISCR_FIOCE_SHIFT 24
-#define MCM_ISCR_FDZCE_MASK 0x2000000u
-#define MCM_ISCR_FDZCE_SHIFT 25
-#define MCM_ISCR_FOFCE_MASK 0x4000000u
-#define MCM_ISCR_FOFCE_SHIFT 26
-#define MCM_ISCR_FUFCE_MASK 0x8000000u
-#define MCM_ISCR_FUFCE_SHIFT 27
-#define MCM_ISCR_FIXCE_MASK 0x10000000u
-#define MCM_ISCR_FIXCE_SHIFT 28
-#define MCM_ISCR_FIDCE_MASK 0x80000000u
-#define MCM_ISCR_FIDCE_SHIFT 31
-/* CPO Bit Fields */
-#define MCM_CPO_CPOREQ_MASK 0x1u
-#define MCM_CPO_CPOREQ_SHIFT 0
-#define MCM_CPO_CPOACK_MASK 0x2u
-#define MCM_CPO_CPOACK_SHIFT 1
-#define MCM_CPO_CPOWOI_MASK 0x4u
-#define MCM_CPO_CPOWOI_SHIFT 2
-
-/*!
- * @}
- */ /* end of group MCM_Register_Masks */
-
-
-/* MCM - Peripheral instance base addresses */
-/** Peripheral MCM base address */
-#define MCM_BASE (0xE0080000u)
-/** Peripheral MCM base pointer */
-#define MCM ((MCM_Type *)MCM_BASE)
-#define MCM_BASE_PTR (MCM)
-/** Array initializer of MCM peripheral base addresses */
-#define MCM_BASE_ADDRS { MCM_BASE }
-/** Array initializer of MCM peripheral base pointers */
-#define MCM_BASE_PTRS { MCM }
-
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register instance definitions */
-/* MCM */
-#define MCM_PLASC MCM_PLASC_REG(MCM)
-#define MCM_PLAMC MCM_PLAMC_REG(MCM)
-#define MCM_PLACR MCM_PLACR_REG(MCM)
-#define MCM_ISCR MCM_ISCR_REG(MCM)
-#define MCM_CPO MCM_CPO_REG(MCM)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group MCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
- * @{
- */
-
-/** NV - Register Layout Typedef */
-typedef struct {
- __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
- __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
- __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
- __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
- __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
- __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
- __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
- __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
- __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
- __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
- __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
- __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
- __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
- __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
-} NV_Type, *NV_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register accessors */
-#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
-#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
-#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
-#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
-#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
-#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
-#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
-#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
-#define NV_FPROT3_REG(base) ((base)->FPROT3)
-#define NV_FPROT2_REG(base) ((base)->FPROT2)
-#define NV_FPROT1_REG(base) ((base)->FPROT1)
-#define NV_FPROT0_REG(base) ((base)->FPROT0)
-#define NV_FSEC_REG(base) ((base)->FSEC)
-#define NV_FOPT_REG(base) ((base)->FOPT)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Masks NV Register Masks
- * @{
- */
-
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK 0x1u
-#define NV_FOPT_LPBOOT_SHIFT 0
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-#define NV_FOPT_NMI_DIS_MASK 0x4u
-#define NV_FOPT_NMI_DIS_SHIFT 2
-#define NV_FOPT_FAST_INIT_MASK 0x20u
-#define NV_FOPT_FAST_INIT_SHIFT 5
-
-/*!
- * @}
- */ /* end of group NV_Register_Masks */
-
-
-/* NV - Peripheral instance base addresses */
-/** Peripheral FTFA_FlashConfig base address */
-#define FTFA_FlashConfig_BASE (0x400u)
-/** Peripheral FTFA_FlashConfig base pointer */
-#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
-#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
-/** Array initializer of NV peripheral base addresses */
-#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
-/** Array initializer of NV peripheral base pointers */
-#define NV_BASE_PTRS { FTFA_FlashConfig }
-
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register instance definitions */
-/* FTFA_FlashConfig */
-#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
-#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
-#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
-#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
-#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
-#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
-#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
-#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
-#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
-#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
-#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
-#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
-#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
-#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group NV_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
- * @{
- */
-
-/** OSC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
- uint8_t RESERVED_0[1];
- __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
-} OSC_Type, *OSC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register accessors */
-#define OSC_CR_REG(base) ((base)->CR)
-#define OSC_DIV_REG(base) ((base)->DIV)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Masks OSC Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-/* DIV Bit Fields */
-#define OSC_DIV_ERPS_MASK 0xC0u
-#define OSC_DIV_ERPS_SHIFT 6
-#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Masks */
-
-
-/* OSC - Peripheral instance base addresses */
-/** Peripheral OSC base address */
-#define OSC_BASE (0x40065000u)
-/** Peripheral OSC base pointer */
-#define OSC ((OSC_Type *)OSC_BASE)
-#define OSC_BASE_PTR (OSC)
-/** Array initializer of OSC peripheral base addresses */
-#define OSC_BASE_ADDRS { OSC_BASE }
-/** Array initializer of OSC peripheral base pointers */
-#define OSC_BASE_PTRS { OSC }
-
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register instance definitions */
-/* OSC */
-#define OSC_CR OSC_CR_REG(OSC)
-#define OSC_DIV OSC_DIV_REG(OSC)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group OSC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PDB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
- * @{
- */
-
-/** PDB - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
- __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
- __I uint32_t CNT; /**< Counter register, offset: 0x8 */
- __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
- struct { /* offset: 0x10, array step: 0x28 */
- __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
- __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
- __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
- uint8_t RESERVED_0[24];
- } CH[2];
- uint8_t RESERVED_0[240];
- struct { /* offset: 0x150, array step: 0x8 */
- __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
- __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
- } DAC[2];
- uint8_t RESERVED_1[48];
- __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
- __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
-} PDB_Type, *PDB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register accessors */
-#define PDB_SC_REG(base) ((base)->SC)
-#define PDB_MOD_REG(base) ((base)->MOD)
-#define PDB_CNT_REG(base) ((base)->CNT)
-#define PDB_IDLY_REG(base) ((base)->IDLY)
-#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
-#define PDB_S_REG(base,index) ((base)->CH[index].S)
-#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
-#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
-#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
-#define PDB_POEN_REG(base) ((base)->POEN)
-#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PDB Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Masks PDB Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK 0x1u
-#define PDB_SC_LDOK_SHIFT 0
-#define PDB_SC_CONT_MASK 0x2u
-#define PDB_SC_CONT_SHIFT 1
-#define PDB_SC_MULT_MASK 0xCu
-#define PDB_SC_MULT_SHIFT 2
-#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK 0x20u
-#define PDB_SC_PDBIE_SHIFT 5
-#define PDB_SC_PDBIF_MASK 0x40u
-#define PDB_SC_PDBIF_SHIFT 6
-#define PDB_SC_PDBEN_MASK 0x80u
-#define PDB_SC_PDBEN_SHIFT 7
-#define PDB_SC_TRGSEL_MASK 0xF00u
-#define PDB_SC_TRGSEL_SHIFT 8
-#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK 0x7000u
-#define PDB_SC_PRESCALER_SHIFT 12
-#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK 0x8000u
-#define PDB_SC_DMAEN_SHIFT 15
-#define PDB_SC_SWTRIG_MASK 0x10000u
-#define PDB_SC_SWTRIG_SHIFT 16
-#define PDB_SC_PDBEIE_MASK 0x20000u
-#define PDB_SC_PDBEIE_SHIFT 17
-#define PDB_SC_LDMOD_MASK 0xC0000u
-#define PDB_SC_LDMOD_SHIFT 18
-#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK 0xFFFFu
-#define PDB_MOD_MOD_SHIFT 0
-#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK 0xFFFFu
-#define PDB_CNT_CNT_SHIFT 0
-#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK 0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT 0
-#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK 0xFFu
-#define PDB_C1_EN_SHIFT 0
-#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK 0xFF00u
-#define PDB_C1_TOS_SHIFT 8
-#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK 0xFF0000u
-#define PDB_C1_BB_SHIFT 16
-#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK 0xFFu
-#define PDB_S_ERR_SHIFT 0
-#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK 0xFF0000u
-#define PDB_S_CF_SHIFT 16
-#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK 0xFFFFu
-#define PDB_DLY_DLY_SHIFT 0
-#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* INTC Bit Fields */
-#define PDB_INTC_TOE_MASK 0x1u
-#define PDB_INTC_TOE_SHIFT 0
-#define PDB_INTC_EXT_MASK 0x2u
-#define PDB_INTC_EXT_SHIFT 1
-/* INT Bit Fields */
-#define PDB_INT_INT_MASK 0xFFFFu
-#define PDB_INT_INT_SHIFT 0
-#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK 0xFFu
-#define PDB_POEN_POEN_SHIFT 0
-#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK 0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT 0
-#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT 16
-#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Masks */
-
-
-/* PDB - Peripheral instance base addresses */
-/** Peripheral PDB0 base address */
-#define PDB0_BASE (0x40036000u)
-/** Peripheral PDB0 base pointer */
-#define PDB0 ((PDB_Type *)PDB0_BASE)
-#define PDB0_BASE_PTR (PDB0)
-/** Array initializer of PDB peripheral base addresses */
-#define PDB_BASE_ADDRS { PDB0_BASE }
-/** Array initializer of PDB peripheral base pointers */
-#define PDB_BASE_PTRS { PDB0 }
-/** Interrupt vectors for the PDB peripheral type */
-#define PDB_IRQS { PDB0_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register instance definitions */
-/* PDB0 */
-#define PDB0_SC PDB_SC_REG(PDB0)
-#define PDB0_MOD PDB_MOD_REG(PDB0)
-#define PDB0_CNT PDB_CNT_REG(PDB0)
-#define PDB0_IDLY PDB_IDLY_REG(PDB0)
-#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
-#define PDB0_CH0S PDB_S_REG(PDB0,0)
-#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
-#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
-#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
-#define PDB0_CH1S PDB_S_REG(PDB0,1)
-#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
-#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
-#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
-#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
-#define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
-#define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
-#define PDB0_POEN PDB_POEN_REG(PDB0)
-#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
-#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
-
-/* PDB - Register array accessors */
-#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
-#define PDB0_S(index) PDB_S_REG(PDB0,index)
-#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
-#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
-#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
-#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PDB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
- * @{
- */
-
-/** PIT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
- uint8_t RESERVED_0[252];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
- __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
- __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
- __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
- } CHANNEL[4];
-} PIT_Type, *PIT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register accessors */
-#define PIT_MCR_REG(base) ((base)->MCR)
-#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
-#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
-#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
-#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-#define PIT_TCTRL_CHN_MASK 0x4u
-#define PIT_TCTRL_CHN_SHIFT 2
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-
-/*!
- * @}
- */ /* end of group PIT_Register_Masks */
-
-
-/* PIT - Peripheral instance base addresses */
-/** Peripheral PIT base address */
-#define PIT_BASE (0x40037000u)
-/** Peripheral PIT base pointer */
-#define PIT ((PIT_Type *)PIT_BASE)
-#define PIT_BASE_PTR (PIT)
-/** Array initializer of PIT peripheral base addresses */
-#define PIT_BASE_ADDRS { PIT_BASE }
-/** Array initializer of PIT peripheral base pointers */
-#define PIT_BASE_PTRS { PIT }
-/** Interrupt vectors for the PIT peripheral type */
-#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register instance definitions */
-/* PIT */
-#define PIT_MCR PIT_MCR_REG(PIT)
-#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
-#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
-#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
-#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
-#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
-#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
-#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
-#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
-#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
-#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
-#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
-#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
-#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
-#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
-#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
-#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
-
-/* PIT - Register array accessors */
-#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
-#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
-#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
-#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
- * @{
- */
-
-/** PMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
- __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
- __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type, *PMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register accessors */
-#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
-#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
-#define PMC_REGSC_REG(base) ((base)->REGSC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Masks PMC Register Masks
- * @{
- */
-
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-#define PMC_REGSC_BGEN_MASK 0x10u
-#define PMC_REGSC_BGEN_SHIFT 4
-
-/*!
- * @}
- */ /* end of group PMC_Register_Masks */
-
-
-/* PMC - Peripheral instance base addresses */
-/** Peripheral PMC base address */
-#define PMC_BASE (0x4007D000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-#define PMC_BASE_PTR (PMC)
-/** Array initializer of PMC peripheral base addresses */
-#define PMC_BASE_ADDRS { PMC_BASE }
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASE_PTRS { PMC }
-/** Interrupt vectors for the PMC peripheral type */
-#define PMC_IRQS { LVD_LVW_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register instance definitions */
-/* PMC */
-#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
-#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
-#define PMC_REGSC PMC_REGSC_REG(PMC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
- * @{
- */
-
-/** PORT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
- __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
- __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
- uint8_t RESERVED_0[24];
- __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
- uint8_t RESERVED_1[28];
- __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
- __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
- __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type, *PORT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register accessors */
-#define PORT_PCR_REG(base,index) ((base)->PCR[index])
-#define PORT_GPCLR_REG(base) ((base)->GPCLR)
-#define PORT_GPCHR_REG(base) ((base)->GPCHR)
-#define PORT_ISFR_REG(base) ((base)->ISFR)
-#define PORT_DFER_REG(base) ((base)->DFER)
-#define PORT_DFCR_REG(base) ((base)->DFCR)
-#define PORT_DFWR_REG(base) ((base)->DFWR)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Masks PORT Register Masks
- * @{
- */
-
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_ODE_MASK 0x20u
-#define PORT_PCR_ODE_SHIFT 5
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK 0x8000u
-#define PORT_PCR_LK_SHIFT 15
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT 0
-#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK 0x1u
-#define PORT_DFCR_CS_SHIFT 0
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK 0x1Fu
-#define PORT_DFWR_FILT_SHIFT 0
-#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Masks */
-
-
-/* PORT - Peripheral instance base addresses */
-/** Peripheral PORTA base address */
-#define PORTA_BASE (0x40049000u)
-/** Peripheral PORTA base pointer */
-#define PORTA ((PORT_Type *)PORTA_BASE)
-#define PORTA_BASE_PTR (PORTA)
-/** Peripheral PORTB base address */
-#define PORTB_BASE (0x4004A000u)
-/** Peripheral PORTB base pointer */
-#define PORTB ((PORT_Type *)PORTB_BASE)
-#define PORTB_BASE_PTR (PORTB)
-/** Peripheral PORTC base address */
-#define PORTC_BASE (0x4004B000u)
-/** Peripheral PORTC base pointer */
-#define PORTC ((PORT_Type *)PORTC_BASE)
-#define PORTC_BASE_PTR (PORTC)
-/** Peripheral PORTD base address */
-#define PORTD_BASE (0x4004C000u)
-/** Peripheral PORTD base pointer */
-#define PORTD ((PORT_Type *)PORTD_BASE)
-#define PORTD_BASE_PTR (PORTD)
-/** Peripheral PORTE base address */
-#define PORTE_BASE (0x4004D000u)
-/** Peripheral PORTE base pointer */
-#define PORTE ((PORT_Type *)PORTE_BASE)
-#define PORTE_BASE_PTR (PORTE)
-/** Array initializer of PORT peripheral base addresses */
-#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
-/** Array initializer of PORT peripheral base pointers */
-#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
-/** Interrupt vectors for the PORT peripheral type */
-#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register instance definitions */
-/* PORTA */
-#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
-#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
-#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
-#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
-#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
-#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
-#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
-#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
-#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
-#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
-#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
-#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
-#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
-#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
-#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
-#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
-#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
-#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
-#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
-#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
-#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
-#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
-#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
-#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
-#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
-#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
-#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
-#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
-#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
-#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
-#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
-#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
-#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
-#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
-#define PORTA_ISFR PORT_ISFR_REG(PORTA)
-/* PORTB */
-#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
-#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
-#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
-#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
-#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
-#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
-#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
-#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
-#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
-#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
-#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
-#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
-#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
-#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
-#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
-#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
-#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
-#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
-#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
-#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
-#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
-#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
-#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
-#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
-#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
-#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
-#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
-#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
-#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
-#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
-#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
-#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
-#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
-#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
-#define PORTB_ISFR PORT_ISFR_REG(PORTB)
-/* PORTC */
-#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
-#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
-#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
-#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
-#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
-#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
-#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
-#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
-#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
-#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
-#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
-#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
-#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
-#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
-#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
-#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
-#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
-#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
-#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
-#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
-#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
-#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
-#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
-#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
-#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
-#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
-#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
-#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
-#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
-#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
-#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
-#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
-#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
-#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
-#define PORTC_ISFR PORT_ISFR_REG(PORTC)
-/* PORTD */
-#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
-#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
-#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
-#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
-#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
-#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
-#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
-#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
-#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
-#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
-#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
-#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
-#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
-#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
-#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
-#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
-#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
-#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
-#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
-#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
-#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
-#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
-#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
-#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
-#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
-#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
-#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
-#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
-#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
-#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
-#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
-#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
-#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
-#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
-#define PORTD_ISFR PORT_ISFR_REG(PORTD)
-#define PORTD_DFER PORT_DFER_REG(PORTD)
-#define PORTD_DFCR PORT_DFCR_REG(PORTD)
-#define PORTD_DFWR PORT_DFWR_REG(PORTD)
-/* PORTE */
-#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
-#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
-#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
-#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
-#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
-#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
-#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
-#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
-#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
-#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
-#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
-#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
-#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
-#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
-#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
-#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
-#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
-#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
-#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
-#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
-#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
-#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
-#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
-#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
-#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
-#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
-#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
-#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
-#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
-#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
-#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
-#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
-#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
-#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
-#define PORTE_ISFR PORT_ISFR_REG(PORTE)
-
-/* PORT - Register array accessors */
-#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
-#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
-#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
-#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
-#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PORT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
- * @{
- */
-
-/** RCM - Register Layout Typedef */
-typedef struct {
- __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
- __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
- uint8_t RESERVED_0[2];
- __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
- __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
- uint8_t RESERVED_1[1];
- __I uint8_t MR; /**< Mode Register, offset: 0x7 */
- __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
- __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
-} RCM_Type, *RCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register accessors */
-#define RCM_SRS0_REG(base) ((base)->SRS0)
-#define RCM_SRS1_REG(base) ((base)->SRS1)
-#define RCM_RPFC_REG(base) ((base)->RPFC)
-#define RCM_RPFW_REG(base) ((base)->RPFW)
-#define RCM_MR_REG(base) ((base)->MR)
-#define RCM_SSRS0_REG(base) ((base)->SSRS0)
-#define RCM_SSRS1_REG(base) ((base)->SSRS1)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Masks RCM Register Masks
- * @{
- */
-
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOL_MASK 0x8u
-#define RCM_SRS0_LOL_SHIFT 3
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK 0x1u
-#define RCM_SRS1_JTAG_SHIFT 0
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_EZPT_MASK 0x10u
-#define RCM_SRS1_EZPT_SHIFT 4
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK 0x2u
-#define RCM_MR_EZP_MS_SHIFT 1
-/* SSRS0 Bit Fields */
-#define RCM_SSRS0_SWAKEUP_MASK 0x1u
-#define RCM_SSRS0_SWAKEUP_SHIFT 0
-#define RCM_SSRS0_SLVD_MASK 0x2u
-#define RCM_SSRS0_SLVD_SHIFT 1
-#define RCM_SSRS0_SLOC_MASK 0x4u
-#define RCM_SSRS0_SLOC_SHIFT 2
-#define RCM_SSRS0_SLOL_MASK 0x8u
-#define RCM_SSRS0_SLOL_SHIFT 3
-#define RCM_SSRS0_SWDOG_MASK 0x20u
-#define RCM_SSRS0_SWDOG_SHIFT 5
-#define RCM_SSRS0_SPIN_MASK 0x40u
-#define RCM_SSRS0_SPIN_SHIFT 6
-#define RCM_SSRS0_SPOR_MASK 0x80u
-#define RCM_SSRS0_SPOR_SHIFT 7
-/* SSRS1 Bit Fields */
-#define RCM_SSRS1_SJTAG_MASK 0x1u
-#define RCM_SSRS1_SJTAG_SHIFT 0
-#define RCM_SSRS1_SLOCKUP_MASK 0x2u
-#define RCM_SSRS1_SLOCKUP_SHIFT 1
-#define RCM_SSRS1_SSW_MASK 0x4u
-#define RCM_SSRS1_SSW_SHIFT 2
-#define RCM_SSRS1_SMDM_AP_MASK 0x8u
-#define RCM_SSRS1_SMDM_AP_SHIFT 3
-#define RCM_SSRS1_SEZPT_MASK 0x10u
-#define RCM_SSRS1_SEZPT_SHIFT 4
-#define RCM_SSRS1_SSACKERR_MASK 0x20u
-#define RCM_SSRS1_SSACKERR_SHIFT 5
-
-/*!
- * @}
- */ /* end of group RCM_Register_Masks */
-
-
-/* RCM - Peripheral instance base addresses */
-/** Peripheral RCM base address */
-#define RCM_BASE (0x4007F000u)
-/** Peripheral RCM base pointer */
-#define RCM ((RCM_Type *)RCM_BASE)
-#define RCM_BASE_PTR (RCM)
-/** Array initializer of RCM peripheral base addresses */
-#define RCM_BASE_ADDRS { RCM_BASE }
-/** Array initializer of RCM peripheral base pointers */
-#define RCM_BASE_PTRS { RCM }
-
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register instance definitions */
-/* RCM */
-#define RCM_SRS0 RCM_SRS0_REG(RCM)
-#define RCM_SRS1 RCM_SRS1_REG(RCM)
-#define RCM_RPFC RCM_RPFC_REG(RCM)
-#define RCM_RPFW RCM_RPFW_REG(RCM)
-#define RCM_MR RCM_MR_REG(RCM)
-#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
-#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
- * @{
- */
-
-/** RFSYS - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type, *RFSYS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register accessors */
-#define RFSYS_REG_REG(base,index) ((base)->REG[index])
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK 0xFFu
-#define RFSYS_REG_LL_SHIFT 0
-#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK 0xFF00u
-#define RFSYS_REG_LH_SHIFT 8
-#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK 0xFF0000u
-#define RFSYS_REG_HL_SHIFT 16
-#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK 0xFF000000u
-#define RFSYS_REG_HH_SHIFT 24
-#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Masks */
-
-
-/* RFSYS - Peripheral instance base addresses */
-/** Peripheral RFSYS base address */
-#define RFSYS_BASE (0x40041000u)
-/** Peripheral RFSYS base pointer */
-#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
-#define RFSYS_BASE_PTR (RFSYS)
-/** Array initializer of RFSYS peripheral base addresses */
-#define RFSYS_BASE_ADDRS { RFSYS_BASE }
-/** Array initializer of RFSYS peripheral base pointers */
-#define RFSYS_BASE_PTRS { RFSYS }
-
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register instance definitions */
-/* RFSYS */
-#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
-#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
-#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
-#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
-#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
-#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
-#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
-#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
-
-/* RFSYS - Register array accessors */
-#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RFSYS_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
- * @{
- */
-
-/** RFVBAT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type, *RFVBAT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register accessors */
-#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK 0xFFu
-#define RFVBAT_REG_LL_SHIFT 0
-#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK 0xFF00u
-#define RFVBAT_REG_LH_SHIFT 8
-#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK 0xFF0000u
-#define RFVBAT_REG_HL_SHIFT 16
-#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK 0xFF000000u
-#define RFVBAT_REG_HH_SHIFT 24
-#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Masks */
-
-
-/* RFVBAT - Peripheral instance base addresses */
-/** Peripheral RFVBAT base address */
-#define RFVBAT_BASE (0x4003E000u)
-/** Peripheral RFVBAT base pointer */
-#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
-#define RFVBAT_BASE_PTR (RFVBAT)
-/** Array initializer of RFVBAT peripheral base addresses */
-#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
-/** Array initializer of RFVBAT peripheral base pointers */
-#define RFVBAT_BASE_PTRS { RFVBAT }
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register instance definitions */
-/* RFVBAT */
-#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
-#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
-#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
-#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
-#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
-#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
-#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
-#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
-
-/* RFVBAT - Register array accessors */
-#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RFVBAT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RNG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
- * @{
- */
-
-/** RNG - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
- __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
- __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
- __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
-} RNG_Type, *RNG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RNG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register accessors */
-#define RNG_CR_REG(base) ((base)->CR)
-#define RNG_SR_REG(base) ((base)->SR)
-#define RNG_ER_REG(base) ((base)->ER)
-#define RNG_OR_REG(base) ((base)->OR)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RNG Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Masks RNG Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define RNG_CR_GO_MASK 0x1u
-#define RNG_CR_GO_SHIFT 0
-#define RNG_CR_HA_MASK 0x2u
-#define RNG_CR_HA_SHIFT 1
-#define RNG_CR_INTM_MASK 0x4u
-#define RNG_CR_INTM_SHIFT 2
-#define RNG_CR_CLRI_MASK 0x8u
-#define RNG_CR_CLRI_SHIFT 3
-#define RNG_CR_SLP_MASK 0x10u
-#define RNG_CR_SLP_SHIFT 4
-/* SR Bit Fields */
-#define RNG_SR_SECV_MASK 0x1u
-#define RNG_SR_SECV_SHIFT 0
-#define RNG_SR_LRS_MASK 0x2u
-#define RNG_SR_LRS_SHIFT 1
-#define RNG_SR_ORU_MASK 0x4u
-#define RNG_SR_ORU_SHIFT 2
-#define RNG_SR_ERRI_MASK 0x8u
-#define RNG_SR_ERRI_SHIFT 3
-#define RNG_SR_SLP_MASK 0x10u
-#define RNG_SR_SLP_SHIFT 4
-#define RNG_SR_OREG_LVL_MASK 0xFF00u
-#define RNG_SR_OREG_LVL_SHIFT 8
-#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
-#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
-#define RNG_SR_OREG_SIZE_SHIFT 16
-#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
-/* ER Bit Fields */
-#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
-#define RNG_ER_EXT_ENT_SHIFT 0
-#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
-/* OR Bit Fields */
-#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
-#define RNG_OR_RANDOUT_SHIFT 0
-#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Masks */
-
-
-/* RNG - Peripheral instance base addresses */
-/** Peripheral RNG base address */
-#define RNG_BASE (0x40029000u)
-/** Peripheral RNG base pointer */
-#define RNG ((RNG_Type *)RNG_BASE)
-#define RNG_BASE_PTR (RNG)
-/** Array initializer of RNG peripheral base addresses */
-#define RNG_BASE_ADDRS { RNG_BASE }
-/** Array initializer of RNG peripheral base pointers */
-#define RNG_BASE_PTRS { RNG }
-/** Interrupt vectors for the RNG peripheral type */
-#define RNG_IRQS { RNG_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- RNG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register instance definitions */
-/* RNG */
-#define RNG_CR RNG_CR_REG(RNG)
-#define RNG_SR RNG_SR_REG(RNG)
-#define RNG_ER RNG_ER_REG(RNG)
-#define RNG_OR RNG_OR_REG(RNG)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RNG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
- __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
- __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
- __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
- __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
- __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
- __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
- __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
- uint8_t RESERVED_0[2016];
- __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
- __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type, *RTC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register accessors */
-#define RTC_TSR_REG(base) ((base)->TSR)
-#define RTC_TPR_REG(base) ((base)->TPR)
-#define RTC_TAR_REG(base) ((base)->TAR)
-#define RTC_TCR_REG(base) ((base)->TCR)
-#define RTC_CR_REG(base) ((base)->CR)
-#define RTC_SR_REG(base) ((base)->SR)
-#define RTC_LR_REG(base) ((base)->LR)
-#define RTC_IER_REG(base) ((base)->IER)
-#define RTC_WAR_REG(base) ((base)->WAR)
-#define RTC_RAR_REG(base) ((base)->RAR)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_WPS_MASK 0x10u
-#define RTC_CR_WPS_SHIFT 4
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-#define RTC_IER_WPON_MASK 0x80u
-#define RTC_IER_WPON_SHIFT 7
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK 0x1u
-#define RTC_WAR_TSRW_SHIFT 0
-#define RTC_WAR_TPRW_MASK 0x2u
-#define RTC_WAR_TPRW_SHIFT 1
-#define RTC_WAR_TARW_MASK 0x4u
-#define RTC_WAR_TARW_SHIFT 2
-#define RTC_WAR_TCRW_MASK 0x8u
-#define RTC_WAR_TCRW_SHIFT 3
-#define RTC_WAR_CRW_MASK 0x10u
-#define RTC_WAR_CRW_SHIFT 4
-#define RTC_WAR_SRW_MASK 0x20u
-#define RTC_WAR_SRW_SHIFT 5
-#define RTC_WAR_LRW_MASK 0x40u
-#define RTC_WAR_LRW_SHIFT 6
-#define RTC_WAR_IERW_MASK 0x80u
-#define RTC_WAR_IERW_SHIFT 7
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK 0x1u
-#define RTC_RAR_TSRR_SHIFT 0
-#define RTC_RAR_TPRR_MASK 0x2u
-#define RTC_RAR_TPRR_SHIFT 1
-#define RTC_RAR_TARR_MASK 0x4u
-#define RTC_RAR_TARR_SHIFT 2
-#define RTC_RAR_TCRR_MASK 0x8u
-#define RTC_RAR_TCRR_SHIFT 3
-#define RTC_RAR_CRR_MASK 0x10u
-#define RTC_RAR_CRR_SHIFT 4
-#define RTC_RAR_SRR_MASK 0x20u
-#define RTC_RAR_SRR_SHIFT 5
-#define RTC_RAR_LRR_MASK 0x40u
-#define RTC_RAR_LRR_SHIFT 6
-#define RTC_RAR_IERR_MASK 0x80u
-#define RTC_RAR_IERR_SHIFT 7
-
-/*!
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4003D000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-#define RTC_BASE_PTR (RTC)
-/** Array initializer of RTC peripheral base addresses */
-#define RTC_BASE_ADDRS { RTC_BASE }
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASE_PTRS { RTC }
-/** Interrupt vectors for the RTC peripheral type */
-#define RTC_IRQS { RTC_IRQn }
-#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register instance definitions */
-/* RTC */
-#define RTC_TSR RTC_TSR_REG(RTC)
-#define RTC_TPR RTC_TPR_REG(RTC)
-#define RTC_TAR RTC_TAR_REG(RTC)
-#define RTC_TCR RTC_TCR_REG(RTC)
-#define RTC_CR RTC_CR_REG(RTC)
-#define RTC_SR RTC_SR_REG(RTC)
-#define RTC_LR RTC_LR_REG(RTC)
-#define RTC_IER RTC_IER_REG(RTC)
-#define RTC_WAR RTC_WAR_REG(RTC)
-#define RTC_RAR RTC_RAR_REG(RTC)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
- * @{
- */
-
-/** SIM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
- __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
- uint8_t RESERVED_0[4092];
- __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
- __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
- uint8_t RESERVED_2[4];
- __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
- __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
- uint8_t RESERVED_3[4];
- __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
- uint8_t RESERVED_4[12];
- __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
- __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
- __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
- __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
- __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
- __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
- __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
- __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
- __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
- __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
- __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
- __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type, *SIM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register accessors */
-#define SIM_SOPT1_REG(base) ((base)->SOPT1)
-#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
-#define SIM_SOPT2_REG(base) ((base)->SOPT2)
-#define SIM_SOPT4_REG(base) ((base)->SOPT4)
-#define SIM_SOPT5_REG(base) ((base)->SOPT5)
-#define SIM_SOPT7_REG(base) ((base)->SOPT7)
-#define SIM_SOPT8_REG(base) ((base)->SOPT8)
-#define SIM_SDID_REG(base) ((base)->SDID)
-#define SIM_SCGC4_REG(base) ((base)->SCGC4)
-#define SIM_SCGC5_REG(base) ((base)->SCGC5)
-#define SIM_SCGC6_REG(base) ((base)->SCGC6)
-#define SIM_SCGC7_REG(base) ((base)->SCGC7)
-#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
-#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
-#define SIM_FCFG1_REG(base) ((base)->FCFG1)
-#define SIM_FCFG2_REG(base) ((base)->FCFG2)
-#define SIM_UIDH_REG(base) ((base)->UIDH)
-#define SIM_UIDMH_REG(base) ((base)->UIDMH)
-#define SIM_UIDML_REG(base) ((base)->UIDML)
-#define SIM_UIDL_REG(base) ((base)->UIDL)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Masks SIM Register Masks
- * @{
- */
-
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT 12
-#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
-#define SIM_SOPT1_OSC32KOUT_SHIFT 16
-#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT 29
-#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT 30
-#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT 31
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT 24
-#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT 25
-#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT 26
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_FBSL_MASK 0x300u
-#define SIM_SOPT2_FBSL_SHIFT 8
-#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
-#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-#define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
-#define SIM_SOPT2_LPUARTSRC_SHIFT 26
-#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT 0
-#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT 1
-#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT 4
-#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
-#define SIM_SOPT4_FTM2FLT0_SHIFT 8
-#define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
-#define SIM_SOPT4_FTM3FLT0_SHIFT 12
-#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
-#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
-#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH1SRC_MASK 0x400000u
-#define SIM_SOPT4_FTM2CH1SRC_SHIFT 22
-#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
-#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
-#define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
-#define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
-#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
-#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
-#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
-#define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
-#define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
-#define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
-#define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-#define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
-#define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
-#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
-#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
-#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
-#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
-#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
-#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
-#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
-/* SOPT8 Bit Fields */
-#define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
-#define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
-#define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
-#define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
-#define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
-#define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
-#define SIM_SOPT8_FTM3SYNCBIT_MASK 0x8u
-#define SIM_SOPT8_FTM3SYNCBIT_SHIFT 3
-#define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
-#define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
-#define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
-#define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
-#define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
-#define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
-#define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
-#define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
-#define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
-#define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
-#define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
-#define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
-#define SIM_SOPT8_FTM0OCH6SRC_MASK 0x400000u
-#define SIM_SOPT8_FTM0OCH6SRC_SHIFT 22
-#define SIM_SOPT8_FTM0OCH7SRC_MASK 0x800000u
-#define SIM_SOPT8_FTM0OCH7SRC_SHIFT 23
-#define SIM_SOPT8_FTM3OCH0SRC_MASK 0x1000000u
-#define SIM_SOPT8_FTM3OCH0SRC_SHIFT 24
-#define SIM_SOPT8_FTM3OCH1SRC_MASK 0x2000000u
-#define SIM_SOPT8_FTM3OCH1SRC_SHIFT 25
-#define SIM_SOPT8_FTM3OCH2SRC_MASK 0x4000000u
-#define SIM_SOPT8_FTM3OCH2SRC_SHIFT 26
-#define SIM_SOPT8_FTM3OCH3SRC_MASK 0x8000000u
-#define SIM_SOPT8_FTM3OCH3SRC_SHIFT 27
-#define SIM_SOPT8_FTM3OCH4SRC_MASK 0x10000000u
-#define SIM_SOPT8_FTM3OCH4SRC_SHIFT 28
-#define SIM_SOPT8_FTM3OCH5SRC_MASK 0x20000000u
-#define SIM_SOPT8_FTM3OCH5SRC_SHIFT 29
-#define SIM_SOPT8_FTM3OCH6SRC_MASK 0x40000000u
-#define SIM_SOPT8_FTM3OCH6SRC_SHIFT 30
-#define SIM_SOPT8_FTM3OCH7SRC_MASK 0x80000000u
-#define SIM_SOPT8_FTM3OCH7SRC_SHIFT 31
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK 0x70u
-#define SIM_SDID_FAMID_SHIFT 4
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_DIEID_MASK 0xF80u
-#define SIM_SDID_DIEID_SHIFT 7
-#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-#define SIM_SDID_SERIESID_MASK 0xF00000u
-#define SIM_SDID_SERIESID_SHIFT 20
-#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
-#define SIM_SDID_SUBFAMID_MASK 0xF000000u
-#define SIM_SDID_SUBFAMID_SHIFT 24
-#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
-#define SIM_SDID_FAMILYID_MASK 0xF0000000u
-#define SIM_SDID_FAMILYID_SHIFT 28
-#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK 0x2u
-#define SIM_SCGC4_EWM_SHIFT 1
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_I2C1_MASK 0x80u
-#define SIM_SCGC4_I2C1_SHIFT 7
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_VREF_MASK 0x100000u
-#define SIM_SCGC4_VREF_SHIFT 20
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTMR_MASK 0x1u
-#define SIM_SCGC5_LPTMR_SHIFT 0
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTF_MASK 0x1u
-#define SIM_SCGC6_FTF_SHIFT 0
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_FTM3_MASK 0x40u
-#define SIM_SCGC6_FTM3_SHIFT 6
-#define SIM_SCGC6_ADC1_MASK 0x80u
-#define SIM_SCGC6_ADC1_SHIFT 7
-#define SIM_SCGC6_DAC1_MASK 0x100u
-#define SIM_SCGC6_DAC1_SHIFT 8
-#define SIM_SCGC6_RNGA_MASK 0x200u
-#define SIM_SCGC6_RNGA_SHIFT 9
-#define SIM_SCGC6_LPUART0_MASK 0x400u
-#define SIM_SCGC6_LPUART0_SHIFT 10
-#define SIM_SCGC6_SPI0_MASK 0x1000u
-#define SIM_SCGC6_SPI0_SHIFT 12
-#define SIM_SCGC6_SPI1_MASK 0x2000u
-#define SIM_SCGC6_SPI1_SHIFT 13
-#define SIM_SCGC6_I2S_MASK 0x8000u
-#define SIM_SCGC6_I2S_SHIFT 15
-#define SIM_SCGC6_CRC_MASK 0x40000u
-#define SIM_SCGC6_CRC_SHIFT 18
-#define SIM_SCGC6_PDB_MASK 0x400000u
-#define SIM_SCGC6_PDB_SHIFT 22
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_FTM0_MASK 0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT 24
-#define SIM_SCGC6_FTM1_MASK 0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT 25
-#define SIM_SCGC6_FTM2_MASK 0x4000000u
-#define SIM_SCGC6_FTM2_SHIFT 26
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-#define SIM_SCGC6_DAC0_MASK 0x80000000u
-#define SIM_SCGC6_DAC0_SHIFT 31
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_FLEXBUS_MASK 0x1u
-#define SIM_SCGC7_FLEXBUS_SHIFT 0
-#define SIM_SCGC7_DMA_MASK 0x2u
-#define SIM_SCGC7_DMA_SHIFT 1
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
-#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
-#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
-#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT 0
-#define SIM_CLKDIV2_USBDIV_MASK 0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT 1
-#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT 16
-#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT 24
-#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT 0
-#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Masks */
-
-
-/* SIM - Peripheral instance base addresses */
-/** Peripheral SIM base address */
-#define SIM_BASE (0x40047000u)
-/** Peripheral SIM base pointer */
-#define SIM ((SIM_Type *)SIM_BASE)
-#define SIM_BASE_PTR (SIM)
-/** Array initializer of SIM peripheral base addresses */
-#define SIM_BASE_ADDRS { SIM_BASE }
-/** Array initializer of SIM peripheral base pointers */
-#define SIM_BASE_PTRS { SIM }
-
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register instance definitions */
-/* SIM */
-#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
-#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
-#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
-#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
-#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
-#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
-#define SIM_SOPT8 SIM_SOPT8_REG(SIM)
-#define SIM_SDID SIM_SDID_REG(SIM)
-#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
-#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
-#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
-#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
-#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
-#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
-#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
-#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
-#define SIM_UIDH SIM_UIDH_REG(SIM)
-#define SIM_UIDMH SIM_UIDMH_REG(SIM)
-#define SIM_UIDML SIM_UIDML_REG(SIM)
-#define SIM_UIDL SIM_UIDL_REG(SIM)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SIM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
- * @{
- */
-
-/** SMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
- __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
- __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
- __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type, *SMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register accessors */
-#define SMC_PMPROT_REG(base) ((base)->PMPROT)
-#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
-#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
-#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Masks SMC Register Masks
- * @{
- */
-
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-#define SMC_PMPROT_AHSRUN_MASK 0x80u
-#define SMC_PMPROT_AHSRUN_SHIFT 7
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-/* STOPCTRL Bit Fields */
-#define SMC_STOPCTRL_LLSM_MASK 0x7u
-#define SMC_STOPCTRL_LLSM_SHIFT 0
-#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
-#define SMC_STOPCTRL_PORPO_MASK 0x20u
-#define SMC_STOPCTRL_PORPO_SHIFT 5
-#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
-#define SMC_STOPCTRL_PSTOPO_SHIFT 6
-#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Masks */
-
-
-/* SMC - Peripheral instance base addresses */
-/** Peripheral SMC base address */
-#define SMC_BASE (0x4007E000u)
-/** Peripheral SMC base pointer */
-#define SMC ((SMC_Type *)SMC_BASE)
-#define SMC_BASE_PTR (SMC)
-/** Array initializer of SMC peripheral base addresses */
-#define SMC_BASE_ADDRS { SMC_BASE }
-/** Array initializer of SMC peripheral base pointers */
-#define SMC_BASE_PTRS { SMC }
-
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register instance definitions */
-/* SMC */
-#define SMC_PMPROT SMC_PMPROT_REG(SMC)
-#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
-#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
-#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
- uint8_t RESERVED_0[4];
- __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
- union { /* offset: 0xC */
- __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
- __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
- };
- uint8_t RESERVED_1[24];
- __IO uint32_t SR; /**< Status Register, offset: 0x2C */
- __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
- union { /* offset: 0x34 */
- __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
- __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
- };
- __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
- __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
- __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
- __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
- __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
- uint8_t RESERVED_2[48];
- __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
- __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
- __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
- __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
-} SPI_Type, *SPI_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register accessors */
-#define SPI_MCR_REG(base) ((base)->MCR)
-#define SPI_TCR_REG(base) ((base)->TCR)
-#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
-#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
-#define SPI_SR_REG(base) ((base)->SR)
-#define SPI_RSER_REG(base) ((base)->RSER)
-#define SPI_PUSHR_REG(base) ((base)->PUSHR)
-#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
-#define SPI_POPR_REG(base) ((base)->POPR)
-#define SPI_TXFR0_REG(base) ((base)->TXFR0)
-#define SPI_TXFR1_REG(base) ((base)->TXFR1)
-#define SPI_TXFR2_REG(base) ((base)->TXFR2)
-#define SPI_TXFR3_REG(base) ((base)->TXFR3)
-#define SPI_RXFR0_REG(base) ((base)->RXFR0)
-#define SPI_RXFR1_REG(base) ((base)->RXFR1)
-#define SPI_RXFR2_REG(base) ((base)->RXFR2)
-#define SPI_RXFR3_REG(base) ((base)->RXFR3)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK 0x1u
-#define SPI_MCR_HALT_SHIFT 0
-#define SPI_MCR_SMPL_PT_MASK 0x300u
-#define SPI_MCR_SMPL_PT_SHIFT 8
-#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK 0x400u
-#define SPI_MCR_CLR_RXF_SHIFT 10
-#define SPI_MCR_CLR_TXF_MASK 0x800u
-#define SPI_MCR_CLR_TXF_SHIFT 11
-#define SPI_MCR_DIS_RXF_MASK 0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT 12
-#define SPI_MCR_DIS_TXF_MASK 0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT 13
-#define SPI_MCR_MDIS_MASK 0x4000u
-#define SPI_MCR_MDIS_SHIFT 14
-#define SPI_MCR_DOZE_MASK 0x8000u
-#define SPI_MCR_DOZE_SHIFT 15
-#define SPI_MCR_PCSIS_MASK 0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT 16
-#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK 0x1000000u
-#define SPI_MCR_ROOE_SHIFT 24
-#define SPI_MCR_PCSSE_MASK 0x2000000u
-#define SPI_MCR_PCSSE_SHIFT 25
-#define SPI_MCR_MTFE_MASK 0x4000000u
-#define SPI_MCR_MTFE_SHIFT 26
-#define SPI_MCR_FRZ_MASK 0x8000000u
-#define SPI_MCR_FRZ_SHIFT 27
-#define SPI_MCR_DCONF_MASK 0x30000000u
-#define SPI_MCR_DCONF_SHIFT 28
-#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT 30
-#define SPI_MCR_MSTR_MASK 0x80000000u
-#define SPI_MCR_MSTR_SHIFT 31
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT 16
-#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK 0xFu
-#define SPI_CTAR_BR_SHIFT 0
-#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK 0xF0u
-#define SPI_CTAR_DT_SHIFT 4
-#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK 0xF00u
-#define SPI_CTAR_ASC_SHIFT 8
-#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK 0xF000u
-#define SPI_CTAR_CSSCK_SHIFT 12
-#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK 0x30000u
-#define SPI_CTAR_PBR_SHIFT 16
-#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK 0xC0000u
-#define SPI_CTAR_PDT_SHIFT 18
-#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK 0x300000u
-#define SPI_CTAR_PASC_SHIFT 20
-#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK 0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT 22
-#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK 0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT 24
-#define SPI_CTAR_CPHA_MASK 0x2000000u
-#define SPI_CTAR_CPHA_SHIFT 25
-#define SPI_CTAR_CPOL_MASK 0x4000000u
-#define SPI_CTAR_CPOL_SHIFT 26
-#define SPI_CTAR_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT 27
-#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK 0x80000000u
-#define SPI_CTAR_DBR_SHIFT 31
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
-#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
-#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
-#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK 0xFu
-#define SPI_SR_POPNXTPTR_SHIFT 0
-#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK 0xF0u
-#define SPI_SR_RXCTR_SHIFT 4
-#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK 0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT 8
-#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK 0xF000u
-#define SPI_SR_TXCTR_SHIFT 12
-#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK 0x20000u
-#define SPI_SR_RFDF_SHIFT 17
-#define SPI_SR_RFOF_MASK 0x80000u
-#define SPI_SR_RFOF_SHIFT 19
-#define SPI_SR_TFFF_MASK 0x2000000u
-#define SPI_SR_TFFF_SHIFT 25
-#define SPI_SR_TFUF_MASK 0x8000000u
-#define SPI_SR_TFUF_SHIFT 27
-#define SPI_SR_EOQF_MASK 0x10000000u
-#define SPI_SR_EOQF_SHIFT 28
-#define SPI_SR_TXRXS_MASK 0x40000000u
-#define SPI_SR_TXRXS_SHIFT 30
-#define SPI_SR_TCF_MASK 0x80000000u
-#define SPI_SR_TCF_SHIFT 31
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT 16
-#define SPI_RSER_RFDF_RE_MASK 0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT 17
-#define SPI_RSER_RFOF_RE_MASK 0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT 19
-#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT 24
-#define SPI_RSER_TFFF_RE_MASK 0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT 25
-#define SPI_RSER_TFUF_RE_MASK 0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT 27
-#define SPI_RSER_EOQF_RE_MASK 0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT 28
-#define SPI_RSER_TCF_RE_MASK 0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT 31
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT 0
-#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK 0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT 16
-#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK 0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT 26
-#define SPI_PUSHR_EOQ_MASK 0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT 27
-#define SPI_PUSHR_CTAS_MASK 0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT 28
-#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK 0x80000000u
-#define SPI_PUSHR_CONT_SHIFT 31
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
-#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT 0
-#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT 0
-#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT 0
-#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT 0
-#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT 0
-#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT 0
-#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT 0
-#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT 0
-#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT 0
-#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x4002C000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-#define SPI0_BASE_PTR (SPI0)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE (0x4002D000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1 ((SPI_Type *)SPI1_BASE)
-#define SPI1_BASE_PTR (SPI1)
-/** Array initializer of SPI peripheral base addresses */
-#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASE_PTRS { SPI0, SPI1 }
-/** Interrupt vectors for the SPI peripheral type */
-#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register instance definitions */
-/* SPI0 */
-#define SPI0_MCR SPI_MCR_REG(SPI0)
-#define SPI0_TCR SPI_TCR_REG(SPI0)
-#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
-#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
-#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
-#define SPI0_SR SPI_SR_REG(SPI0)
-#define SPI0_RSER SPI_RSER_REG(SPI0)
-#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
-#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
-#define SPI0_POPR SPI_POPR_REG(SPI0)
-#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
-#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
-#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
-#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
-#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
-#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
-#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
-#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
-/* SPI1 */
-#define SPI1_MCR SPI_MCR_REG(SPI1)
-#define SPI1_TCR SPI_TCR_REG(SPI1)
-#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
-#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
-#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
-#define SPI1_SR SPI_SR_REG(SPI1)
-#define SPI1_RSER SPI_RSER_REG(SPI1)
-#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
-#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
-#define SPI1_POPR SPI_POPR_REG(SPI1)
-#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
-#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
-#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
-#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
-#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
-#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
-#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
-#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
-
-/* SPI - Register array accessors */
-#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
-#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
-#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
-#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- UART Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
- * @{
- */
-
-/** UART - Register Layout Typedef */
-typedef struct {
- __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
- __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
- __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
- __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
- __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
- __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
- __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
- __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
- __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
- __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
- __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
- __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
- __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
- __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
- __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
- uint8_t RESERVED_0[1];
- __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
- __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
- __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
- __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
- __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
- __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
- __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
- uint8_t RESERVED_1[1];
- __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
- __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
- __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
- __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
- __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
- __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
- __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
- __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
- uint8_t RESERVED_2[26];
- __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
- __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
- union { /* offset: 0x3C */
- struct { /* offset: 0x3C */
- __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
- __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
- } TYPE0;
- struct { /* offset: 0x3C */
- __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
- __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
- } TYPE1;
- };
- __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
- __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
-} UART_Type, *UART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register accessors */
-#define UART_BDH_REG(base) ((base)->BDH)
-#define UART_BDL_REG(base) ((base)->BDL)
-#define UART_C1_REG(base) ((base)->C1)
-#define UART_C2_REG(base) ((base)->C2)
-#define UART_S1_REG(base) ((base)->S1)
-#define UART_S2_REG(base) ((base)->S2)
-#define UART_C3_REG(base) ((base)->C3)
-#define UART_D_REG(base) ((base)->D)
-#define UART_MA1_REG(base) ((base)->MA1)
-#define UART_MA2_REG(base) ((base)->MA2)
-#define UART_C4_REG(base) ((base)->C4)
-#define UART_C5_REG(base) ((base)->C5)
-#define UART_ED_REG(base) ((base)->ED)
-#define UART_MODEM_REG(base) ((base)->MODEM)
-#define UART_IR_REG(base) ((base)->IR)
-#define UART_PFIFO_REG(base) ((base)->PFIFO)
-#define UART_CFIFO_REG(base) ((base)->CFIFO)
-#define UART_SFIFO_REG(base) ((base)->SFIFO)
-#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
-#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
-#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
-#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
-#define UART_C7816_REG(base) ((base)->C7816)
-#define UART_IE7816_REG(base) ((base)->IE7816)
-#define UART_IS7816_REG(base) ((base)->IS7816)
-#define UART_WP7816_REG(base) ((base)->WP7816)
-#define UART_WN7816_REG(base) ((base)->WN7816)
-#define UART_WF7816_REG(base) ((base)->WF7816)
-#define UART_ET7816_REG(base) ((base)->ET7816)
-#define UART_TL7816_REG(base) ((base)->TL7816)
-#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
-#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
-#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
-#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
-#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
-#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
-#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
-#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- UART Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Masks UART Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_MSBF_MASK 0x20u
-#define UART_S2_MSBF_SHIFT 5
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-/* D Bit Fields */
-#define UART_D_RT_MASK 0xFFu
-#define UART_D_RT_SHIFT 0
-#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK 0xFFu
-#define UART_MA1_MA_SHIFT 0
-#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK 0xFFu
-#define UART_MA2_MA_SHIFT 0
-#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK 0x1Fu
-#define UART_C4_BRFA_SHIFT 0
-#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK 0x20u
-#define UART_C4_M10_SHIFT 5
-#define UART_C4_MAEN2_MASK 0x40u
-#define UART_C4_MAEN2_SHIFT 6
-#define UART_C4_MAEN1_MASK 0x80u
-#define UART_C4_MAEN1_SHIFT 7
-/* C5 Bit Fields */
-#define UART_C5_RDMAS_MASK 0x20u
-#define UART_C5_RDMAS_SHIFT 5
-#define UART_C5_TDMAS_MASK 0x80u
-#define UART_C5_TDMAS_SHIFT 7
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK 0x40u
-#define UART_ED_PARITYE_SHIFT 6
-#define UART_ED_NOISY_MASK 0x80u
-#define UART_ED_NOISY_SHIFT 7
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK 0x1u
-#define UART_MODEM_TXCTSE_SHIFT 0
-#define UART_MODEM_TXRTSE_MASK 0x2u
-#define UART_MODEM_TXRTSE_SHIFT 1
-#define UART_MODEM_TXRTSPOL_MASK 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT 2
-#define UART_MODEM_RXRTSE_MASK 0x8u
-#define UART_MODEM_RXRTSE_SHIFT 3
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK 0x3u
-#define UART_IR_TNP_SHIFT 0
-#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK 0x4u
-#define UART_IR_IREN_SHIFT 2
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
-#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK 0x8u
-#define UART_PFIFO_RXFE_SHIFT 3
-#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
-#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK 0x80u
-#define UART_PFIFO_TXFE_SHIFT 7
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK 0x1u
-#define UART_CFIFO_RXUFE_SHIFT 0
-#define UART_CFIFO_TXOFE_MASK 0x2u
-#define UART_CFIFO_TXOFE_SHIFT 1
-#define UART_CFIFO_RXOFE_MASK 0x4u
-#define UART_CFIFO_RXOFE_SHIFT 2
-#define UART_CFIFO_RXFLUSH_MASK 0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT 6
-#define UART_CFIFO_TXFLUSH_MASK 0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT 7
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK 0x1u
-#define UART_SFIFO_RXUF_SHIFT 0
-#define UART_SFIFO_TXOF_MASK 0x2u
-#define UART_SFIFO_TXOF_SHIFT 1
-#define UART_SFIFO_RXOF_MASK 0x4u
-#define UART_SFIFO_RXOF_SHIFT 2
-#define UART_SFIFO_RXEMPT_MASK 0x40u
-#define UART_SFIFO_RXEMPT_SHIFT 6
-#define UART_SFIFO_TXEMPT_MASK 0x80u
-#define UART_SFIFO_TXEMPT_SHIFT 7
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT 0
-#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT 0
-#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT 0
-#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT 0
-#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK 0x1u
-#define UART_C7816_ISO_7816E_SHIFT 0
-#define UART_C7816_TTYPE_MASK 0x2u
-#define UART_C7816_TTYPE_SHIFT 1
-#define UART_C7816_INIT_MASK 0x4u
-#define UART_C7816_INIT_SHIFT 2
-#define UART_C7816_ANACK_MASK 0x8u
-#define UART_C7816_ANACK_SHIFT 3
-#define UART_C7816_ONACK_MASK 0x10u
-#define UART_C7816_ONACK_SHIFT 4
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK 0x1u
-#define UART_IE7816_RXTE_SHIFT 0
-#define UART_IE7816_TXTE_MASK 0x2u
-#define UART_IE7816_TXTE_SHIFT 1
-#define UART_IE7816_GTVE_MASK 0x4u
-#define UART_IE7816_GTVE_SHIFT 2
-#define UART_IE7816_ADTE_MASK 0x8u
-#define UART_IE7816_ADTE_SHIFT 3
-#define UART_IE7816_INITDE_MASK 0x10u
-#define UART_IE7816_INITDE_SHIFT 4
-#define UART_IE7816_BWTE_MASK 0x20u
-#define UART_IE7816_BWTE_SHIFT 5
-#define UART_IE7816_CWTE_MASK 0x40u
-#define UART_IE7816_CWTE_SHIFT 6
-#define UART_IE7816_WTE_MASK 0x80u
-#define UART_IE7816_WTE_SHIFT 7
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK 0x1u
-#define UART_IS7816_RXT_SHIFT 0
-#define UART_IS7816_TXT_MASK 0x2u
-#define UART_IS7816_TXT_SHIFT 1
-#define UART_IS7816_GTV_MASK 0x4u
-#define UART_IS7816_GTV_SHIFT 2
-#define UART_IS7816_ADT_MASK 0x8u
-#define UART_IS7816_ADT_SHIFT 3
-#define UART_IS7816_INITD_MASK 0x10u
-#define UART_IS7816_INITD_SHIFT 4
-#define UART_IS7816_BWT_MASK 0x20u
-#define UART_IS7816_BWT_SHIFT 5
-#define UART_IS7816_CWT_MASK 0x40u
-#define UART_IS7816_CWT_SHIFT 6
-#define UART_IS7816_WT_MASK 0x80u
-#define UART_IS7816_WT_SHIFT 7
-/* WP7816 Bit Fields */
-#define UART_WP7816_WTX_MASK 0xFFu
-#define UART_WP7816_WTX_SHIFT 0
-#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK 0xFFu
-#define UART_WN7816_GTN_SHIFT 0
-#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK 0xFFu
-#define UART_WF7816_GTFD_SHIFT 0
-#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT 0
-#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT 4
-#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK 0xFFu
-#define UART_TL7816_TLEN_SHIFT 0
-#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-/* AP7816A_T0 Bit Fields */
-#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
-#define UART_AP7816A_T0_ADTI_H_SHIFT 0
-#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
-/* AP7816B_T0 Bit Fields */
-#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
-#define UART_AP7816B_T0_ADTI_L_SHIFT 0
-#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
-/* WP7816A_T0 Bit Fields */
-#define UART_WP7816A_T0_WI_H_MASK 0xFFu
-#define UART_WP7816A_T0_WI_H_SHIFT 0
-#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
-/* WP7816B_T0 Bit Fields */
-#define UART_WP7816B_T0_WI_L_MASK 0xFFu
-#define UART_WP7816B_T0_WI_L_SHIFT 0
-#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
-/* WP7816A_T1 Bit Fields */
-#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
-#define UART_WP7816A_T1_BWI_H_SHIFT 0
-#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
-/* WP7816B_T1 Bit Fields */
-#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
-#define UART_WP7816B_T1_BWI_L_SHIFT 0
-#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
-/* WGP7816_T1 Bit Fields */
-#define UART_WGP7816_T1_BGI_MASK 0xFu
-#define UART_WGP7816_T1_BGI_SHIFT 0
-#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
-#define UART_WGP7816_T1_CWI1_MASK 0xF0u
-#define UART_WGP7816_T1_CWI1_SHIFT 4
-#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
-/* WP7816C_T1 Bit Fields */
-#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
-#define UART_WP7816C_T1_CWI2_SHIFT 0
-#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
-
-/*!
- * @}
- */ /* end of group UART_Register_Masks */
-
-
-/* UART - Peripheral instance base addresses */
-/** Peripheral UART0 base address */
-#define UART0_BASE (0x4006A000u)
-/** Peripheral UART0 base pointer */
-#define UART0 ((UART_Type *)UART0_BASE)
-#define UART0_BASE_PTR (UART0)
-/** Peripheral UART1 base address */
-#define UART1_BASE (0x4006B000u)
-/** Peripheral UART1 base pointer */
-#define UART1 ((UART_Type *)UART1_BASE)
-#define UART1_BASE_PTR (UART1)
-/** Peripheral UART2 base address */
-#define UART2_BASE (0x4006C000u)
-/** Peripheral UART2 base pointer */
-#define UART2 ((UART_Type *)UART2_BASE)
-#define UART2_BASE_PTR (UART2)
-/** Array initializer of UART peripheral base addresses */
-#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
-/** Array initializer of UART peripheral base pointers */
-#define UART_BASE_PTRS { UART0, UART1, UART2 }
-/** Interrupt vectors for the UART peripheral type */
-#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
-#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register instance definitions */
-/* UART0 */
-#define UART0_BDH UART_BDH_REG(UART0)
-#define UART0_BDL UART_BDL_REG(UART0)
-#define UART0_C1 UART_C1_REG(UART0)
-#define UART0_C2 UART_C2_REG(UART0)
-#define UART0_S1 UART_S1_REG(UART0)
-#define UART0_S2 UART_S2_REG(UART0)
-#define UART0_C3 UART_C3_REG(UART0)
-#define UART0_D UART_D_REG(UART0)
-#define UART0_MA1 UART_MA1_REG(UART0)
-#define UART0_MA2 UART_MA2_REG(UART0)
-#define UART0_C4 UART_C4_REG(UART0)
-#define UART0_C5 UART_C5_REG(UART0)
-#define UART0_ED UART_ED_REG(UART0)
-#define UART0_MODEM UART_MODEM_REG(UART0)
-#define UART0_IR UART_IR_REG(UART0)
-#define UART0_PFIFO UART_PFIFO_REG(UART0)
-#define UART0_CFIFO UART_CFIFO_REG(UART0)
-#define UART0_SFIFO UART_SFIFO_REG(UART0)
-#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
-#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
-#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
-#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
-#define UART0_C7816 UART_C7816_REG(UART0)
-#define UART0_IE7816 UART_IE7816_REG(UART0)
-#define UART0_IS7816 UART_IS7816_REG(UART0)
-#define UART0_WP7816 UART_WP7816_REG(UART0)
-#define UART0_WN7816 UART_WN7816_REG(UART0)
-#define UART0_WF7816 UART_WF7816_REG(UART0)
-#define UART0_ET7816 UART_ET7816_REG(UART0)
-#define UART0_TL7816 UART_TL7816_REG(UART0)
-#define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
-#define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
-#define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
-#define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
-#define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
-#define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
-#define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
-#define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
-/* UART1 */
-#define UART1_BDH UART_BDH_REG(UART1)
-#define UART1_BDL UART_BDL_REG(UART1)
-#define UART1_C1 UART_C1_REG(UART1)
-#define UART1_C2 UART_C2_REG(UART1)
-#define UART1_S1 UART_S1_REG(UART1)
-#define UART1_S2 UART_S2_REG(UART1)
-#define UART1_C3 UART_C3_REG(UART1)
-#define UART1_D UART_D_REG(UART1)
-#define UART1_MA1 UART_MA1_REG(UART1)
-#define UART1_MA2 UART_MA2_REG(UART1)
-#define UART1_C4 UART_C4_REG(UART1)
-#define UART1_C5 UART_C5_REG(UART1)
-#define UART1_ED UART_ED_REG(UART1)
-#define UART1_MODEM UART_MODEM_REG(UART1)
-#define UART1_IR UART_IR_REG(UART1)
-#define UART1_PFIFO UART_PFIFO_REG(UART1)
-#define UART1_CFIFO UART_CFIFO_REG(UART1)
-#define UART1_SFIFO UART_SFIFO_REG(UART1)
-#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
-#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
-#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
-#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
-/* UART2 */
-#define UART2_BDH UART_BDH_REG(UART2)
-#define UART2_BDL UART_BDL_REG(UART2)
-#define UART2_C1 UART_C1_REG(UART2)
-#define UART2_C2 UART_C2_REG(UART2)
-#define UART2_S1 UART_S1_REG(UART2)
-#define UART2_S2 UART_S2_REG(UART2)
-#define UART2_C3 UART_C3_REG(UART2)
-#define UART2_D UART_D_REG(UART2)
-#define UART2_MA1 UART_MA1_REG(UART2)
-#define UART2_MA2 UART_MA2_REG(UART2)
-#define UART2_C4 UART_C4_REG(UART2)
-#define UART2_C5 UART_C5_REG(UART2)
-#define UART2_ED UART_ED_REG(UART2)
-#define UART2_MODEM UART_MODEM_REG(UART2)
-#define UART2_IR UART_IR_REG(UART2)
-#define UART2_PFIFO UART_PFIFO_REG(UART2)
-#define UART2_CFIFO UART_CFIFO_REG(UART2)
-#define UART2_SFIFO UART_SFIFO_REG(UART2)
-#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
-#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
-#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
-#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group UART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
- __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
- uint8_t RESERVED_0[3];
- __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
- uint8_t RESERVED_1[3];
- __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
- uint8_t RESERVED_2[3];
- __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
- uint8_t RESERVED_3[3];
- __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
- uint8_t RESERVED_4[3];
- __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
- uint8_t RESERVED_5[3];
- __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
- uint8_t RESERVED_6[3];
- __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
- uint8_t RESERVED_7[99];
- __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
- uint8_t RESERVED_8[3];
- __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
- uint8_t RESERVED_9[3];
- __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
- uint8_t RESERVED_10[3];
- __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
- uint8_t RESERVED_11[3];
- __I uint8_t STAT; /**< Status register, offset: 0x90 */
- uint8_t RESERVED_12[3];
- __IO uint8_t CTL; /**< Control register, offset: 0x94 */
- uint8_t RESERVED_13[3];
- __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
- uint8_t RESERVED_14[3];
- __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
- uint8_t RESERVED_15[3];
- __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
- uint8_t RESERVED_16[3];
- __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
- uint8_t RESERVED_17[3];
- __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
- uint8_t RESERVED_18[3];
- __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
- uint8_t RESERVED_19[3];
- __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
- uint8_t RESERVED_20[3];
- __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
- uint8_t RESERVED_21[11];
- struct { /* offset: 0xC0, array step: 0x4 */
- __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_0[3];
- } ENDPOINT[16];
- __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
- uint8_t RESERVED_22[3];
- __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
- uint8_t RESERVED_23[3];
- __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
- uint8_t RESERVED_24[3];
- __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
- uint8_t RESERVED_25[7];
- __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
- uint8_t RESERVED_26[43];
- __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
- uint8_t RESERVED_27[3];
- __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
- uint8_t RESERVED_28[23];
- __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
-} USB_Type, *USB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register accessors */
-#define USB_PERID_REG(base) ((base)->PERID)
-#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
-#define USB_REV_REG(base) ((base)->REV)
-#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
-#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
-#define USB_OTGICR_REG(base) ((base)->OTGICR)
-#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
-#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
-#define USB_ISTAT_REG(base) ((base)->ISTAT)
-#define USB_INTEN_REG(base) ((base)->INTEN)
-#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
-#define USB_ERREN_REG(base) ((base)->ERREN)
-#define USB_STAT_REG(base) ((base)->STAT)
-#define USB_CTL_REG(base) ((base)->CTL)
-#define USB_ADDR_REG(base) ((base)->ADDR)
-#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
-#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
-#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
-#define USB_TOKEN_REG(base) ((base)->TOKEN)
-#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
-#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
-#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
-#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
-#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
-#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
-#define USB_CONTROL_REG(base) ((base)->CONTROL)
-#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
-#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
-#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
-#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
-#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT 0
-#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
-/* CLK_RECOVER_CTRL Bit Fields */
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
-/* CLK_RECOVER_IRC_EN Bit Fields */
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
-/* CLK_RECOVER_INT_STATUS Bit Fields */
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
-
-/*!
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x40072000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-#define USB0_BASE_PTR (USB0)
-/** Array initializer of USB peripheral base addresses */
-#define USB_BASE_ADDRS { USB0_BASE }
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASE_PTRS { USB0 }
-/** Interrupt vectors for the USB peripheral type */
-#define USB_IRQS { USB0_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register instance definitions */
-/* USB0 */
-#define USB0_PERID USB_PERID_REG(USB0)
-#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
-#define USB0_REV USB_REV_REG(USB0)
-#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
-#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
-#define USB0_OTGICR USB_OTGICR_REG(USB0)
-#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
-#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
-#define USB0_ISTAT USB_ISTAT_REG(USB0)
-#define USB0_INTEN USB_INTEN_REG(USB0)
-#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
-#define USB0_ERREN USB_ERREN_REG(USB0)
-#define USB0_STAT USB_STAT_REG(USB0)
-#define USB0_CTL USB_CTL_REG(USB0)
-#define USB0_ADDR USB_ADDR_REG(USB0)
-#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
-#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
-#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
-#define USB0_TOKEN USB_TOKEN_REG(USB0)
-#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
-#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
-#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
-#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
-#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
-#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
-#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
-#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
-#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
-#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
-#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
-#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
-#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
-#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
-#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
-#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
-#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
-#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
-#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
-#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
-#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
-#define USB0_CONTROL USB_CONTROL_REG(USB0)
-#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
-#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
-#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
-#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
-#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
-
-/* USB - Register array accessors */
-#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- VREF Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
- * @{
- */
-
-/** VREF - Register Layout Typedef */
-typedef struct {
- __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
- __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type, *VREF_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register accessors */
-#define VREF_TRM_REG(base) ((base)->TRM)
-#define VREF_SC_REG(base) ((base)->SC)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- VREF Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Masks VREF Register Masks
- * @{
- */
-
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK 0x3Fu
-#define VREF_TRM_TRIM_SHIFT 0
-#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK 0x40u
-#define VREF_TRM_CHOPEN_SHIFT 6
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK 0x3u
-#define VREF_SC_MODE_LV_SHIFT 0
-#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK 0x4u
-#define VREF_SC_VREFST_SHIFT 2
-#define VREF_SC_ICOMPEN_MASK 0x20u
-#define VREF_SC_ICOMPEN_SHIFT 5
-#define VREF_SC_REGEN_MASK 0x40u
-#define VREF_SC_REGEN_SHIFT 6
-#define VREF_SC_VREFEN_MASK 0x80u
-#define VREF_SC_VREFEN_SHIFT 7
-
-/*!
- * @}
- */ /* end of group VREF_Register_Masks */
-
-
-/* VREF - Peripheral instance base addresses */
-/** Peripheral VREF base address */
-#define VREF_BASE (0x40074000u)
-/** Peripheral VREF base pointer */
-#define VREF ((VREF_Type *)VREF_BASE)
-#define VREF_BASE_PTR (VREF)
-/** Array initializer of VREF peripheral base addresses */
-#define VREF_BASE_ADDRS { VREF_BASE }
-/** Array initializer of VREF peripheral base pointers */
-#define VREF_BASE_PTRS { VREF }
-
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register instance definitions */
-/* VREF */
-#define VREF_TRM VREF_TRM_REG(VREF)
-#define VREF_SC VREF_SC_REG(VREF)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group VREF_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- WDOG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
- * @{
- */
-
-/** WDOG - Register Layout Typedef */
-typedef struct {
- __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
- __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
- __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
- __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
- __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
- __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
- __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
- __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
- __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
- __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
- __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
- __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
-} WDOG_Type, *WDOG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register accessors */
-#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
-#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
-#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
-#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
-#define WDOG_WINH_REG(base) ((base)->WINH)
-#define WDOG_WINL_REG(base) ((base)->WINL)
-#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
-#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
-#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
-#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
-#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
-#define WDOG_PRESC_REG(base) ((base)->PRESC)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- WDOG Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Masks WDOG Register Masks
- * @{
- */
-
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT 0
-#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT 1
-#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
-#define WDOG_STCTRLH_WINEN_MASK 0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT 3
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
-#define WDOG_STCTRLH_DBGEN_MASK 0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT 5
-#define WDOG_STCTRLH_STOPEN_MASK 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT 6
-#define WDOG_STCTRLH_WAITEN_MASK 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT 7
-#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
-#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT 11
-#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT 12
-#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT 15
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
-#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT 0
-#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT 0
-#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK 0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT 0
-#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
-#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
-#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
-#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
-#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT 0
-#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT 8
-#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Masks */
-
-
-/* WDOG - Peripheral instance base addresses */
-/** Peripheral WDOG base address */
-#define WDOG_BASE (0x40052000u)
-/** Peripheral WDOG base pointer */
-#define WDOG ((WDOG_Type *)WDOG_BASE)
-#define WDOG_BASE_PTR (WDOG)
-/** Array initializer of WDOG peripheral base addresses */
-#define WDOG_BASE_ADDRS { WDOG_BASE }
-/** Array initializer of WDOG peripheral base pointers */
-#define WDOG_BASE_PTRS { WDOG }
-/** Interrupt vectors for the WDOG peripheral type */
-#define WDOG_IRQS { Watchdog_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register instance definitions */
-/* WDOG */
-#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
-#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
-#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
-#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
-#define WDOG_WINH WDOG_WINH_REG(WDOG)
-#define WDOG_WINL WDOG_WINL_REG(WDOG)
-#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
-#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
-#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
-#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
-#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
-#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group WDOG_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma pop
-#elif defined(__CWCC__)
- #pragma pop
-#elif defined(__GNUC__)
- /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=default
-#else
- #error Not supported compiler type
-#endif
-
-/*!
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
- -- Backward Compatibility
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
- * @{
- */
-
-#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
-#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
-#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
-#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
-#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
-#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
-#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
-#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
-#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
-#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
-#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
-#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
-#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
-#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
-#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
-#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
-#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
-#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
-#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
-#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
-#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
-#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
-#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
-#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
-#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
-#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
-#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
-#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
-#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
-#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
-#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
-#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
-#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
-#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
-#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
-
-/*!
- * @}
- */ /* end of group Backward_Compatibility_Symbols */
-
-
-#else /* #if !defined(MK22F51212_H_) */
- /* There is already included the same memory map. Check if it is compatible (has the same major version) */
- #if (MCU_MEM_MAP_VERSION != 0x0200u)
- #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
- #warning There are included two not compatible versions of memory maps. Please check possible differences.
- #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
- #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
-#endif /* #if !defined(MK22F51212_H_) */
-
-/* MK22F51212.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct
deleted file mode 100644
index 710144bf3..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct
+++ /dev/null
@@ -1,13 +0,0 @@
-
-LR_IROM1 0x00000000 0x80000 { ; load region size_region (512k)
- ER_IROM1 0x00000000 0x80000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
- ; 0x20000 - 0x198 = 0x1FE68
- RW_IRAM1 0x1FFF0198 0x1FE68 {
- .ANY (+RW +ZI)
- }
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s
deleted file mode 100644
index 5c53006d0..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s
+++ /dev/null
@@ -1,679 +0,0 @@
-;/*****************************************************************************
-; * @file: startup_MK22F12.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
-; * MK22F12
-; * @version: 1.5
-; * @date: 2013-5-16
-; *
-; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
-;*
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-__initial_sp EQU 0x20010000 ; Top of RAM
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
- DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
- DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
- DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
- DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
- DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
- DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
- DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
- DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
- DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
- DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
- DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
- DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
- DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
- DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
- DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
- DCD DMA_Error_IRQHandler ; DMA Error Interrupt
- DCD MCM_IRQHandler ; Normal Interrupt
- DCD FTFE_IRQHandler ; FTFE Command complete interrupt
- DCD Read_Collision_IRQHandler ; Read Collision Interrupt
- DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
- DCD LLW_IRQHandler ; Low Leakage Wakeup
- DCD Watchdog_IRQHandler ; WDOG Interrupt
- DCD Reserved39_IRQHandler ; Reserved Interrupt 39
- DCD I2C0_IRQHandler ; I2C0 interrupt
- DCD I2C1_IRQHandler ; I2C1 interrupt
- DCD SPI0_IRQHandler ; SPI0 Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupt
- DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
- DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
- DCD UART0_LON_IRQHandler ; UART0 LON interrupt
- DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
- DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
- DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
- DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
- DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
- DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
- DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
- DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
- DCD ADC0_IRQHandler ; ADC0 interrupt
- DCD CMP0_IRQHandler ; CMP0 interrupt
- DCD CMP1_IRQHandler ; CMP1 interrupt
- DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
- DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
- DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
- DCD CMT_IRQHandler ; CMT interrupt
- DCD RTC_IRQHandler ; RTC interrupt
- DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
- DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
- DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
- DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
- DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
- DCD PDB0_IRQHandler ; PDB0 Interrupt
- DCD USB0_IRQHandler ; USB0 interrupt
- DCD USBDCD_IRQHandler ; USBDCD Interrupt
- DCD Reserved71_IRQHandler ; Reserved interrupt 71
- DCD DAC0_IRQHandler ; DAC0 interrupt
- DCD MCG_IRQHandler ; MCG Interrupt
- DCD LPTimer_IRQHandler ; LPTimer interrupt
- DCD PORTA_IRQHandler ; Port A interrupt
- DCD PORTB_IRQHandler ; Port B interrupt
- DCD PORTC_IRQHandler ; Port C interrupt
- DCD PORTD_IRQHandler ; Port D interrupt
- DCD PORTE_IRQHandler ; Port E interrupt
- DCD SWI_IRQHandler ; Software interrupt
- DCD SPI2_IRQHandler ; SPI2 Interrupt
- DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
- DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
- DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
- DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
- DCD CMP2_IRQHandler ; CMP2 interrupt
- DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
- DCD DAC1_IRQHandler ; DAC1 interrupt
- DCD ADC1_IRQHandler ; ADC1 interrupt
- DCD I2C2_IRQHandler ; I2C2 interrupt
- DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
- DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
- DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
- DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
- DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
- DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
- DCD SDHC_IRQHandler ; SDHC interrupt
- DCD DefaultISR ; 98
- DCD DefaultISR ; 99
- DCD DefaultISR ; 100
- DCD DefaultISR ; 101
- DCD DefaultISR ; 102
- DCD DefaultISR ; 103
- DCD DefaultISR ; 104
- DCD DefaultISR ; 105
- DCD DefaultISR ; 106
- DCD DefaultISR ; 107
- DCD DefaultISR ; 108
- DCD DefaultISR ; 109
- DCD DefaultISR ; 110
- DCD DefaultISR ; 111
- DCD DefaultISR ; 112
- DCD DefaultISR ; 113
- DCD DefaultISR ; 114
- DCD DefaultISR ; 115
- DCD DefaultISR ; 116
- DCD DefaultISR ; 117
- DCD DefaultISR ; 118
- DCD DefaultISR ; 119
- DCD DefaultISR ; 120
- DCD DefaultISR ; 121
- DCD DefaultISR ; 122
- DCD DefaultISR ; 123
- DCD DefaultISR ; 124
- DCD DefaultISR ; 125
- DCD DefaultISR ; 126
- DCD DefaultISR ; 127
- DCD DefaultISR ; 128
- DCD DefaultISR ; 129
- DCD DefaultISR ; 130
- DCD DefaultISR ; 131
- DCD DefaultISR ; 132
- DCD DefaultISR ; 133
- DCD DefaultISR ; 134
- DCD DefaultISR ; 135
- DCD DefaultISR ; 136
- DCD DefaultISR ; 137
- DCD DefaultISR ; 138
- DCD DefaultISR ; 139
- DCD DefaultISR ; 140
- DCD DefaultISR ; 141
- DCD DefaultISR ; 142
- DCD DefaultISR ; 143
- DCD DefaultISR ; 144
- DCD DefaultISR ; 145
- DCD DefaultISR ; 146
- DCD DefaultISR ; 147
- DCD DefaultISR ; 148
- DCD DefaultISR ; 149
- DCD DefaultISR ; 150
- DCD DefaultISR ; 151
- DCD DefaultISR ; 152
- DCD DefaultISR ; 153
- DCD DefaultISR ; 154
- DCD DefaultISR ; 155
- DCD DefaultISR ; 156
- DCD DefaultISR ; 157
- DCD DefaultISR ; 158
- DCD DefaultISR ; 159
- DCD DefaultISR ; 160
- DCD DefaultISR ; 161
- DCD DefaultISR ; 162
- DCD DefaultISR ; 163
- DCD DefaultISR ; 164
- DCD DefaultISR ; 165
- DCD DefaultISR ; 166
- DCD DefaultISR ; 167
- DCD DefaultISR ; 168
- DCD DefaultISR ; 169
- DCD DefaultISR ; 170
- DCD DefaultISR ; 171
- DCD DefaultISR ; 172
- DCD DefaultISR ; 173
- DCD DefaultISR ; 174
- DCD DefaultISR ; 175
- DCD DefaultISR ; 176
- DCD DefaultISR ; 177
- DCD DefaultISR ; 178
- DCD DefaultISR ; 179
- DCD DefaultISR ; 180
- DCD DefaultISR ; 181
- DCD DefaultISR ; 182
- DCD DefaultISR ; 183
- DCD DefaultISR ; 184
- DCD DefaultISR ; 185
- DCD DefaultISR ; 186
- DCD DefaultISR ; 187
- DCD DefaultISR ; 188
- DCD DefaultISR ; 189
- DCD DefaultISR ; 190
- DCD DefaultISR ; 191
- DCD DefaultISR ; 192
- DCD DefaultISR ; 193
- DCD DefaultISR ; 194
- DCD DefaultISR ; 195
- DCD DefaultISR ; 196
- DCD DefaultISR ; 197
- DCD DefaultISR ; 198
- DCD DefaultISR ; 199
- DCD DefaultISR ; 200
- DCD DefaultISR ; 201
- DCD DefaultISR ; 202
- DCD DefaultISR ; 203
- DCD DefaultISR ; 204
- DCD DefaultISR ; 205
- DCD DefaultISR ; 206
- DCD DefaultISR ; 207
- DCD DefaultISR ; 208
- DCD DefaultISR ; 209
- DCD DefaultISR ; 210
- DCD DefaultISR ; 211
- DCD DefaultISR ; 212
- DCD DefaultISR ; 213
- DCD DefaultISR ; 214
- DCD DefaultISR ; 215
- DCD DefaultISR ; 216
- DCD DefaultISR ; 217
- DCD DefaultISR ; 218
- DCD DefaultISR ; 219
- DCD DefaultISR ; 220
- DCD DefaultISR ; 221
- DCD DefaultISR ; 222
- DCD DefaultISR ; 223
- DCD DefaultISR ; 224
- DCD DefaultISR ; 225
- DCD DefaultISR ; 226
- DCD DefaultISR ; 227
- DCD DefaultISR ; 228
- DCD DefaultISR ; 229
- DCD DefaultISR ; 230
- DCD DefaultISR ; 231
- DCD DefaultISR ; 232
- DCD DefaultISR ; 233
- DCD DefaultISR ; 234
- DCD DefaultISR ; 235
- DCD DefaultISR ; 236
- DCD DefaultISR ; 237
- DCD DefaultISR ; 238
- DCD DefaultISR ; 239
- DCD DefaultISR ; 240
- DCD DefaultISR ; 241
- DCD DefaultISR ; 242
- DCD DefaultISR ; 243
- DCD DefaultISR ; 244
- DCD DefaultISR ; 245
- DCD DefaultISR ; 246
- DCD DefaultISR ; 247
- DCD DefaultISR ; 248
- DCD DefaultISR ; 249
- DCD DefaultISR ; 250
- DCD DefaultISR ; 251
- DCD DefaultISR ; 252
- DCD DefaultISR ; 253
- DCD DefaultISR ; 254
- DCD DefaultISR ; 255
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-; <h> Flash Configuration
-; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
-; <i> and security information that allows the MCU to restrict acces to the FTFL module.
-; <h> Backdoor Comparison Key
-; <o0> Backdoor Key 0 <0x0-0xFF:2>
-; <o1> Backdoor Key 1 <0x0-0xFF:2>
-; <o2> Backdoor Key 2 <0x0-0xFF:2>
-; <o3> Backdoor Key 3 <0x0-0xFF:2>
-; <o4> Backdoor Key 4 <0x0-0xFF:2>
-; <o5> Backdoor Key 5 <0x0-0xFF:2>
-; <o6> Backdoor Key 6 <0x0-0xFF:2>
-; <o7> Backdoor Key 7 <0x0-0xFF:2>
-BackDoorK0 EQU 0xFF
-BackDoorK1 EQU 0xFF
-BackDoorK2 EQU 0xFF
-BackDoorK3 EQU 0xFF
-BackDoorK4 EQU 0xFF
-BackDoorK5 EQU 0xFF
-BackDoorK6 EQU 0xFF
-BackDoorK7 EQU 0xFF
-; </h>
-; <h> Program flash protection bytes (FPROT)
-; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-; <i> Each bit protects a 1/32 region of the program flash memory.
-; <h> FPROT0
-; <i> Program flash protection bytes
-; <i> 1/32 - 8/32 region
-; <o.0> FPROT0.0
-; <o.1> FPROT0.1
-; <o.2> FPROT0.2
-; <o.3> FPROT0.3
-; <o.4> FPROT0.4
-; <o.5> FPROT0.5
-; <o.6> FPROT0.6
-; <o.7> FPROT0.7
-nFPROT0 EQU 0x00
-FPROT0 EQU nFPROT0:EOR:0xFF
-; </h>
-; <h> FPROT1
-; <i> Program Flash Region Protect Register 1
-; <i> 9/32 - 16/32 region
-; <o.0> FPROT1.0
-; <o.1> FPROT1.1
-; <o.2> FPROT1.2
-; <o.3> FPROT1.3
-; <o.4> FPROT1.4
-; <o.5> FPROT1.5
-; <o.6> FPROT1.6
-; <o.7> FPROT1.7
-nFPROT1 EQU 0x00
-FPROT1 EQU nFPROT1:EOR:0xFF
-; </h>
-; <h> FPROT2
-; <i> Program Flash Region Protect Register 2
-; <i> 17/32 - 24/32 region
-; <o.0> FPROT2.0
-; <o.1> FPROT2.1
-; <o.2> FPROT2.2
-; <o.3> FPROT2.3
-; <o.4> FPROT2.4
-; <o.5> FPROT2.5
-; <o.6> FPROT2.6
-; <o.7> FPROT2.7
-nFPROT2 EQU 0x00
-FPROT2 EQU nFPROT2:EOR:0xFF
-; </h>
-; <h> FPROT3
-; <i> Program Flash Region Protect Register 3
-; <i> 25/32 - 32/32 region
-; <o.0> FPROT3.0
-; <o.1> FPROT3.1
-; <o.2> FPROT3.2
-; <o.3> FPROT3.3
-; <o.4> FPROT3.4
-; <o.5> FPROT3.5
-; <o.6> FPROT3.6
-; <o.7> FPROT3.7
-nFPROT3 EQU 0x00
-FPROT3 EQU nFPROT3:EOR:0xFF
-; </h>
-; </h>
-; <h> Data flash protection byte (FDPROT)
-; <i> Each bit protects a 1/8 region of the data flash memory.
-; <i> (Program flash only devices: Reserved)
-; <o.0> FDPROT.0
-; <o.1> FDPROT.1
-; <o.2> FDPROT.2
-; <o.3> FDPROT.3
-; <o.4> FDPROT.4
-; <o.5> FDPROT.5
-; <o.6> FDPROT.6
-; <o.7> FDPROT.7
-nFDPROT EQU 0x00
-FDPROT EQU nFDPROT:EOR:0xFF
-; </h>
-; <h> EEPROM protection byte (FEPROT)
-; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
-; <i> (Program flash only devices: Reserved)
-; <o.0> FEPROT.0
-; <o.1> FEPROT.1
-; <o.2> FEPROT.2
-; <o.3> FEPROT.3
-; <o.4> FEPROT.4
-; <o.5> FEPROT.5
-; <o.6> FEPROT.6
-; <o.7> FEPROT.7
-nFEPROT EQU 0x00
-FEPROT EQU nFEPROT:EOR:0xFF
-; </h>
-; <h> Flash nonvolatile option byte (FOPT)
-; <i> Allows the user to customize the operation of the MCU at boot time.
-; <o.0> LPBOOT
-; <0=> Low-power boot
-; <1=> normal boot
-; <o.1> EZPORT_DIS
-; <0=> EzPort operation is enabled
-; <1=> EzPort operation is disabled
-FOPT EQU 0xFF
-; </h>
-; <h> Flash security byte (FSEC)
-; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-; <o.0..1> SEC
-; <2=> MCU security status is unsecure
-; <3=> MCU security status is secure
-; <i> Flash Security
-; <i> This bits define the security state of the MCU.
-; <o.2..3> FSLACC
-; <2=> Freescale factory access denied
-; <3=> Freescale factory access granted
-; <i> Freescale Failure Analysis Access Code
-; <i> This bits define the security state of the MCU.
-; <o.4..5> MEEN
-; <2=> Mass erase is disabled
-; <3=> Mass erase is enabled
-; <i> Mass Erase Enable Bits
-; <i> Enables and disables mass erase capability of the FTFL module
-; <o.6..7> KEYEN
-; <2=> Backdoor key access enabled
-; <3=> Backdoor key access disabled
-; <i> Backdoor key Security Enable
-; <i> These bits enable and disable backdoor key access to the FTFL module.
-FSEC EQU 0xFE
-; </h>
-; </h>
- IF :LNOT::DEF:RAM_TARGET
- AREA |.ARM.__at_0x400|, CODE, READONLY
- DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
- DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
- DCB FPROT0, FPROT1, FPROT2, FPROT3
- DCB FSEC, FOPT, FEPROT, FDPROT
- ENDIF
-
- AREA |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT DMA0_IRQHandler [WEAK]
- EXPORT DMA1_IRQHandler [WEAK]
- EXPORT DMA2_IRQHandler [WEAK]
- EXPORT DMA3_IRQHandler [WEAK]
- EXPORT DMA4_IRQHandler [WEAK]
- EXPORT DMA5_IRQHandler [WEAK]
- EXPORT DMA6_IRQHandler [WEAK]
- EXPORT DMA7_IRQHandler [WEAK]
- EXPORT DMA8_IRQHandler [WEAK]
- EXPORT DMA9_IRQHandler [WEAK]
- EXPORT DMA10_IRQHandler [WEAK]
- EXPORT DMA11_IRQHandler [WEAK]
- EXPORT DMA12_IRQHandler [WEAK]
- EXPORT DMA13_IRQHandler [WEAK]
- EXPORT DMA14_IRQHandler [WEAK]
- EXPORT DMA15_IRQHandler [WEAK]
- EXPORT DMA_Error_IRQHandler [WEAK]
- EXPORT MCM_IRQHandler [WEAK]
- EXPORT FTFE_IRQHandler [WEAK]
- EXPORT Read_Collision_IRQHandler [WEAK]
- EXPORT LVD_LVW_IRQHandler [WEAK]
- EXPORT LLW_IRQHandler [WEAK]
- EXPORT Watchdog_IRQHandler [WEAK]
- EXPORT Reserved39_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT I2S0_Tx_IRQHandler [WEAK]
- EXPORT I2S0_Rx_IRQHandler [WEAK]
- EXPORT UART0_LON_IRQHandler [WEAK]
- EXPORT UART0_RX_TX_IRQHandler [WEAK]
- EXPORT UART0_ERR_IRQHandler [WEAK]
- EXPORT UART1_RX_TX_IRQHandler [WEAK]
- EXPORT UART1_ERR_IRQHandler [WEAK]
- EXPORT UART2_RX_TX_IRQHandler [WEAK]
- EXPORT UART2_ERR_IRQHandler [WEAK]
- EXPORT UART3_RX_TX_IRQHandler [WEAK]
- EXPORT UART3_ERR_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT CMP0_IRQHandler [WEAK]
- EXPORT CMP1_IRQHandler [WEAK]
- EXPORT FTM0_IRQHandler [WEAK]
- EXPORT FTM1_IRQHandler [WEAK]
- EXPORT FTM2_IRQHandler [WEAK]
- EXPORT CMT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT RTC_Seconds_IRQHandler [WEAK]
- EXPORT PIT0_IRQHandler [WEAK]
- EXPORT PIT1_IRQHandler [WEAK]
- EXPORT PIT2_IRQHandler [WEAK]
- EXPORT PIT3_IRQHandler [WEAK]
- EXPORT PDB0_IRQHandler [WEAK]
- EXPORT USB0_IRQHandler [WEAK]
- EXPORT USBDCD_IRQHandler [WEAK]
- EXPORT Reserved71_IRQHandler [WEAK]
- EXPORT DAC0_IRQHandler [WEAK]
- EXPORT MCG_IRQHandler [WEAK]
- EXPORT LPTimer_IRQHandler [WEAK]
- EXPORT PORTA_IRQHandler [WEAK]
- EXPORT PORTB_IRQHandler [WEAK]
- EXPORT PORTC_IRQHandler [WEAK]
- EXPORT PORTD_IRQHandler [WEAK]
- EXPORT PORTE_IRQHandler [WEAK]
- EXPORT SWI_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT UART4_RX_TX_IRQHandler [WEAK]
- EXPORT UART4_ERR_IRQHandler [WEAK]
- EXPORT UART5_RX_TX_IRQHandler [WEAK]
- EXPORT UART5_ERR_IRQHandler [WEAK]
- EXPORT CMP2_IRQHandler [WEAK]
- EXPORT FTM3_IRQHandler [WEAK]
- EXPORT DAC1_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT I2C2_IRQHandler [WEAK]
- EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
- EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
- EXPORT CAN0_Error_IRQHandler [WEAK]
- EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
- EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
- EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
- EXPORT SDHC_IRQHandler [WEAK]
- EXPORT DefaultISR [WEAK]
-
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-DMA4_IRQHandler
-DMA5_IRQHandler
-DMA6_IRQHandler
-DMA7_IRQHandler
-DMA8_IRQHandler
-DMA9_IRQHandler
-DMA10_IRQHandler
-DMA11_IRQHandler
-DMA12_IRQHandler
-DMA13_IRQHandler
-DMA14_IRQHandler
-DMA15_IRQHandler
-DMA_Error_IRQHandler
-MCM_IRQHandler
-FTFE_IRQHandler
-Read_Collision_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-Watchdog_IRQHandler
-Reserved39_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-I2S0_Tx_IRQHandler
-I2S0_Rx_IRQHandler
-UART0_LON_IRQHandler
-UART0_RX_TX_IRQHandler
-UART0_ERR_IRQHandler
-UART1_RX_TX_IRQHandler
-UART1_ERR_IRQHandler
-UART2_RX_TX_IRQHandler
-UART2_ERR_IRQHandler
-UART3_RX_TX_IRQHandler
-UART3_ERR_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-CMP1_IRQHandler
-FTM0_IRQHandler
-FTM1_IRQHandler
-FTM2_IRQHandler
-CMT_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT0_IRQHandler
-PIT1_IRQHandler
-PIT2_IRQHandler
-PIT3_IRQHandler
-PDB0_IRQHandler
-USB0_IRQHandler
-USBDCD_IRQHandler
-Reserved71_IRQHandler
-DAC0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-PORTA_IRQHandler
-PORTB_IRQHandler
-PORTC_IRQHandler
-PORTD_IRQHandler
-PORTE_IRQHandler
-SWI_IRQHandler
-SPI2_IRQHandler
-UART4_RX_TX_IRQHandler
-UART4_ERR_IRQHandler
-UART5_RX_TX_IRQHandler
-UART5_ERR_IRQHandler
-CMP2_IRQHandler
-FTM3_IRQHandler
-DAC1_IRQHandler
-ADC1_IRQHandler
-I2C2_IRQHandler
-CAN0_ORed_Message_buffer_IRQHandler
-CAN0_Bus_Off_IRQHandler
-CAN0_Error_IRQHandler
-CAN0_Tx_Warning_IRQHandler
-CAN0_Rx_Warning_IRQHandler
-CAN0_Wake_Up_IRQHandler
-SDHC_IRQHandler
-DefaultISR
-
- B .
-
- ENDP
-
-
- ALIGN
- END
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp
deleted file mode 100644
index b129b2c2a..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp
+++ /dev/null
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld
deleted file mode 100644
index b7b3fe61c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * K64F ARM GCC linker script file
- */
-
-MEMORY
-{
- VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
- FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
- FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x000080000 - 0x00000410
- RAM (rwx) : ORIGIN = 0x1FFF0400, LENGTH = 0x000020000 - 0x00000400
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * _reset_init : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .isr_vector :
- {
- __vector_table = .;
- KEEP(*(.vector_table))
- *(.text.Reset_Handler)
- *(.text.System_Init)
- . = ALIGN(4);
- } > VECTORS
-
- .flash_protect :
- {
- KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
- } > FLASH_PROTECTION
-
- .text :
- {
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
-
- } > RAM
-
- .bss :
- {
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- __bss_end__ = .;
- } > RAM
-
- .heap :
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy :
- {
- *(.stack)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
-
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S
deleted file mode 100644
index 2b5675164..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S
+++ /dev/null
@@ -1,369 +0,0 @@
-/* K64F startup ARM GCC
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V1.2
- * Date: 15 Nov 2011
- *
- * Copyright (c) 2011, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of the ARM Limited nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- .syntax unified
- .arch armv7-m
-
-/* Memory Model
- The HEAP starts at the end of the DATA section and grows upward.
-
- The STACK starts at the end of the RAM and grows downward.
-
- The HEAP and stack STACK are only checked at compile time:
- (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
-
- This is just a check for the bare minimum for the Heap+Stack area before
- aborting compilation, it is not the run time limit:
- Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
- */
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0xC00
-#endif
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x400
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .space Heap_Size
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .vector_table,"a",%progbits
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External Interrupts */
- .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
- .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
- .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
- .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
- .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/
- .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/
- .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/
- .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/
- .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/
- .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/
- .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/
- .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/
- .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/
- .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/
- .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/
- .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/
- .long DMA_Error_IRQHandler /* DMA Error Interrupt*/
- .long MCM_IRQHandler /* Normal Interrupt*/
- .long FTF_IRQHandler /* FTFA Command complete interrupt*/
- .long Read_Collision_IRQHandler /* Read Collision Interrupt*/
- .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
- .long LLW_IRQHandler /* Low Leakage Wakeup*/
- .long Watchdog_IRQHandler /* WDOG Interrupt*/
- .long RNG_IRQHandler /* RNG Interrupt*/
- .long I2C0_IRQHandler /* I2C0 interrupt*/
- .long I2C1_IRQHandler /* I2C1 interrupt*/
- .long SPI0_IRQHandler /* SPI0 Interrupt*/
- .long SPI1_IRQHandler /* SPI1 Interrupt*/
- .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
- .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
- .long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/
- .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
- .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
- .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
- .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
- .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
- .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
- .long Reserved53_IRQHandler /* Reserved interrupt 53*/
- .long Reserved54_IRQHandler /* Reserved interrupt 54*/
- .long ADC0_IRQHandler /* ADC0 interrupt*/
- .long CMP0_IRQHandler /* CMP0 interrupt*/
- .long CMP1_IRQHandler /* CMP1 interrupt*/
- .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
- .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
- .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
- .long Reserved61_IRQHandler /* Reserved interrupt 61*/
- .long RTC_IRQHandler /* RTC interrupt*/
- .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
- .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
- .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
- .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
- .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
- .long PDB0_IRQHandler /* PDB0 Interrupt*/
- .long USB0_IRQHandler /* USB0 interrupt*/
- .long Reserved70_IRQHandler /* Reserved interrupt 70*/
- .long Reserved71_IRQHandler /* Reserved interrupt 71*/
- .long DAC0_IRQHandler /* DAC0 interrupt*/
- .long MCG_IRQHandler /* MCG Interrupt*/
- .long LPTimer_IRQHandler /* LPTimer interrupt*/
- .long PORTA_IRQHandler /* Port A interrupt*/
- .long PORTB_IRQHandler /* Port B interrupt*/
- .long PORTC_IRQHandler /* Port C interrupt*/
- .long PORTD_IRQHandler /* Port D interrupt*/
- .long PORTE_IRQHandler /* Port E interrupt*/
- .long SWI_IRQHandler /* Software interrupt*/
- .long Reserved81_IRQHandler /* Reserved interrupt 81*/
- .long Reserved82_IRQHandler /* Reserved interrupt 82*/
- .long Reserved83_IRQHandler /* Reserved interrupt 83*/
- .long Reserved84_IRQHandler /* Reserved interrupt 84*/
- .long Reserved85_IRQHandler /* Reserved interrupt 85*/
- .long Reserved86_IRQHandler /* Reserved interrupt 86*/
- .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
- .long DAC1_IRQHandler /* DAC1 interrupt*/
- .long ADC1_IRQHandler /* ADC1 interrupt*/
- .long Reserved90_IRQHandler /* Reserved Interrupt 90*/
- .long Reserved91_IRQHandler /* Reserved Interrupt 91*/
- .long Reserved92_IRQHandler /* Reserved Interrupt 92*/
- .long Reserved93_IRQHandler /* Reserved Interrupt 93*/
- .long Reserved94_IRQHandler /* Reserved Interrupt 94*/
- .long Reserved95_IRQHandler /* Reserved Interrupt 95*/
- .long Reserved96_IRQHandler /* Reserved Interrupt 96*/
- .long Reserved97_IRQHandler /* Reserved Interrupt 97*/
- .long Reserved98_IRQHandler /* Reserved Interrupt 98*/
- .long Reserved99_IRQHandler /* Reserved Interrupt 99*/
- .long Reserved100_IRQHandler /* Reserved Interrupt 100*/
- .long Reserved101_IRQHandler /* Reserved Interrupt 101*/
-
- .size __isr_vector, . - __isr_vector
-
- .section .text.Reset_Handler
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
-
-disable_watchdog:
- /* unlock */
- ldr r1, =0x4005200e
- ldr r0, =0xc520
- strh r0, [r1]
- ldr r0, =0xd928
- strh r0, [r1]
- /* disable */
- ldr r1, =0x40052000
- ldr r0, =0x01d2
- strh r0, [r1]
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .Lflash_to_ram_loop_end
-
- movs r4, 0
-.Lflash_to_ram_loop:
- ldr r0, [r1,r4]
- str r0, [r2,r4]
- adds r4, 4
- cmp r4, r3
- blt .Lflash_to_ram_loop
-.Lflash_to_ram_loop_end:
-
- ldr r0, =SystemInit
- blx r0
- ldr r0, =_start
- bx r0
- .pool
- .size Reset_Handler, . - Reset_Handler
-
- .text
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_default_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- .type \handler_name, %function
-\handler_name :
- b .
- .size \handler_name, . - \handler_name
- .endm
-
-/* Exception Handlers */
-
- def_default_handler NMI_Handler
- def_default_handler HardFault_Handler
- def_default_handler MemManage_Handler
- def_default_handler BusFault_Handler
- def_default_handler UsageFault_Handler
- def_default_handler SVC_Handler
- def_default_handler DebugMon_Handler
- def_default_handler PendSV_Handler
- def_default_handler SysTick_Handler
- def_default_handler Default_Handler
-
- .macro def_irq_default_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
-
-/* IRQ Handlers */
- def_irq_default_handler DMA0_IRQHandler
- def_irq_default_handler DMA1_IRQHandler
- def_irq_default_handler DMA2_IRQHandler
- def_irq_default_handler DMA3_IRQHandler
- def_irq_default_handler DMA4_IRQHandler
- def_irq_default_handler DMA5_IRQHandler
- def_irq_default_handler DMA6_IRQHandler
- def_irq_default_handler DMA7_IRQHandler
- def_irq_default_handler DMA8_IRQHandler
- def_irq_default_handler DMA9_IRQHandler
- def_irq_default_handler DMA10_IRQHandler
- def_irq_default_handler DMA11_IRQHandler
- def_irq_default_handler DMA12_IRQHandler
- def_irq_default_handler DMA13_IRQHandler
- def_irq_default_handler DMA14_IRQHandler
- def_irq_default_handler DMA15_IRQHandler
- def_irq_default_handler DMA_Error_IRQHandler
- def_irq_default_handler MCM_IRQHandler
- def_irq_default_handler FTF_IRQHandler
- def_irq_default_handler Read_Collision_IRQHandler
- def_irq_default_handler LVD_LVW_IRQHandler
- def_irq_default_handler LLW_IRQHandler
- def_irq_default_handler Watchdog_IRQHandler
- def_irq_default_handler RNG_IRQHandler
- def_irq_default_handler I2C0_IRQHandler
- def_irq_default_handler I2C1_IRQHandler
- def_irq_default_handler SPI0_IRQHandler
- def_irq_default_handler SPI1_IRQHandler
- def_irq_default_handler I2S0_Tx_IRQHandler
- def_irq_default_handler I2S0_Rx_IRQHandler
- def_irq_default_handler LPUART0_IRQHandler
- def_irq_default_handler UART0_RX_TX_IRQHandler
- def_irq_default_handler UART0_ERR_IRQHandler
- def_irq_default_handler UART1_RX_TX_IRQHandler
- def_irq_default_handler UART1_ERR_IRQHandler
- def_irq_default_handler UART2_RX_TX_IRQHandler
- def_irq_default_handler UART2_ERR_IRQHandler
- def_irq_default_handler Reserved53_IRQHandler
- def_irq_default_handler Reserved54_IRQHandler
- def_irq_default_handler ADC0_IRQHandler
- def_irq_default_handler CMP0_IRQHandler
- def_irq_default_handler CMP1_IRQHandler
- def_irq_default_handler FTM0_IRQHandler
- def_irq_default_handler FTM1_IRQHandler
- def_irq_default_handler FTM2_IRQHandler
- def_irq_default_handler Reserved61_IRQHandler
- def_irq_default_handler RTC_IRQHandler
- def_irq_default_handler RTC_Seconds_IRQHandler
- def_irq_default_handler PIT0_IRQHandler
- def_irq_default_handler PIT1_IRQHandler
- def_irq_default_handler PIT2_IRQHandler
- def_irq_default_handler PIT3_IRQHandler
- def_irq_default_handler PDB0_IRQHandler
- def_irq_default_handler USB0_IRQHandler
- def_irq_default_handler Reserved70_IRQHandler
- def_irq_default_handler Reserved71_IRQHandler
- def_irq_default_handler DAC0_IRQHandler
- def_irq_default_handler MCG_IRQHandler
- def_irq_default_handler LPTimer_IRQHandler
- def_irq_default_handler PORTA_IRQHandler
- def_irq_default_handler PORTB_IRQHandler
- def_irq_default_handler PORTC_IRQHandler
- def_irq_default_handler PORTD_IRQHandler
- def_irq_default_handler PORTE_IRQHandler
- def_irq_default_handler SWI_IRQHandler
- def_irq_default_handler Reserved81_IRQHandler
- def_irq_default_handler Reserved82_IRQHandler
- def_irq_default_handler Reserved83_IRQHandler
- def_irq_default_handler Reserved84_IRQHandler
- def_irq_default_handler Reserved85_IRQHandler
- def_irq_default_handler Reserved86_IRQHandler
- def_irq_default_handler FTM3_IRQHandler
- def_irq_default_handler DAC1_IRQHandler
- def_irq_default_handler ADC1_IRQHandler
- def_irq_default_handler Reserved90_IRQHandler
- def_irq_default_handler Reserved91_IRQHandler
- def_irq_default_handler Reserved92_IRQHandler
- def_irq_default_handler Reserved93_IRQHandler
- def_irq_default_handler Reserved94_IRQHandler
- def_irq_default_handler Reserved95_IRQHandler
- def_irq_default_handler Reserved96_IRQHandler
- def_irq_default_handler Reserved97_IRQHandler
- def_irq_default_handler Reserved98_IRQHandler
- def_irq_default_handler Reserved99_IRQHandler
- def_irq_default_handler Reserved100_IRQHandler
- def_irq_default_handler Reserved101_IRQHandler
- def_irq_default_handler DefaultISR
-
-/* Flash protection region, placed at 0x400 */
- .text
- .thumb
- .align 2
- .section .kinetis_flash_config_field,"a",%progbits
-kinetis_flash_config:
- .long 0xffffffff
- .long 0xffffffff
- .long 0xffffffff
- .long 0xfffffffe
-
- .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf
deleted file mode 100644
index 4955517c8..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf
+++ /dev/null
@@ -1,43 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0007ffff;
-define symbol __ICFEDIT_region_NVIC_start__ = 0x1fff0000;
-define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff03ff;
-define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0400;
-define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
-/*-Sizes-*/
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __ICFEDIT_size_cstack__ = 0x4000;
-define symbol __ICFEDIT_size_heap__ = 0x8000;
-/**** End of ICF editor section. ###ICF###*/
-
-define symbol __region_RAM2_start__ = 0x20000000;
-define symbol __region_RAM2_end__ = 0x2000ffff;
-
-define symbol __FlashConfig_start__ = 0x00000400;
-define symbol __FlashConfig_end__ = 0x0000040f;
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in FlashConfig_region {section FlashConfig};
-
-place in ROM_region { readonly };
-
-place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s
deleted file mode 100644
index 90ee34879..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s
+++ /dev/null
@@ -1,535 +0,0 @@
-/**************************************************
- *
- * Copyright 2012 IAR Systems. All rights reserved.
- *
- * $Revision: 16 $
- *
- **************************************************/
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:ROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK) ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- ; External Interrupts
- DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
- DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
- DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
- DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
- DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
- DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
- DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
- DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
- DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
- DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
- DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
- DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
- DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
- DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
- DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
- DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
- DCD DMA_Error_IRQHandler ; DMA Error Interrupt
- DCD MCM_IRQHandler ; Normal Interrupt
- DCD FTFE_IRQHandler ; FTFE Command complete interrupt
- DCD Read_Collision_IRQHandler ; Read Collision Interrupt
- DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
- DCD LLW_IRQHandler ; Low Leakage Wakeup
- DCD Watchdog_IRQHandler ; WDOG Interrupt
- DCD 0 ; Reserved
- DCD I2C0_IRQHandler ; I2C0 interrupt
- DCD I2C1_IRQHandler ; I2C1 interrupt
- DCD SPI0_IRQHandler ; SPI0 Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupt
- DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
- DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
- DCD UART0_LON_IRQHandler ; UART0 LON interrupt
- DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
- DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
- DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
- DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
- DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
- DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
- DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
- DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
- DCD ADC0_IRQHandler ; ADC0 interrupt
- DCD CMP0_IRQHandler ; CMP0 interrupt
- DCD CMP1_IRQHandler ; CMP1 interrupt
- DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
- DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
- DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
- DCD CMT_IRQHandler ; CMT interrupt
- DCD RTC_IRQHandler ; RTC interrupt
- DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
- DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
- DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
- DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
- DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
- DCD PDB0_IRQHandler ; PDB0 Interrupt
- DCD USB0_IRQHandler ; USB0 interrupt
- DCD USBDCD_IRQHandler ; USBDCD Interrupt
- DCD 0 ; Reserved
- DCD DAC0_IRQHandler ; DAC0 interrupt
- DCD MCG_IRQHandler ; MCG Interrupt
- DCD LPTimer_IRQHandler ; LPTimer interrupt
- DCD PORTA_IRQHandler ; Port A interrupt
- DCD PORTB_IRQHandler ; Port B interrupt
- DCD PORTC_IRQHandler ; Port C interrupt
- DCD PORTD_IRQHandler ; Port D interrupt
- DCD PORTE_IRQHandler ; Port E interrupt
- DCD SWI_IRQHandler ; Software interrupt
- DCD SPI2_IRQHandler ; SPI2 Interrupt
- DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
- DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
- DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
- DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
- DCD CMP2_IRQHandler ; CMP2 interrupt
- DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
- DCD DAC1_IRQHandler ; DAC1 interrupt
- DCD ADC1_IRQHandler ; ADC1 interrupt
- DCD I2C2_IRQHandler ; I2C2 interrupt
- DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
- DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
- DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
- DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
- DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
- DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
- DCD SDHC_IRQHandler ; SDHC interrupt
- DCD Default_Handler ; 98
- DCD Default_Handler ; 99
- DCD Default_Handler ; 100
- DCD Default_Handler ; 101
- DCD Default_Handler ; 102
- DCD Default_Handler ; 103
- DCD Default_Handler ; 104
- DCD Default_Handler ; 105
- DCD Default_Handler ; 106
- DCD Default_Handler ; 107
- DCD Default_Handler ; 108
- DCD Default_Handler ; 109
- DCD Default_Handler ; 110
- DCD Default_Handler ; 111
- DCD Default_Handler ; 112
- DCD Default_Handler ; 113
- DCD Default_Handler ; 114
- DCD Default_Handler ; 115
- DCD Default_Handler ; 116
- DCD Default_Handler ; 117
- DCD Default_Handler ; 118
- DCD Default_Handler ; 119
- DCD Default_Handler ; 120
- DCD Default_Handler ; 121
- DCD Default_Handler ; 122
- DCD Default_Handler ; 123
- DCD Default_Handler ; 124
- DCD Default_Handler ; 125
- DCD Default_Handler ; 126
- DCD Default_Handler ; 127
- DCD Default_Handler ; 128
- DCD Default_Handler ; 129
- DCD Default_Handler ; 130
- DCD Default_Handler ; 131
- DCD Default_Handler ; 132
- DCD Default_Handler ; 133
- DCD Default_Handler ; 134
- DCD Default_Handler ; 135
- DCD Default_Handler ; 136
- DCD Default_Handler ; 137
- DCD Default_Handler ; 138
- DCD Default_Handler ; 139
- DCD Default_Handler ; 140
- DCD Default_Handler ; 141
- DCD Default_Handler ; 142
- DCD Default_Handler ; 143
- DCD Default_Handler ; 144
- DCD Default_Handler ; 145
- DCD Default_Handler ; 146
- DCD Default_Handler ; 147
- DCD Default_Handler ; 148
- DCD Default_Handler ; 149
- DCD Default_Handler ; 150
- DCD Default_Handler ; 151
- DCD Default_Handler ; 152
- DCD Default_Handler ; 153
- DCD Default_Handler ; 154
- DCD Default_Handler ; 155
- DCD Default_Handler ; 156
- DCD Default_Handler ; 157
- DCD Default_Handler ; 158
- DCD Default_Handler ; 159
- DCD Default_Handler ; 160
- DCD Default_Handler ; 161
- DCD Default_Handler ; 162
- DCD Default_Handler ; 163
- DCD Default_Handler ; 164
- DCD Default_Handler ; 165
- DCD Default_Handler ; 166
- DCD Default_Handler ; 167
- DCD Default_Handler ; 168
- DCD Default_Handler ; 169
- DCD Default_Handler ; 170
- DCD Default_Handler ; 171
- DCD Default_Handler ; 172
- DCD Default_Handler ; 173
- DCD Default_Handler ; 174
- DCD Default_Handler ; 175
- DCD Default_Handler ; 176
- DCD Default_Handler ; 177
- DCD Default_Handler ; 178
- DCD Default_Handler ; 179
- DCD Default_Handler ; 180
- DCD Default_Handler ; 181
- DCD Default_Handler ; 182
- DCD Default_Handler ; 183
- DCD Default_Handler ; 184
- DCD Default_Handler ; 185
- DCD Default_Handler ; 186
- DCD Default_Handler ; 187
- DCD Default_Handler ; 188
- DCD Default_Handler ; 189
- DCD Default_Handler ; 190
- DCD Default_Handler ; 191
- DCD Default_Handler ; 192
- DCD Default_Handler ; 193
- DCD Default_Handler ; 194
- DCD Default_Handler ; 195
- DCD Default_Handler ; 196
- DCD Default_Handler ; 197
- DCD Default_Handler ; 198
- DCD Default_Handler ; 199
- DCD Default_Handler ; 200
- DCD Default_Handler ; 201
- DCD Default_Handler ; 202
- DCD Default_Handler ; 203
- DCD Default_Handler ; 204
- DCD Default_Handler ; 205
- DCD Default_Handler ; 206
- DCD Default_Handler ; 207
- DCD Default_Handler ; 208
- DCD Default_Handler ; 209
- DCD Default_Handler ; 210
- DCD Default_Handler ; 211
- DCD Default_Handler ; 212
- DCD Default_Handler ; 213
- DCD Default_Handler ; 214
- DCD Default_Handler ; 215
- DCD Default_Handler ; 216
- DCD Default_Handler ; 217
- DCD Default_Handler ; 218
- DCD Default_Handler ; 219
- DCD Default_Handler ; 220
- DCD Default_Handler ; 221
- DCD Default_Handler ; 222
- DCD Default_Handler ; 223
- DCD Default_Handler ; 224
- DCD Default_Handler ; 225
- DCD Default_Handler ; 226
- DCD Default_Handler ; 227
- DCD Default_Handler ; 228
- DCD Default_Handler ; 229
- DCD Default_Handler ; 230
- DCD Default_Handler ; 231
- DCD Default_Handler ; 232
- DCD Default_Handler ; 233
- DCD Default_Handler ; 234
- DCD Default_Handler ; 235
- DCD Default_Handler ; 236
- DCD Default_Handler ; 237
- DCD Default_Handler ; 238
- DCD Default_Handler ; 239
- DCD Default_Handler ; 240
- DCD Default_Handler ; 241
- DCD Default_Handler ; 242
- DCD Default_Handler ; 243
- DCD Default_Handler ; 244
- DCD Default_Handler ; 245
- DCD Default_Handler ; 246
- DCD Default_Handler ; 247
- DCD Default_Handler ; 248
- DCD Default_Handler ; 249
- DCD Default_Handler ; 250
- DCD Default_Handler ; 251
- DCD Default_Handler ; 252
- DCD Default_Handler ; 253
- DCD Default_Handler ; 254
- DCD Default_Handler ; 255
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;Flash Configuration
-;;16-byte flash configuration field that stores default protection settings (loaded on reset)
-;;and security information that allows the MCU to restrict acces to the FTFL module.
-
-BackDoorK0 EQU 0xFF
-BackDoorK1 EQU 0xFF
-BackDoorK2 EQU 0xFF
-BackDoorK3 EQU 0xFF
-BackDoorK4 EQU 0xFF
-BackDoorK5 EQU 0xFF
-BackDoorK6 EQU 0xFF
-BackDoorK7 EQU 0xFF
-
-nFPROT0 EQU 0x00
-FPROT0 EQU nFPROT0^0xFF
-
-nFPROT1 EQU 0x00
-FPROT1 EQU nFPROT1^0xFF
-
-nFPROT2 EQU 0x00
-FPROT2 EQU nFPROT2^0xFF
-
-nFPROT3 EQU 0x00
-FPROT3 EQU nFPROT3^0xFF
-
-nFEPROT EQU 0x00
-FEPROT EQU nFEPROT^0xFF
-
-nFDPROT EQU 0x00
-FDPROT EQU nFDPROT^0xFF
-
-FOPT EQU 0xFF
-
-FSEC EQU 0xFE
- SECTION FlashConfig:CONST:REORDER:ROOT(2)
-Config:
- DATA
- DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
- DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
- DCB FPROT0, FPROT1, FPROT2, FPROT3
- DCB FSEC, FOPT, FEPROT, FDPROT
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- PUBWEAK HardFault_Handler
- PUBWEAK MemManage_Handler
- PUBWEAK BusFault_Handler
- PUBWEAK UsageFault_Handler
- PUBWEAK SVC_Handler
- PUBWEAK DebugMon_Handler
- PUBWEAK PendSV_Handler
- PUBWEAK SysTick_Handler
- PUBWEAK DMA0_IRQHandler
- PUBWEAK DMA1_IRQHandler
- PUBWEAK DMA2_IRQHandler
- PUBWEAK DMA3_IRQHandler
- PUBWEAK DMA4_IRQHandler
- PUBWEAK DMA5_IRQHandler
- PUBWEAK DMA6_IRQHandler
- PUBWEAK DMA7_IRQHandler
- PUBWEAK DMA8_IRQHandler
- PUBWEAK DMA9_IRQHandler
- PUBWEAK DMA10_IRQHandler
- PUBWEAK DMA11_IRQHandler
- PUBWEAK DMA12_IRQHandler
- PUBWEAK DMA13_IRQHandler
- PUBWEAK DMA14_IRQHandler
- PUBWEAK DMA15_IRQHandler
- PUBWEAK DMA_Error_IRQHandler
- PUBWEAK MCM_IRQHandler
- PUBWEAK FTFE_IRQHandler
- PUBWEAK Read_Collision_IRQHandler
- PUBWEAK LVD_LVW_IRQHandler
- PUBWEAK LLW_IRQHandler
- PUBWEAK Watchdog_IRQHandler
- PUBWEAK I2C0_IRQHandler
- PUBWEAK I2C1_IRQHandler
- PUBWEAK SPI0_IRQHandler
- PUBWEAK SPI1_IRQHandler
- PUBWEAK I2S0_Tx_IRQHandler
- PUBWEAK I2S0_Rx_IRQHandler
- PUBWEAK UART0_LON_IRQHandler
- PUBWEAK UART0_RX_TX_IRQHandler
- PUBWEAK UART0_ERR_IRQHandler
- PUBWEAK UART1_RX_TX_IRQHandler
- PUBWEAK UART1_ERR_IRQHandler
- PUBWEAK UART2_RX_TX_IRQHandler
- PUBWEAK UART2_ERR_IRQHandler
- PUBWEAK UART3_RX_TX_IRQHandler
- PUBWEAK UART3_ERR_IRQHandler
- PUBWEAK ADC0_IRQHandler
- PUBWEAK CMP0_IRQHandler
- PUBWEAK CMP1_IRQHandler
- PUBWEAK FTM0_IRQHandler
- PUBWEAK FTM1_IRQHandler
- PUBWEAK FTM2_IRQHandler
- PUBWEAK CMT_IRQHandler
- PUBWEAK RTC_IRQHandler
- PUBWEAK RTC_Seconds_IRQHandler
- PUBWEAK PIT0_IRQHandler
- PUBWEAK PIT1_IRQHandler
- PUBWEAK PIT2_IRQHandler
- PUBWEAK PIT3_IRQHandler
- PUBWEAK PDB0_IRQHandler
- PUBWEAK USB0_IRQHandler
- PUBWEAK USBDCD_IRQHandler
- PUBWEAK DAC0_IRQHandler
- PUBWEAK MCG_IRQHandler
- PUBWEAK LPTimer_IRQHandler
- PUBWEAK PORTA_IRQHandler
- PUBWEAK PORTB_IRQHandler
- PUBWEAK PORTC_IRQHandler
- PUBWEAK PORTD_IRQHandler
- PUBWEAK PORTE_IRQHandler
- PUBWEAK SWI_IRQHandler
- PUBWEAK SPI2_IRQHandler
- PUBWEAK UART4_RX_TX_IRQHandler
- PUBWEAK UART4_ERR_IRQHandler
- PUBWEAK UART5_RX_TX_IRQHandler
- PUBWEAK UART5_ERR_IRQHandler
- PUBWEAK CMP2_IRQHandler
- PUBWEAK FTM3_IRQHandler
- PUBWEAK DAC1_IRQHandler
- PUBWEAK ADC1_IRQHandler
- PUBWEAK I2C2_IRQHandler
- PUBWEAK CAN0_ORed_Message_buffer_IRQHandler
- PUBWEAK CAN0_Bus_Off_IRQHandler
- PUBWEAK CAN0_Error_IRQHandler
- PUBWEAK CAN0_Tx_Warning_IRQHandler
- PUBWEAK CAN0_Rx_Warning_IRQHandler
- PUBWEAK CAN0_Wake_Up_IRQHandler
- PUBWEAK SDHC_IRQHandler
-
- SECTION .text:CODE:REORDER:NOROOT(1)
- THUMB
-NMI_Handler
-HardFault_Handler
-MemManage_Handler
-BusFault_Handler
-UsageFault_Handler
-SVC_Handler
-DebugMon_Handler
-PendSV_Handler
-SysTick_Handler
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-DMA4_IRQHandler
-DMA5_IRQHandler
-DMA6_IRQHandler
-DMA7_IRQHandler
-DMA8_IRQHandler
-DMA9_IRQHandler
-DMA10_IRQHandler
-DMA11_IRQHandler
-DMA12_IRQHandler
-DMA13_IRQHandler
-DMA14_IRQHandler
-DMA15_IRQHandler
-DMA_Error_IRQHandler
-MCM_IRQHandler
-FTFE_IRQHandler
-Read_Collision_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-Watchdog_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-I2S0_Tx_IRQHandler
-I2S0_Rx_IRQHandler
-UART0_LON_IRQHandler
-UART0_RX_TX_IRQHandler
-UART0_ERR_IRQHandler
-UART1_RX_TX_IRQHandler
-UART1_ERR_IRQHandler
-UART2_RX_TX_IRQHandler
-UART2_ERR_IRQHandler
-UART3_RX_TX_IRQHandler
-UART3_ERR_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-CMP1_IRQHandler
-FTM0_IRQHandler
-FTM1_IRQHandler
-FTM2_IRQHandler
-CMT_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT0_IRQHandler
-PIT1_IRQHandler
-PIT2_IRQHandler
-PIT3_IRQHandler
-PDB0_IRQHandler
-USB0_IRQHandler
-USBDCD_IRQHandler
-DAC0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-PORTA_IRQHandler
-PORTB_IRQHandler
-PORTC_IRQHandler
-PORTD_IRQHandler
-PORTE_IRQHandler
-SWI_IRQHandler
-SPI2_IRQHandler
-UART4_RX_TX_IRQHandler
-UART4_ERR_IRQHandler
-UART5_RX_TX_IRQHandler
-UART5_ERR_IRQHandler
-CMP2_IRQHandler
-FTM3_IRQHandler
-DAC1_IRQHandler
-ADC1_IRQHandler
-I2C2_IRQHandler
-CAN0_ORed_Message_buffer_IRQHandler
-CAN0_Bus_Off_IRQHandler
-CAN0_Error_IRQHandler
-CAN0_Tx_Warning_IRQHandler
-CAN0_Rx_Warning_IRQHandler
-CAN0_Wake_Up_IRQHandler
-SDHC_IRQHandler
-Default_Handler
-
- B Default_Handler
- END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h
deleted file mode 100644
index ff19283b7..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * A generic CMSIS include header, pulling in LPC11U24 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "MK22F51212.h"
-#include "cmsis_nvic.h"
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c
deleted file mode 100644
index fc13c884f..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- uint32_t i;
-
- // Copy and switch to dynamic vectors if the first time called
- if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
- uint32_t *old_vectors = vectors;
- vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- for (i=0; i<NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
- }
- SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
- }
- vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- return vectors[IRQn + 16];
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h
deleted file mode 100644
index 206b64543..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c
deleted file mode 100644
index bc387c16c..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
-** ###################################################################
-** Compilers: Keil ARM C/C++ Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
-** Version: rev. 2.5, 2014-05-06
-** Build: b140611
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright (c) 2014 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2013-07-23)
-** Initial version.
-** - rev. 1.1 (2013-09-17)
-** RM rev. 0.4 update.
-** - rev. 2.0 (2013-10-29)
-** Register accessor macros added to the memory map.
-** Symbols for Processor Expert memory map compatibility added to the memory map.
-** Startup file for gcc has been updated according to CMSIS 3.2.
-** System initialization updated.
-** - rev. 2.1 (2013-10-30)
-** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
-** - rev. 2.2 (2013-12-20)
-** Update according to reference manual rev. 0.6,
-** - rev. 2.3 (2014-01-13)
-** Update according to reference manual rev. 0.61,
-** - rev. 2.4 (2014-02-10)
-** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
-** - rev. 2.5 (2014-05-06)
-** Update according to reference manual rev. 1.0,
-** Update of system and startup files.
-** Module access macro module_BASES replaced by module_BASE_PTRS.
-**
-** ###################################################################
-*/
-
-/*!
- * @file MK22F51212
- * @version 2.5
- * @date 2014-05-06
- * @brief Device specific configuration file for MK22F51212 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "cmsis.h"
-
-
-
-/* ----------------------------------------------------------------------------
- -- Core clock
- ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
- -- SystemInit()
- ---------------------------------------------------------------------------- */
-
-void SystemInit (void) {
-#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
- SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
-
-#if (DISABLE_WDOG)
- /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
- WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
- /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
- WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
- /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
- WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
- WDOG_STCTRLH_WAITEN_MASK |
- WDOG_STCTRLH_STOPEN_MASK |
- WDOG_STCTRLH_ALLOWUPDATE_MASK |
- WDOG_STCTRLH_CLKSRC_MASK |
- 0x0100U;
-#endif /* (DISABLE_WDOG) */
- if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
- {
- if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
- {
- PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
- }
- } else {
-#ifdef SYSTEM_RTC_CR_VALUE
- SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
- if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
- RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
- RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
- RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
- }
-#endif
- }
-
- /* Power mode protection initialization */
-#ifdef SYSTEM_SMC_PMPROT_VALUE
- SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
-#endif
-
- /* High speed run mode enable */
-#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
- SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
- while(SMC->PMSTAT != 0x80U) { /* Wait until the system is in HSRUN mode */
- }
-#endif
- /* System clock initialization */
- /* Internal reference clock trim initialization */
-#if defined(SLOW_TRIM_ADDRESS)
- if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
- MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
- #endif /* defined(SLOW_TRIM_ADDRESS) */
- #if defined(SLOW_FINE_TRIM_ADDRESS)
- MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
- #endif
- #if defined(FAST_TRIM_ADDRESS)
- MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
- #endif
- #if defined(FAST_FINE_TRIM_ADDRESS)
- MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
- #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
-#if defined(SLOW_TRIM_ADDRESS)
- }
- #endif /* defined(SLOW_TRIM_ADDRESS) */
-
- /* Set system prescalers and clock sources */
- SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
- SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
- SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
-#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
- /* Set MCG and OSC */
-#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
- /* SIM_SCGC5: PORTA=1 */
- SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
- /* PORTA_PCR18: ISF=0,MUX=0 */
- PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
- if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
- /* PORTA_PCR19: ISF=0,MUX=0 */
- PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
- }
-#endif
- MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
- MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
- /* Check that the source of the FLL reference clock is the requested one. */
- if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
- while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
- }
- } else {
- while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
- }
- }
- MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
- MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
- OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
- MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
- #if (MCG_MODE == MCG_MODE_BLPI)
- /* BLPI specific */
- MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
- #endif
-
-#else /* MCG_MODE */
- /* Set MCG and OSC */
-#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
- /* SIM_SCGC5: PORTA=1 */
- SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
- /* PORTA_PCR18: ISF=0,MUX=0 */
- PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
- if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
- /* PORTA_PCR19: ISF=0,MUX=0 */
- PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
- }
-#endif
- MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
- MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
- OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
- MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
- #if (MCG_MODE == MCG_MODE_PEE)
- MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
- #else
- MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
- #endif
- if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
- while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
- }
- }
- /* Check that the source of the FLL reference clock is the requested one. */
- if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
- while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
- }
- } else {
- while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
- }
- }
- MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
-#endif /* MCG_MODE */
-
- /* Common for all MCG modes */
-
- /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
- MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
- MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
- if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
- MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
- }
- /* BLPE, PEE and PBE MCG mode specific */
-
-#if (MCG_MODE == MCG_MODE_BLPE)
- MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
-#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
- MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
- while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
- }
- #if (MCG_MODE == MCG_MODE_PEE)
- MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
- #endif
-#endif
-#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
- while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
- }
-#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
- while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
- }
-#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
- while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
- }
-#elif (MCG_MODE == MCG_MODE_PEE)
- while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
- }
-#endif
-#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
- SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
- while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
- }
-#endif
-
-#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
- SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
-#endif
-
- /* PLL loss of lock interrupt request initialization */
- if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
- NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
- }
-}
-
-/* ----------------------------------------------------------------------------
- -- SystemCoreClockUpdate()
- ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
-
- uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
- uint16_t Divider;
-
- if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
- /* Output of FLL or PLL is selected */
- if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
- /* FLL is selected */
- if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
- /* External reference clock is selected */
- switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
- case 0x00U:
- MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
- break;
- case 0x01U:
- MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
- break;
- case 0x02U:
- default:
- MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
- break;
- }
- if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
- switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
- case 0x38U:
- Divider = 1536U;
- break;
- case 0x30U:
- Divider = 1280U;
- break;
- default:
- Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
- break;
- }
- } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
- Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
- }
- MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
- } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
- MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
- } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
- /* Select correct multiplier to calculate the MCG output clock */
- switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
- case 0x00U:
- MCGOUTClock *= 640U;
- break;
- case 0x20U:
- MCGOUTClock *= 1280U;
- break;
- case 0x40U:
- MCGOUTClock *= 1920U;
- break;
- case 0x60U:
- MCGOUTClock *= 2560U;
- break;
- case 0x80U:
- MCGOUTClock *= 732U;
- break;
- case 0xA0U:
- MCGOUTClock *= 1464U;
- break;
- case 0xC0U:
- MCGOUTClock *= 2197U;
- break;
- case 0xE0U:
- MCGOUTClock *= 2929U;
- break;
- default:
- break;
- }
- } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
- /* PLL is selected */
- Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
- MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
- Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
- MCGOUTClock *= Divider; /* Calculate the MCG output clock */
- } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
- } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
- /* Internal reference clock is selected */
- if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
- MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
- } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
- Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
- MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
- } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
- } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
- /* External reference clock is selected */
- switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
- case 0x00U:
- MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
- break;
- case 0x01U:
- MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
- break;
- case 0x02U:
- default:
- MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
- break;
- }
- } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
- /* Reserved value */
- return;
- } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
- SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
-}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h
deleted file mode 100644
index bdeed9c5a..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
-** ###################################################################
-** Compilers: Keil ARM C/C++ Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
-** Version: rev. 2.5, 2014-05-06
-** Build: b140611
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright (c) 2014 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2013-07-23)
-** Initial version.
-** - rev. 1.1 (2013-09-17)
-** RM rev. 0.4 update.
-** - rev. 2.0 (2013-10-29)
-** Register accessor macros added to the memory map.
-** Symbols for Processor Expert memory map compatibility added to the memory map.
-** Startup file for gcc has been updated according to CMSIS 3.2.
-** System initialization updated.
-** - rev. 2.1 (2013-10-30)
-** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
-** - rev. 2.2 (2013-12-20)
-** Update according to reference manual rev. 0.6,
-** - rev. 2.3 (2014-01-13)
-** Update according to reference manual rev. 0.61,
-** - rev. 2.4 (2014-02-10)
-** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
-** - rev. 2.5 (2014-05-06)
-** Update according to reference manual rev. 1.0,
-** Update of system and startup files.
-** Module access macro module_BASES replaced by module_BASE_PTRS.
-**
-** ###################################################################
-*/
-
-/*!
- * @file MK22F51212
- * @version 2.5
- * @date 2014-05-06
- * @brief Device specific configuration file for MK22F51212 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef SYSTEM_MK22F51212_H_
-#define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-
-#define DISABLE_WDOG 1
-
-#ifndef CLOCK_SETUP
- #define CLOCK_SETUP 4
-#endif
-
-/* MCG mode constants */
-
-#define MCG_MODE_FEI 0U
-#define MCG_MODE_FBI 1U
-#define MCG_MODE_BLPI 2U
-#define MCG_MODE_FEE 3U
-#define MCG_MODE_FBE 4U
-#define MCG_MODE_BLPE 5U
-#define MCG_MODE_PBE 6U
-#define MCG_MODE_PEE 7U
-
-/* Predefined clock setups
- 0 ... Default part configuration
- Multipurpose Clock Generator (MCG) in FEI mode.
- Reference clock source for MCG module: Slow internal reference clock
- Core clock = 20.97152MHz
- Bus clock = 20.97152MHz
- 1 ... Maximum achievable clock frequency configuration
- Multipurpose Clock Generator (MCG) in PEE mode.
- Reference clock source for MCG module: System oscillator 0 reference clock
- Core clock = 120MHz
- Bus clock = 60MHz
- 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
- Multipurpose Clock Generator (MCG) in BLPI mode.
- Reference clock source for MCG module: Fast internal reference clock
- Core clock = 4MHz
- Bus clock = 4MHz
- 3 ... Chip externally clocked, ready for Very Low Power Run mode.
- Multipurpose Clock Generator (MCG) in BLPE mode.
- Reference clock source for MCG module: System oscillator 0 reference clock
- Core clock = 4MHz
- Bus clock = 4MHz
- 4 ... USB clock setup
- Multipurpose Clock Generator (MCG) in PEE mode.
- Reference clock source for MCG module: System oscillator 0 reference clock
- Core clock = 120MHz
- Bus clock = 60MHz
- 5 ... Maximum achievable clock frequency configuration in RUN mode
- Multipurpose Clock Generator (MCG) in PEE mode.
- Reference clock source for MCG module: System oscillator 0 reference clock
- Core clock = 80MHz
- Bus clock = 40MHz
- */
-
-/* Define clock source values */
-
-#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
-#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
-#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
-#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
-#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
-
-/* RTC oscillator setting */
-/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
-#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
-
-/* Low power mode enable */
-/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
-#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
-
-/* Internal reference clock trim */
-/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
-/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
-/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
-/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
-
-#if (CLOCK_SETUP == 0)
- #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
- #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
- /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
- #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
- /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
- /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
- #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
- /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
- #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
- #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
- #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
- #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
-/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
-/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
- #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
- #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
- #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
-/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
- #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 1)
- #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
- #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
- /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
- /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
- /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
- #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
- /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
- #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
- #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
- #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
- #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
-/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
-/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
- #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
- #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
- #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
-/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
- #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 2)
- #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
- #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
- /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
- #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
- /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
- #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
- /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
- #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
- /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
- #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
- #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
- #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
- #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
-/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
-/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
- #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
- #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
- #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
-/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
- #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 3)
- #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
- #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
- /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
- /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
- #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
- /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
- #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
- /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
- #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
- #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
- #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
- #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
-/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
-/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
- #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
- #define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
- #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
-/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
- #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 4)
- #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
- #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
- /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
- /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
- /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
- #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
- /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
- #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
- #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
- #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
- #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
-/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
-/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
- #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
- #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
-/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
- #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
- #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
-/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
- #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 5)
- #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
- #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
- /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
- #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
- /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
- #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
- /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
- #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
- /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
- #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
- #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
- #define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
- #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
-/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
- #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
-/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
- #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
- #define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
- #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
-/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
- #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
-#endif
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #if !defined(SYSTEM_MK22F51212_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h
deleted file mode 100644
index cc046d06e..000000000
--- a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h
+++ /dev/null
@@ -1,3613 +0,0 @@
-/*
-** ###################################################################
-** Processors: MKL05Z32FK4
-** MKL05Z32LC4
-** MKL05Z32VLF4
-**
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
-** Version: rev. 1.3, 2012-10-04
-**
-** Abstract:
-** CMSIS Peripheral Access Layer for MKL05Z4
-**
-** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2012-06-08)
-** Initial version.
-** - rev. 1.1 (2012-06-21)
-** Update according to reference manual rev. 1.
-** - rev. 1.2 (2012-08-01)
-** Device type UARTLP changed to UART0.
-** Missing PORTB_IRQn interrupt number definition added.
-** - rev. 1.3 (2012-10-04)
-** Update according to reference manual rev. 3.
-**
-** ###################################################################
-*/
-
-/**
- * @file MKL05Z4.h
- * @version 1.3
- * @date 2012-10-04
- * @brief CMSIS Peripheral Access Layer for MKL05Z4
- *
- * CMSIS Peripheral Access Layer for MKL05Z4
- */
-
-#if !defined(MKL05Z4_H_)
-#define MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0003u
-
-
-/* ----------------------------------------------------------------------------
- -- Interrupt vector numbers
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-typedef enum IRQn {
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
-
- /* Device specific interrupts */
- DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
- DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
- DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
- DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
- Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
- FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
- LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
- LLW_IRQn = 7, /**< Low Leakage Wakeup */
- I2C0_IRQn = 8, /**< I2C0 interrupt */
- Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
- SPI0_IRQn = 10, /**< SPI0 interrupt */
- Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
- UART0_IRQn = 12, /**< UART0 status/error interrupt */
- Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
- Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
- ADC0_IRQn = 15, /**< ADC0 interrupt */
- CMP0_IRQn = 16, /**< CMP0 interrupt */
- TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
- TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
- Reserved35_IRQn = 19, /**< Reserved interrupt 35 */
- RTC_IRQn = 20, /**< RTC interrupt */
- RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
- PIT_IRQn = 22, /**< PIT timer interrupt */
- Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
- Reserved40_IRQn = 24, /**< Reserved interrupt 40 */
- DAC0_IRQn = 25, /**< DAC0 interrupt */
- TSI0_IRQn = 26, /**< TSI0 interrupt */
- MCG_IRQn = 27, /**< MCG interrupt */
- LPTimer_IRQn = 28, /**< LPTimer interrupt */
- Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
- PORTA_IRQn = 30, /**< Port A interrupt */
- PORTB_IRQn = 31 /**< Port B interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
- -- Cortex M0 Core Configuration
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
- * @{
- */
-
-#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
-#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
-#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-
-#include "core_cm0plus.h" /* Core Peripheral Access Layer */
-#include "system_MKL05Z4.h" /* Device specific configuration file */
-
-/**
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
- -- Device Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
- -- ADC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
- __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
- __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
- __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
- __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
- __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
- __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
- __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
- __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
- __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
- __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
- __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
- __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
- __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
- __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
- __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
-} ADC_Type;
-
-/* ----------------------------------------------------------------------------
- -- ADC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-
-/**
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x4003B000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASES { ADC0 }
-
-/**
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
- * @{
- */
-
-/** CMP - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
- __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
- __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
- __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
- __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
- __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type;
-
-/* ----------------------------------------------------------------------------
- -- CMP Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Register_Masks CMP Register Masks
- * @{
- */
-
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_TRIGM_MASK 0x20u
-#define CMP_CR1_TRIGM_SHIFT 5
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-#define CMP_MUXCR_PSTM_MASK 0x80u
-#define CMP_MUXCR_PSTM_SHIFT 7
-
-/**
- * @}
- */ /* end of group CMP_Register_Masks */
-
-
-/* CMP - Peripheral instance base addresses */
-/** Peripheral CMP0 base address */
-#define CMP0_BASE (0x40073000u)
-/** Peripheral CMP0 base pointer */
-#define CMP0 ((CMP_Type *)CMP0_BASE)
-/** Array initializer of CMP peripheral base pointers */
-#define CMP_BASES { CMP0 }
-
-/**
- * @}
- */ /* end of group CMP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DAC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
- * @{
- */
-
-/** DAC - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x2 */
- __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
- __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
- } DAT[2];
- uint8_t RESERVED_0[28];
- __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
- __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
- __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
- __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type;
-
-/* ----------------------------------------------------------------------------
- -- DAC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Register_Masks DAC Register Masks
- * @{
- */
-
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFMD_MASK 0x4u
-#define DAC_C1_DACBFMD_SHIFT 2
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0x1u
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFRP_MASK 0x10u
-#define DAC_C2_DACBFRP_SHIFT 4
-
-/**
- * @}
- */ /* end of group DAC_Register_Masks */
-
-
-/* DAC - Peripheral instance base addresses */
-/** Peripheral DAC0 base address */
-#define DAC0_BASE (0x4003F000u)
-/** Peripheral DAC0 base pointer */
-#define DAC0 ((DAC_Type *)DAC0_BASE)
-/** Array initializer of DAC peripheral base pointers */
-#define DAC_BASES { DAC0 }
-
-/**
- * @}
- */ /* end of group DAC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[256];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
- __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
- union { /* offset: 0x108, array step: 0x10 */
- __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
- struct { /* offset: 0x108, array step: 0x10 */
- uint8_t RESERVED_0[3];
- __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
- } DMA_DSR_ACCESS8BIT;
- };
- __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
- } DMA[4];
-} DMA_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* SAR Bit Fields */
-#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
-#define DMA_SAR_SAR_SHIFT 0
-#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
-/* DAR Bit Fields */
-#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
-#define DMA_DAR_DAR_SHIFT 0
-#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
-/* DSR_BCR Bit Fields */
-#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
-#define DMA_DSR_BCR_BCR_SHIFT 0
-#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
-#define DMA_DSR_BCR_DONE_MASK 0x1000000u
-#define DMA_DSR_BCR_DONE_SHIFT 24
-#define DMA_DSR_BCR_BSY_MASK 0x2000000u
-#define DMA_DSR_BCR_BSY_SHIFT 25
-#define DMA_DSR_BCR_REQ_MASK 0x4000000u
-#define DMA_DSR_BCR_REQ_SHIFT 26
-#define DMA_DSR_BCR_BED_MASK 0x10000000u
-#define DMA_DSR_BCR_BED_SHIFT 28
-#define DMA_DSR_BCR_BES_MASK 0x20000000u
-#define DMA_DSR_BCR_BES_SHIFT 29
-#define DMA_DSR_BCR_CE_MASK 0x40000000u
-#define DMA_DSR_BCR_CE_SHIFT 30
-/* DCR Bit Fields */
-#define DMA_DCR_LCH2_MASK 0x3u
-#define DMA_DCR_LCH2_SHIFT 0
-#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
-#define DMA_DCR_LCH1_MASK 0xCu
-#define DMA_DCR_LCH1_SHIFT 2
-#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
-#define DMA_DCR_LINKCC_MASK 0x30u
-#define DMA_DCR_LINKCC_SHIFT 4
-#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
-#define DMA_DCR_D_REQ_MASK 0x80u
-#define DMA_DCR_D_REQ_SHIFT 7
-#define DMA_DCR_DMOD_MASK 0xF00u
-#define DMA_DCR_DMOD_SHIFT 8
-#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
-#define DMA_DCR_SMOD_MASK 0xF000u
-#define DMA_DCR_SMOD_SHIFT 12
-#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
-#define DMA_DCR_START_MASK 0x10000u
-#define DMA_DCR_START_SHIFT 16
-#define DMA_DCR_DSIZE_MASK 0x60000u
-#define DMA_DCR_DSIZE_SHIFT 17
-#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
-#define DMA_DCR_DINC_MASK 0x80000u
-#define DMA_DCR_DINC_SHIFT 19
-#define DMA_DCR_SSIZE_MASK 0x300000u
-#define DMA_DCR_SSIZE_SHIFT 20
-#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
-#define DMA_DCR_SINC_MASK 0x400000u
-#define DMA_DCR_SINC_SHIFT 22
-#define DMA_DCR_EADREQ_MASK 0x800000u
-#define DMA_DCR_EADREQ_SHIFT 23
-#define DMA_DCR_AA_MASK 0x10000000u
-#define DMA_DCR_AA_SHIFT 28
-#define DMA_DCR_CS_MASK 0x20000000u
-#define DMA_DCR_CS_SHIFT 29
-#define DMA_DCR_ERQ_MASK 0x40000000u
-#define DMA_DCR_ERQ_SHIFT 30
-#define DMA_DCR_EINT_MASK 0x80000000u
-#define DMA_DCR_EINT_SHIFT 31
-
-/**
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA base address */
-#define DMA_BASE (0x40008000u)
-/** Peripheral DMA base pointer */
-#define DMA0 ((DMA_Type *)DMA_BASE)
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASES { DMA0 }
-
-/**
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
- * @{
- */
-
-/** DMAMUX - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
- * @{
- */
-
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-
-/**
- * @}
- */ /* end of group DMAMUX_Register_Masks */
-
-
-/* DMAMUX - Peripheral instance base addresses */
-/** Peripheral DMAMUX0 base address */
-#define DMAMUX0_BASE (0x40021000u)
-/** Peripheral DMAMUX0 base pointer */
-#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
-/** Array initializer of DMAMUX peripheral base pointers */
-#define DMAMUX_BASES { DMAMUX0 }
-
-/**
- * @}
- */ /* end of group DMAMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FGPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
- * @{
- */
-
-/** FGPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} FGPIO_Type;
-
-/* ----------------------------------------------------------------------------
- -- FGPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define FGPIO_PDOR_PDO_SHIFT 0
-#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define FGPIO_PSOR_PTSO_SHIFT 0
-#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define FGPIO_PCOR_PTCO_SHIFT 0
-#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define FGPIO_PTOR_PTTO_SHIFT 0
-#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define FGPIO_PDIR_PDI_SHIFT 0
-#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define FGPIO_PDDR_PDD_SHIFT 0
-#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group FGPIO_Register_Masks */
-
-
-/* FGPIO - Peripheral instance base addresses */
-/** Peripheral FPTA base address */
-#define FPTA_BASE (0xF80FF000u)
-/** Peripheral FPTA base pointer */
-#define FPTA ((FGPIO_Type *)FPTA_BASE)
-/** Peripheral FPTB base address */
-#define FPTB_BASE (0xF80FF040u)
-/** Peripheral FPTB base pointer */
-#define FPTB ((FGPIO_Type *)FPTB_BASE)
-/** Array initializer of FGPIO peripheral base pointers */
-#define FGPIO_BASES { FPTA, FPTB }
-
-/**
- * @}
- */ /* end of group FGPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
- * @{
- */
-
-/** FTFA - Register Layout Typedef */
-typedef struct {
- __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
- __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
- __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
- __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
- __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
- __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
- __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
- __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
- __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
- __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
- __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
- __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
- __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
- __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
- __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
- __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
- __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
- __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
- __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
- __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
-} FTFA_Type;
-
-/* ----------------------------------------------------------------------------
- -- FTFA Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFA_Register_Masks FTFA Register Masks
- * @{
- */
-
-/* FSTAT Bit Fields */
-#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFA_FSTAT_MGSTAT0_SHIFT 0
-#define FTFA_FSTAT_FPVIOL_MASK 0x10u
-#define FTFA_FSTAT_FPVIOL_SHIFT 4
-#define FTFA_FSTAT_ACCERR_MASK 0x20u
-#define FTFA_FSTAT_ACCERR_SHIFT 5
-#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFA_FSTAT_RDCOLERR_SHIFT 6
-#define FTFA_FSTAT_CCIF_MASK 0x80u
-#define FTFA_FSTAT_CCIF_SHIFT 7
-/* FCNFG Bit Fields */
-#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFA_FCNFG_ERSSUSP_SHIFT 4
-#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFA_FCNFG_ERSAREQ_SHIFT 5
-#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFA_FCNFG_CCIE_MASK 0x80u
-#define FTFA_FCNFG_CCIE_SHIFT 7
-/* FSEC Bit Fields */
-#define FTFA_FSEC_SEC_MASK 0x3u
-#define FTFA_FSEC_SEC_SHIFT 0
-#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
-#define FTFA_FSEC_FSLACC_MASK 0xCu
-#define FTFA_FSEC_FSLACC_SHIFT 2
-#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
-#define FTFA_FSEC_MEEN_MASK 0x30u
-#define FTFA_FSEC_MEEN_SHIFT 4
-#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
-#define FTFA_FSEC_KEYEN_MASK 0xC0u
-#define FTFA_FSEC_KEYEN_SHIFT 6
-#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFA_FOPT_OPT_MASK 0xFFu
-#define FTFA_FOPT_OPT_SHIFT 0
-#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB3_CCOBn_SHIFT 0
-#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB2_CCOBn_SHIFT 0
-#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB1_CCOBn_SHIFT 0
-#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB0_CCOBn_SHIFT 0
-#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB7_CCOBn_SHIFT 0
-#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB6_CCOBn_SHIFT 0
-#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB5_CCOBn_SHIFT 0
-#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB4_CCOBn_SHIFT 0
-#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBB_CCOBn_SHIFT 0
-#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBA_CCOBn_SHIFT 0
-#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB9_CCOBn_SHIFT 0
-#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB8_CCOBn_SHIFT 0
-#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFA_FPROT3_PROT_MASK 0xFFu
-#define FTFA_FPROT3_PROT_SHIFT 0
-#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFA_FPROT2_PROT_MASK 0xFFu
-#define FTFA_FPROT2_PROT_SHIFT 0
-#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFA_FPROT1_PROT_MASK 0xFFu
-#define FTFA_FPROT1_PROT_SHIFT 0
-#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFA_FPROT0_PROT_MASK 0xFFu
-#define FTFA_FPROT0_PROT_SHIFT 0
-#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
-
-/**
- * @}
- */ /* end of group FTFA_Register_Masks */
-
-
-/* FTFA - Peripheral instance base addresses */
-/** Peripheral FTFA base address */
-#define FTFA_BASE (0x40020000u)
-/** Peripheral FTFA base pointer */
-#define FTFA ((FTFA_Type *)FTFA_BASE)
-/** Array initializer of FTFA peripheral base pointers */
-#define FTFA_BASES { FTFA }
-
-/**
- * @}
- */ /* end of group FTFA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type;
-
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASES { PTA, PTB }
-
-/**
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
- __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
- __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
- __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
- __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
- __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
- __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
- __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
- __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
- __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
- __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
- __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
- __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2C Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0x1Fu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STOPIE_MASK 0x20u
-#define I2C_FLT_STOPIE_SHIFT 5
-#define I2C_FLT_STOPF_MASK 0x40u
-#define I2C_FLT_STOPF_SHIFT 6
-#define I2C_FLT_SHEN_MASK 0x80u
-#define I2C_FLT_SHEN_SHIFT 7
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-
-/**
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40066000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASES { I2C0 }
-
-/**
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
- * @{
- */
-
-/** LLWU - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
- __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
- __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x2 */
- __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x3 */
- __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x4 */
- __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x5 */
- __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x6 */
-} LLWU_Type;
-
-/* ----------------------------------------------------------------------------
- -- LLWU Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Register_Masks LLWU Register Masks
- * @{
- */
-
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-
-/**
- * @}
- */ /* end of group LLWU_Register_Masks */
-
-
-/* LLWU - Peripheral instance base addresses */
-/** Peripheral LLWU base address */
-#define LLWU_BASE (0x4007C000u)
-/** Peripheral LLWU base pointer */
-#define LLWU ((LLWU_Type *)LLWU_BASE)
-/** Array initializer of LLWU peripheral base pointers */
-#define LLWU_BASES { LLWU }
-
-/**
- * @}
- */ /* end of group LLWU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
- * @{
- */
-
-/** LPTMR - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
- __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
- __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
- __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
- * @{
- */
-
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-
-/**
- * @}
- */ /* end of group LPTMR_Register_Masks */
-
-
-/* LPTMR - Peripheral instance base addresses */
-/** Peripheral LPTMR0 base address */
-#define LPTMR0_BASE (0x40040000u)
-/** Peripheral LPTMR0 base pointer */
-#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-/** Array initializer of LPTMR peripheral base pointers */
-#define LPTMR_BASES { LPTMR0 }
-
-/**
- * @}
- */ /* end of group LPTMR_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
- * @{
- */
-
-/** MCG - Register Layout Typedef */
-typedef struct {
- __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
- __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
- __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
- __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
- __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
- __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
- __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
- uint8_t RESERVED_0[1];
- __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
- uint8_t RESERVED_1[1];
- __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
- __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
-} MCG_Type;
-
-/* ----------------------------------------------------------------------------
- -- MCG Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Register_Masks MCG Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_EREFS0_MASK 0x4u
-#define MCG_C2_EREFS0_SHIFT 2
-#define MCG_C2_HGO0_MASK 0x8u
-#define MCG_C2_HGO0_SHIFT 3
-#define MCG_C2_RANGE0_MASK 0x30u
-#define MCG_C2_RANGE0_SHIFT 4
-#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-/* C6 Bit Fields */
-#define MCG_C6_CME_MASK 0x20u
-#define MCG_C6_CME_SHIFT 5
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-
-/**
- * @}
- */ /* end of group MCG_Register_Masks */
-
-
-/* MCG - Peripheral instance base addresses */
-/** Peripheral MCG base address */
-#define MCG_BASE (0x40064000u)
-/** Peripheral MCG base pointer */
-#define MCG ((MCG_Type *)MCG_BASE)
-/** Array initializer of MCG peripheral base pointers */
-#define MCG_BASES { MCG }
-
-/**
- * @}
- */ /* end of group MCG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
- * @{
- */
-
-/** MCM - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[8];
- __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
- __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
- __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
- uint8_t RESERVED_1[48];
- __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
-} MCM_Type;
-
-/* ----------------------------------------------------------------------------
- -- MCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCM_Register_Masks MCM Register Masks
- * @{
- */
-
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK 0xFFu
-#define MCM_PLASC_ASC_SHIFT 0
-#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK 0xFFu
-#define MCM_PLAMC_AMC_SHIFT 0
-#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* PLACR Bit Fields */
-#define MCM_PLACR_ARB_MASK 0x200u
-#define MCM_PLACR_ARB_SHIFT 9
-#define MCM_PLACR_CFCC_MASK 0x400u
-#define MCM_PLACR_CFCC_SHIFT 10
-#define MCM_PLACR_DFCDA_MASK 0x800u
-#define MCM_PLACR_DFCDA_SHIFT 11
-#define MCM_PLACR_DFCIC_MASK 0x1000u
-#define MCM_PLACR_DFCIC_SHIFT 12
-#define MCM_PLACR_DFCC_MASK 0x2000u
-#define MCM_PLACR_DFCC_SHIFT 13
-#define MCM_PLACR_EFDS_MASK 0x4000u
-#define MCM_PLACR_EFDS_SHIFT 14
-#define MCM_PLACR_DFCS_MASK 0x8000u
-#define MCM_PLACR_DFCS_SHIFT 15
-#define MCM_PLACR_ESFC_MASK 0x10000u
-#define MCM_PLACR_ESFC_SHIFT 16
-/* CPO Bit Fields */
-#define MCM_CPO_CPOREQ_MASK 0x1u
-#define MCM_CPO_CPOREQ_SHIFT 0
-#define MCM_CPO_CPOACK_MASK 0x2u
-#define MCM_CPO_CPOACK_SHIFT 1
-#define MCM_CPO_CPOWOI_MASK 0x4u
-#define MCM_CPO_CPOWOI_SHIFT 2
-
-/**
- * @}
- */ /* end of group MCM_Register_Masks */
-
-
-/* MCM - Peripheral instance base addresses */
-/** Peripheral MCM base address */
-#define MCM_BASE (0xF0003000u)
-/** Peripheral MCM base pointer */
-#define MCM ((MCM_Type *)MCM_BASE)
-/** Array initializer of MCM peripheral base pointers */
-#define MCM_BASES { MCM }
-
-/**
- * @}
- */ /* end of group MCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MTB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
- * @{
- */
-
-/** MTB - Register Layout Typedef */
-typedef struct {
- __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
- __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
- __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
- __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
- uint8_t RESERVED_0[3824];
- __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
- uint8_t RESERVED_1[156];
- __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
- __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
- uint8_t RESERVED_2[8];
- __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
- __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
- __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
- __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
- uint8_t RESERVED_3[8];
- __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
- __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
- __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
- __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} MTB_Type;
-
-/* ----------------------------------------------------------------------------
- -- MTB Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTB_Register_Masks MTB Register Masks
- * @{
- */
-
-/* POSITION Bit Fields */
-#define MTB_POSITION_WRAP_MASK 0x4u
-#define MTB_POSITION_WRAP_SHIFT 2
-#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
-#define MTB_POSITION_POINTER_SHIFT 3
-#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
-/* MASTER Bit Fields */
-#define MTB_MASTER_MASK_MASK 0x1Fu
-#define MTB_MASTER_MASK_SHIFT 0
-#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
-#define MTB_MASTER_TSTARTEN_MASK 0x20u
-#define MTB_MASTER_TSTARTEN_SHIFT 5
-#define MTB_MASTER_TSTOPEN_MASK 0x40u
-#define MTB_MASTER_TSTOPEN_SHIFT 6
-#define MTB_MASTER_SFRWPRIV_MASK 0x80u
-#define MTB_MASTER_SFRWPRIV_SHIFT 7
-#define MTB_MASTER_RAMPRIV_MASK 0x100u
-#define MTB_MASTER_RAMPRIV_SHIFT 8
-#define MTB_MASTER_HALTREQ_MASK 0x200u
-#define MTB_MASTER_HALTREQ_SHIFT 9
-#define MTB_MASTER_EN_MASK 0x80000000u
-#define MTB_MASTER_EN_SHIFT 31
-/* FLOW Bit Fields */
-#define MTB_FLOW_AUTOSTOP_MASK 0x1u
-#define MTB_FLOW_AUTOSTOP_SHIFT 0
-#define MTB_FLOW_AUTOHALT_MASK 0x2u
-#define MTB_FLOW_AUTOHALT_SHIFT 1
-#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
-#define MTB_FLOW_WATERMARK_SHIFT 3
-#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
-/* BASE Bit Fields */
-#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
-#define MTB_BASE_BASEADDR_SHIFT 0
-#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
-/* MODECTRL Bit Fields */
-#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
-#define MTB_MODECTRL_MODECTRL_SHIFT 0
-#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
-/* TAGSET Bit Fields */
-#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
-#define MTB_TAGSET_TAGSET_SHIFT 0
-#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
-/* TAGCLEAR Bit Fields */
-#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
-#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
-#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
-/* LOCKACCESS Bit Fields */
-#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
-#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
-#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
-/* LOCKSTAT Bit Fields */
-#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
-#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
-#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
-/* AUTHSTAT Bit Fields */
-#define MTB_AUTHSTAT_BIT0_MASK 0x1u
-#define MTB_AUTHSTAT_BIT0_SHIFT 0
-#define MTB_AUTHSTAT_BIT1_MASK 0x2u
-#define MTB_AUTHSTAT_BIT1_SHIFT 1
-#define MTB_AUTHSTAT_BIT2_MASK 0x4u
-#define MTB_AUTHSTAT_BIT2_SHIFT 2
-#define MTB_AUTHSTAT_BIT3_MASK 0x8u
-#define MTB_AUTHSTAT_BIT3_SHIFT 3
-/* DEVICEARCH Bit Fields */
-#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
-#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
-#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
-/* DEVICECFG Bit Fields */
-#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
-#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
-#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
-/* DEVICETYPID Bit Fields */
-#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
-#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
-#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
-/* PERIPHID Bit Fields */
-#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
-#define MTB_PERIPHID_PERIPHID_SHIFT 0
-#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
-#define MTB_COMPID_COMPID_SHIFT 0
-#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group MTB_Register_Masks */
-
-
-/* MTB - Peripheral instance base addresses */
-/** Peripheral MTB base address */
-#define MTB_BASE (0xF0000000u)
-/** Peripheral MTB base pointer */
-#define MTB ((MTB_Type *)MTB_BASE)
-/** Array initializer of MTB peripheral base pointers */
-#define MTB_BASES { MTB }
-
-/**
- * @}
- */ /* end of group MTB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MTBDWT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
- * @{
- */
-
-/** MTBDWT - Register Layout Typedef */
-typedef struct {
- __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
- uint8_t RESERVED_0[28];
- struct { /* offset: 0x20, array step: 0x10 */
- __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
- __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
- __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
- uint8_t RESERVED_0[4];
- } COMPARATOR[2];
- uint8_t RESERVED_1[448];
- __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
- uint8_t RESERVED_2[3524];
- __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
- __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
- __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
- __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} MTBDWT_Type;
-
-/* ----------------------------------------------------------------------------
- -- MTBDWT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
- * @{
- */
-
-/* CTRL Bit Fields */
-#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
-#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
-#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
-#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
-#define MTBDWT_CTRL_NUMCMP_SHIFT 28
-#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
-/* COMP Bit Fields */
-#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
-#define MTBDWT_COMP_COMP_SHIFT 0
-#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
-/* MASK Bit Fields */
-#define MTBDWT_MASK_MASK_MASK 0x1Fu
-#define MTBDWT_MASK_MASK_SHIFT 0
-#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
-/* FCT Bit Fields */
-#define MTBDWT_FCT_FUNCTION_MASK 0xFu
-#define MTBDWT_FCT_FUNCTION_SHIFT 0
-#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
-#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
-#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
-#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
-#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
-#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
-#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
-#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
-#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
-#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
-#define MTBDWT_FCT_MATCHED_SHIFT 24
-/* TBCTRL Bit Fields */
-#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
-#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
-#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
-#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
-#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
-#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
-#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
-/* DEVICECFG Bit Fields */
-#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
-#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
-#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
-/* DEVICETYPID Bit Fields */
-#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
-#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
-#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
-/* PERIPHID Bit Fields */
-#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
-#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
-#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
-#define MTBDWT_COMPID_COMPID_SHIFT 0
-#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group MTBDWT_Register_Masks */
-
-
-/* MTBDWT - Peripheral instance base addresses */
-/** Peripheral MTBDWT base address */
-#define MTBDWT_BASE (0xF0001000u)
-/** Peripheral MTBDWT base pointer */
-#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
-/** Array initializer of MTBDWT peripheral base pointers */
-#define MTBDWT_BASES { MTBDWT }
-
-/**
- * @}
- */ /* end of group MTBDWT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
- * @{
- */
-
-/** NV - Register Layout Typedef */
-typedef struct {
- __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
- __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
- __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
- __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
- __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
- __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
- __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
- __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
- __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
- __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
- __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
- __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
- __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
- __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
-} NV_Type;
-
-/* ----------------------------------------------------------------------------
- -- NV Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Register_Masks NV Register Masks
- * @{
- */
-
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT0_MASK 0x1u
-#define NV_FOPT_LPBOOT0_SHIFT 0
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-#define NV_FOPT_NMI_DIS_MASK 0x4u
-#define NV_FOPT_NMI_DIS_SHIFT 2
-#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
-#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
-#define NV_FOPT_LPBOOT1_MASK 0x10u
-#define NV_FOPT_LPBOOT1_SHIFT 4
-#define NV_FOPT_FAST_INIT_MASK 0x20u
-#define NV_FOPT_FAST_INIT_SHIFT 5
-
-/**
- * @}
- */ /* end of group NV_Register_Masks */
-
-
-/* NV - Peripheral instance base addresses */
-/** Peripheral FTFA_FlashConfig base address */
-#define FTFA_FlashConfig_BASE (0x400u)
-/** Peripheral FTFA_FlashConfig base pointer */
-#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
-/** Array initializer of NV peripheral base pointers */
-#define NV_BASES { FTFA_FlashConfig }
-
-/**
- * @}
- */ /* end of group NV_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
- * @{
- */
-
-/** OSC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
-} OSC_Type;
-
-/* ----------------------------------------------------------------------------
- -- OSC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Register_Masks OSC Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-
-/**
- * @}
- */ /* end of group OSC_Register_Masks */
-
-
-/* OSC - Peripheral instance base addresses */
-/** Peripheral OSC0 base address */
-#define OSC0_BASE (0x40065000u)
-/** Peripheral OSC0 base pointer */
-#define OSC0 ((OSC_Type *)OSC0_BASE)
-/** Array initializer of OSC peripheral base pointers */
-#define OSC_BASES { OSC0 }
-
-/**
- * @}
- */ /* end of group OSC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
- * @{
- */
-
-/** PIT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
- uint8_t RESERVED_0[220];
- __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
- __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
- uint8_t RESERVED_1[24];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
- __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
- __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
- __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
- } CHANNEL[2];
-} PIT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-/* LTMR64H Bit Fields */
-#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
-#define PIT_LTMR64H_LTH_SHIFT 0
-#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
-/* LTMR64L Bit Fields */
-#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
-#define PIT_LTMR64L_LTL_SHIFT 0
-#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-#define PIT_TCTRL_CHN_MASK 0x4u
-#define PIT_TCTRL_CHN_SHIFT 2
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-
-/**
- * @}
- */ /* end of group PIT_Register_Masks */
-
-
-/* PIT - Peripheral instance base addresses */
-/** Peripheral PIT base address */
-#define PIT_BASE (0x40037000u)
-/** Peripheral PIT base pointer */
-#define PIT ((PIT_Type *)PIT_BASE)
-/** Array initializer of PIT peripheral base pointers */
-#define PIT_BASES { PIT }
-
-/**
- * @}
- */ /* end of group PIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
- * @{
- */
-
-/** PMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
- __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
- __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- PMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Register_Masks PMC Register Masks
- * @{
- */
-
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-#define PMC_REGSC_BGEN_MASK 0x10u
-#define PMC_REGSC_BGEN_SHIFT 4
-
-/**
- * @}
- */ /* end of group PMC_Register_Masks */
-
-
-/* PMC - Peripheral instance base addresses */
-/** Peripheral PMC base address */
-#define PMC_BASE (0x4007D000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASES { PMC }
-
-/**
- * @}
- */ /* end of group PMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
- * @{
- */
-
-/** PORT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
- __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
- __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
- uint8_t RESERVED_0[24];
- __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
-} PORT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PORT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Register_Masks PORT Register Masks
- * @{
- */
-
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-
-/**
- * @}
- */ /* end of group PORT_Register_Masks */
-
-
-/* PORT - Peripheral instance base addresses */
-/** Peripheral PORTA base address */
-#define PORTA_BASE (0x40049000u)
-/** Peripheral PORTA base pointer */
-#define PORTA ((PORT_Type *)PORTA_BASE)
-/** Peripheral PORTB base address */
-#define PORTB_BASE (0x4004A000u)
-/** Peripheral PORTB base pointer */
-#define PORTB ((PORT_Type *)PORTB_BASE)
-/** Array initializer of PORT peripheral base pointers */
-#define PORT_BASES { PORTA, PORTB }
-
-/**
- * @}
- */ /* end of group PORT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
- * @{
- */
-
-/** RCM - Register Layout Typedef */
-typedef struct {
- __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
- __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
- uint8_t RESERVED_0[2];
- __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
- __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
-} RCM_Type;
-
-/* ----------------------------------------------------------------------------
- -- RCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Register_Masks RCM Register Masks
- * @{
- */
-
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-
-/**
- * @}
- */ /* end of group RCM_Register_Masks */
-
-
-/* RCM - Peripheral instance base addresses */
-/** Peripheral RCM base address */
-#define RCM_BASE (0x4007F000u)
-/** Peripheral RCM base pointer */
-#define RCM ((RCM_Type *)RCM_BASE)
-/** Array initializer of RCM peripheral base pointers */
-#define RCM_BASES { RCM }
-
-/**
- * @}
- */ /* end of group RCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- ROM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
- * @{
- */
-
-/** ROM - Register Layout Typedef */
-typedef struct {
- __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
- __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
- uint8_t RESERVED_0[4028];
- __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
- __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
- __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
- __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
- __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
- __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
- __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
- __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
- __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
- __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} ROM_Type;
-
-/* ----------------------------------------------------------------------------
- -- ROM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ROM_Register_Masks ROM Register Masks
- * @{
- */
-
-/* ENTRY Bit Fields */
-#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
-#define ROM_ENTRY_ENTRY_SHIFT 0
-#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
-/* TABLEMARK Bit Fields */
-#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
-#define ROM_TABLEMARK_MARK_SHIFT 0
-#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
-/* SYSACCESS Bit Fields */
-#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
-#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
-#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
-/* PERIPHID4 Bit Fields */
-#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID4_PERIPHID_SHIFT 0
-#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
-/* PERIPHID5 Bit Fields */
-#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID5_PERIPHID_SHIFT 0
-#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
-/* PERIPHID6 Bit Fields */
-#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID6_PERIPHID_SHIFT 0
-#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
-/* PERIPHID7 Bit Fields */
-#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID7_PERIPHID_SHIFT 0
-#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
-/* PERIPHID0 Bit Fields */
-#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID0_PERIPHID_SHIFT 0
-#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
-/* PERIPHID1 Bit Fields */
-#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID1_PERIPHID_SHIFT 0
-#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
-/* PERIPHID2 Bit Fields */
-#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID2_PERIPHID_SHIFT 0
-#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
-/* PERIPHID3 Bit Fields */
-#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID3_PERIPHID_SHIFT 0
-#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
-#define ROM_COMPID_COMPID_SHIFT 0
-#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group ROM_Register_Masks */
-
-
-/* ROM - Peripheral instance base addresses */
-/** Peripheral ROM base address */
-#define ROM_BASE (0xF0002000u)
-/** Peripheral ROM base pointer */
-#define ROM ((ROM_Type *)ROM_BASE)
-/** Array initializer of ROM peripheral base pointers */
-#define ROM_BASES { ROM }
-
-/**
- * @}
- */ /* end of group ROM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
- __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
- __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
- __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
- __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
- __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
- __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
- __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
-} RTC_Type;
-
-/* ----------------------------------------------------------------------------
- -- RTC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-#define RTC_IER_WPON_MASK 0x80u
-#define RTC_IER_WPON_SHIFT 7
-
-/**
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4003D000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASES { RTC }
-
-/**
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
- * @{
- */
-
-/** SIM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
- __I uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
- uint8_t RESERVED_0[4092];
- __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
- __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
- uint8_t RESERVED_2[4];
- __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
- uint8_t RESERVED_3[8];
- __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
- uint8_t RESERVED_4[12];
- __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
- __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
- __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
- __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
- __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
- uint8_t RESERVED_5[4];
- __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
- __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
- uint8_t RESERVED_6[4];
- __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
- __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
- __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
- uint8_t RESERVED_7[156];
- __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
- __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
-} SIM_Type;
-
-/* ----------------------------------------------------------------------------
- -- SIM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Register_Masks SIM Register Masks
- * @{
- */
-
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
-#define SIM_SOPT2_TPMSRC_SHIFT 24
-#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
-#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
-#define SIM_SOPT2_UART0SRC_SHIFT 26
-#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
-#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
-#def