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#ifndef hal_phy_inc_regs_h
#define hal_phy_inc_regs_h
/* Cesar project {{{
 *
 * Copyright (C) 2008 Spidcom
 *
 * <<<Licence>>>
 *
 * }}} */
/**
 * \file    hal/phy/inc/regs.h
 * \brief   HAL Phy registers.
 * \ingroup hal_phy
 */

#include "hal/phy/inc/regs_addr.h"

typedef u32 uint32_t;

/** Fill with default parameters. */
#define PHY_PARAMS(reg, param, f...) \
    (0 PREPROC_FOR_EACH_PARAM (PHY_PARAMS_FIELD_, (reg, param), f))
#define PHY_PARAMS_FIELD_(reg_param, f) \
    PHY_PARAMS_FIELD__ (PREPROC_UNPACK (reg_param), f)
#define PHY_PARAMS_FIELD__(reg_param, f) \
    PHY_PARAMS_FIELD___ (reg_param, f)
#define PHY_PARAMS_FIELD___(reg, param, f) \
    | BF_SHIFT (reg ## _ ## param ## __ ## f, PHY_PARAM_ ## param ## __ ## f)

/*** PRATIC ***/

/* CONFIG */
#define PHY_PRATIC_CONFIG__DIVISION_FACTOR 20, 0
#define PHY_PRATIC_CONFIG__SLOT_SIZE 31, 21

/* ACTION */
#define PHY_PRATIC_ACTION__NOP            0x00
#define PHY_PRATIC_ACTION__CREATE_PRE     0x01
#define PHY_PRATIC_ACTION__CREATE_PRS     0x02
#define PHY_PRATIC_ACTION__CREATE_FC_10   0x03
#define PHY_PRATIC_ACTION__INIT_TX        0x04
#define PHY_PRATIC_ACTION__TMD_START      0x05
#define PHY_PRATIC_ACTION__PBD_START      0x06
#define PHY_PRATIC_ACTION__START_TX       0x07
#define PHY_PRATIC_ACTION__START_PRP      0x08
#define PHY_PRATIC_ACTION__START_FFT      0x09
#define PHY_PRATIC_ACTION__SEND_SYMB      0x0a
#define PHY_PRATIC_ACTION__SEARCH_PRE     0x0b
#define PHY_PRATIC_ACTION__SEARCH_PRS     0x0c
#define PHY_PRATIC_ACTION__STOP_DETECT    0x0d
#define PHY_PRATIC_ACTION__INTERRUPT1     0x0e
#define PHY_PRATIC_ACTION__ACCESS         0x0f
#define PHY_PRATIC_ACTION__START_ACQU     0x10
#define PHY_PRATIC_ACTION__STOP_ACQU      0x11
#define PHY_PRATIC_ACTION__INIT_RX        0x12
#define PHY_PRATIC_ACTION__START_MAFADESE 0x13
#define PHY_PRATIC_ACTION__STOP_MAFADESE  0x14

/* CSMA */
#define PHY_PRATIC_CSMA__MPDU_CAP 1, 0
#define PHY_PRATIC_CSMA__SENT_CAP 3, 2
#define PHY_PRATIC_CSMA__MEDIUM_CAP 5, 4
#define PHY_PRATIC_CSMA__NB_SLOTS 15, 8
#define PHY_PRATIC_CSMA__FALSE_ALARM 16, 16
#define PHY_PRATIC_CSMA__TX_PRIORITY_LOST 17, 17
#define PHY_PRATIC_CSMA__TX_WHILE_RX 18, 18
#define PHY_PRATIC_CSMA__TX_CANCEL_DUE_TO_FALSE_ALARM 19, 19
#define PHY_PRATIC_CSMA__FALSE_ALARM_MASK 20, 20
#define PHY_PRATIC_CSMA__TX_PRIORITY_LOST_MASK 21, 21
#define PHY_PRATIC_CSMA__TX_WHILE_RX_MASK 22, 22
#define PHY_PRATIC_CSMA__TX_CANCEL_DUE_TO_FALSE_ALARM_MASK 23, 23

/* FFT_PARAM */
#define PHY_PRATIC_FFT_PARAM__SIZE 0, 0
#  define PHY_PRATIC_FFT_PARAM__SIZE__384 0
#  define PHY_PRATIC_FFT_PARAM__SIZE__3072 1
#define PHY_PRATIC_FFT_PARAM__DIRECTION 1, 1
#  define PHY_PRATIC_FFT_PARAM__DIRECTION__IFFT 0
#  define PHY_PRATIC_FFT_PARAM__DIRECTION__FFT 1
#define PHY_PRATIC_FFT_PARAM__SMALL_BUFFER_INDEX 4, 2
#define PHY_PRATIC_FFT_PARAM__FIRST_MEM 7, 5
#define PHY_PRATIC_FFT_PARAM__FIRST_ADD 18, 8

/* SEND_SYMB_PARAM */
#define PHY_PRATIC_SEND_SYMB_PARAM__TYPE 2, 0

/* TIMER_X_CTRL */
#define PHY_PRATIC_TIMER_X_CTRL__VALID 0, 0
#define PHY_PRATIC_TIMER_X_CTRL__TIME_SOURCE 1, 1
#define PHY_PRATIC_TIMER_X_CTRL__ACTION 6, 2
#define PHY_PRATIC_TIMER_X_CTRL__ACTION_2 11, 7

/*** DSP SS ***/

/* COMMON_MODE */
#define PHY_DSPSS_COMMON_MODE__USE_CRC_FC 0, 0
#define PHY_DSPSS_COMMON_MODE__USE_CRC_PB 1, 1

/* TMD_CTRL */
#define PHY_DSPSS_TMD_CTRL__BUSY 0, 0
#define PHY_DSPSS_TMD_CTRL__DONE 1, 1
#define PHY_DSPSS_TMD_CTRL__ERROR 2, 2

/* TX_PARAM */
#define PHY_DSPSS_TX_PARAM__PB_SIZE 0, 0
#define PHY_DSPSS_TX_PARAM__PB_RATE 1, 1
#define PHY_DSPSS_TX_PARAM__PB_MOD 3, 2
#define PHY_DSPSS_TX_PARAM__FC_MODE 5, 4
#define PHY_DSPSS_TX_PARAM__LONG_PPDU 6, 6
#define PHY_DSPSS_TX_PARAM__USE_SCRAMBLER 7, 7
#define PHY_DSPSS_TX_PARAM__TMBI 15, 8
#define PHY_DSPSS_TX_PARAM__NB_PB_SOUND 23, 16
#define PHY_DSPSS_TX_PARAM__USE_ADAPT_TABLE 24, 24
#define PHY_DSPSS_TX_PARAM__USE_AMPLITUDE_MAP 25, 25
#define PHY_DSPSS_TX_PARAM__USE_SHAKER 26, 26
#define PHY_DSPSS_TX_PARAM__SOUND_FRAME 27, 27
#define PHY_DSPSS_TX_PARAM__WRONG_CRC24 30, 30
#define PHY_DSPSS_TX_PARAM__MAMA_DEBUG_ENABLE 31, 31
#  define PHY_DSPSS_TX_PARAM__DEFAULT \
    (BF_MASK (PHY_DSPSS_TX_PARAM__USE_SCRAMBLER) \
     | BF_MASK (PHY_DSPSS_TX_PARAM__USE_AMPLITUDE_MAP) \
     | BF_MASK (PHY_DSPSS_TX_PARAM__USE_SHAKER) \
    )

/* TX_SCALE */
#define PHY_DSPSS_TX_SCALE_ADAPT__GAIN 17, 0
#define PHY_DSPSS_TX_SCALE_ADAPT_BLK_EXP__STEP 2, 0

/* TX_FC_10 */
#define PHY_DSPSS_TX_FC_10__FC 24, 0
#define PHY_DSPSS_TX_FC_10__CRC 31, 31

/* RX_PARAM */
#define PHY_DSPSS_RX_PARAM__PB_SIZE 0, 0
#define PHY_DSPSS_RX_PARAM__PB_RATE 1, 1
#define PHY_DSPSS_RX_PARAM__PB_MOD 3, 2
#define PHY_DSPSS_RX_PARAM__FC_MODE 5, 4
#define PHY_DSPSS_RX_PARAM__LONG_PPDU 6, 6
#define PHY_DSPSS_RX_PARAM__USE_SCRAMBLER 7, 7
#define PHY_DSPSS_RX_PARAM__TMBI 15, 8
#define PHY_DSPSS_RX_PARAM__LOG_SAMPLES 16, 16
#define PHY_DSPSS_RX_PARAM__USE_COEFF 17, 17
#define PHY_DSPSS_RX_PARAM__SOUND_FRAME 27, 27
#define PHY_DSPSS_RX_PARAM__SOUND_ENABLE 28, 28
#define PHY_DSPSS_RX_PARAM__SOUND_ENABLE_LOCK 29, 29
#  define PHY_DSPSS_RX_PARAM__DEFAULT \
    (BF_MASK (PHY_DSPSS_RX_PARAM__USE_SCRAMBLER) \
    )

/* RX_FEC_PARAM */
#define PHY_DSPSS_RX_FEC_PARAM__ME10DOI_MAX_IT 4, 0
#define PHY_DSPSS_RX_FEC_PARAM__TCC_HALF_IT_FC 9, 5
#define PHY_DSPSS_RX_FEC_PARAM__TCC_HALF_IT_DATA 14, 10
#define PHY_DSPSS_RX_FEC_PARAM__TCC_DYN_STOP 15, 15
#define PHY_DSPSS_RX_FEC_PARAM__TCC_BER_PERIOD 23, 16
#define PHY_DSPSS_RX_FEC_PARAM__TCC_THRESHOLD 31, 24

/* RX_FC_10 */
#define PHY_DSPSS_RX_FC_10__FC 24, 0
#define PHY_DSPSS_RX_FC_10__DECODER_SUCCESS 25, 25
#define PHY_DSPSS_RX_FC_10__CRC_OK 26, 26
#define PHY_DSPSS_RX_FC_10__NB_ITERATION_DONE 31, 27
#  define PHY_DSPSS_RX_FC_10__OK_MASK \
    (BF_MASK (PHY_DSPSS_RX_FC_10__DECODER_SUCCESS) \
     | BF_MASK (PHY_DSPSS_RX_FC_10__CRC_OK))

/* RX_FC_AV_STATUS */
#define PHY_DSPSS_RX_FC_AV_STATUS__RECEIVED 0, 0
#define PHY_DSPSS_RX_FC_AV_STATUS__CRC_OK 1, 1

/* X_ROBO_INTERLEAVER_1 */
#define PHY_DSPSS_X_ROBO_INTERLEAVER_1__NPAD 10, 0
#define PHY_DSPSS_X_ROBO_INTERLEAVER_1__BITS_IN_SEGMENT 26, 16

/* X_ROBO_INTERLEAVER_2 */
#define PHY_DSPSS_X_ROBO_INTERLEAVER_2__CYCLE_SHIFT_0 2, 0
#define PHY_DSPSS_X_ROBO_INTERLEAVER_2__CYCLE_SHIFT_1 5, 3
#define PHY_DSPSS_X_ROBO_INTERLEAVER_2__CYCLE_SHIFT_2 8, 6
#define PHY_DSPSS_X_ROBO_INTERLEAVER_2__CYCLE_SHIFT_3 11, 9
#define PHY_DSPSS_X_ROBO_INTERLEAVER_2__CYCLE_SHIFT_4 14, 12
#define PHY_DSPSS_X_ROBO_INTERLEAVER_2__MAX_CARRIER 26, 16

/* TCC_HALF_IT_LAST_PB */
#define PHY_DSPSS_TCC_HALF_IT_LAST_PB__VALUE 4, 0
#define PHY_DSPSS_TCC_HALF_IT_LAST_PB__ENABLED 5, 5
#define PHY_DSPSS_TCC_HALF_IT_LAST_PB__PB_NB 15, 8

/* HPAV_MASK */
#define PHY_DSPSS_HPAV_MASK__NB_CARRIER 10, 0
#define PHY_DSPSS_HPAV_MASK__NB_CARRIER_10 18, 11

/* CHANNEL_ESTIM_COEF */
#define PHY_DSPSS_CHANNEL_ESTIM_COEF__COEF_PREAMBLE 4, 0
#define PHY_DSPSS_CHANNEL_ESTIM_COEF__COEF_RES_DELTA 15, 8

/* RESYS_PARAM */
#define PHY_DSPSS_RESYS_PARAM__RESYS_COND 0, 0
#define PHY_DSPSS_RESYS_PARAM__RESYS_ON 1, 1
#define PHY_DSPSS_RESYS_PARAM__RESYS_FREEZE 2, 2
#define PHY_DSPSS_RESYS_PARAM__LAST_SYMB_INDEX 15, 7

/* RESYS_THRESHOLD */
#define PHY_DSPSS_RESYS_THRESHOLD__NB_SYNCP_1 15, 0
#define PHY_DSPSS_RESYS_THRESHOLD__NB_SYNCP_2 31, 16

/* OSYSEQ_CONFIG */
#define PHY_DSPSS_OSYSEQ_CONFIG__STOP_CONDITION 2, 0
#  define PHY_DSPSS_OSYSEQ_CONFIG__STOP_CONDITION__NEVER 0
#  define PHY_DSPSS_OSYSEQ_CONFIG__STOP_CONDITION__EARLY 1
#  define PHY_DSPSS_OSYSEQ_CONFIG__STOP_CONDITION__PRE 2
#  define PHY_DSPSS_OSYSEQ_CONFIG__STOP_CONDITION__EARLY_PRE 3
#  define PHY_DSPSS_OSYSEQ_CONFIG__STOP_CONDITION__RX 4
#  define PHY_DSPSS_OSYSEQ_CONFIG__STOP_CONDITION__RX_PRE 5

/* DETECT_PARAM_1 */
#define PHY_DSPSS_DETECT_PARAM_1__LAMBDA 15, 0
#define PHY_DSPSS_DETECT_PARAM_1__GAMMA 31, 16

/* DETECT_PARAM_2 */
#define PHY_DSPSS_DETECT_PARAM_2__DMIN 15, 0
#define PHY_DSPSS_DETECT_PARAM_2__DMAX 31, 16

/* DETECT_PARAM_3 */
#define PHY_DSPSS_DETECT_PARAM_3__AFE_IN_BLOCK_EXP 15, 0
#define PHY_DSPSS_DETECT_PARAM_3__USE_BAND_0 16, 16
#define PHY_DSPSS_DETECT_PARAM_3__USE_BAND_1 17, 17
#define PHY_DSPSS_DETECT_PARAM_3__MSB_FILTER_0_CHOICE 22, 18
#define PHY_DSPSS_DETECT_PARAM_3__MSB_FILTER_1_CHOICE 27, 23

/* DETECT_PARAM_4 */
#define PHY_DSPSS_DETECT_PARAM_4__DELAY_BEFORE_DETECT 8, 0
#define PHY_DSPSS_DETECT_PARAM_4__DELAY_FREEZE 17, 9
#define PHY_DSPSS_DETECT_PARAM_4__ACTIVATION_INIT_REFERENCE 31, 31

/* MAGIC_PARAM_1 */
#define PHY_DSPSS_MAGIC_PARAM_1__TARGET_NRJ 15, 0
#define PHY_DSPSS_MAGIC_PARAM_1__CONVERGENCE_TOLERANCE 31, 16

/* MAGIC_PARAM_2 */
#define PHY_DSPSS_MAGIC_PARAM_2__DIVERGENCE_TOLERANCE 15, 0
#define PHY_DSPSS_MAGIC_PARAM_2__CONSTANT_GAIN_THRESHOLD 31, 16

/* MAGIC_PARAM_3 */
#define PHY_DSPSS_MAGIC_PARAM_3__MAX_GAIN 7, 0
#define PHY_DSPSS_MAGIC_PARAM_3__MANUAL_PGA_VALUE 13, 8
#define PHY_DSPSS_MAGIC_PARAM_3__PGA_MANUAL 15, 15
#define PHY_DSPSS_MAGIC_PARAM_3__OVERFLOW_GAIN_RESET 23, 16
#define PHY_DSPSS_MAGIC_PARAM_3__AGC_MANUAL 24, 24
#define PHY_DSPSS_MAGIC_PARAM_3__AGC_MANUAL_START 25, 25
/* The 3 following BYPASS_RX_FILTER bits are only considered for MSE500-300.
 * They are ignored for SPC300 (The Rx filter can not be bypassed).
 * They are ignored for MSE500-500 (The Rx filter is always bypassed). */
#define PHY_DSPSS_MAGIC_PARAM_3__BYPASS_RX_FILTER_FOR_RX_MEM 26, 26
#define PHY_DSPSS_MAGIC_PARAM_3__BYPASS_RX_FILTER_FOR_MAGIC 27, 27
#define PHY_DSPSS_MAGIC_PARAM_3__BYPASS_RX_FILTER_FOR_MAFADESE 28, 28

/* MAGIC_PARAM_4 */
#define PHY_DSPSS_MAGIC_PARAM_4__LAST_AGC_GAIN_VALUE 5, 0
#define PHY_DSPSS_MAGIC_PARAM_4__CURRENT_AGC_GAIN_VALUE 13, 8

/* RESYS_DETECT_OFFSET */
#define PHY_DSPSS_RESYS_DETECT_OFFSET__PREAMBLE 11, 0
#define PHY_DSPSS_RESYS_DETECT_OFFSET__MUFTI_START_ADDRESS 29, 16

/* RESYS_DEBUG_1 */
#define PHY_DSPSS_RESYS_DEBUG_1__SYMBOL_COUNT 7, 0
#define PHY_DSPSS_RESYS_DEBUG_1__SAMPLE_COUNT 26, 8

/* RESYS_DEBUG_2 */
#define PHY_DSPSS_RESYS_DEBUG_2__NEXT_SYMBOL_TRANSITION 18, 0

/* TIME_CHAIN_INFO */
#define PHY_DSPSS_TIME_CHAIN_INFO__CREATION_IN_PROGRESS 8, 8

/* MABEILLE_MODE */
#define PHY_DSPSS_MABEILLE_MODE__DEBUG_MODE_MUFTI 0, 0
#define PHY_DSPSS_MABEILLE_MODE__DEBUG_MODE_TX_MEM 1, 1
#define PHY_DSPSS_MABEILLE_MODE__DEBUG_MODE_RX_MEM 2, 2
#define PHY_DSPSS_MABEILLE_MODE__DEBUG_MODE_PRE_MEM 3, 3
#define PHY_DSPSS_MABEILLE_MODE__DEBUG_MODE_PRS_MEM 4, 4

/* PHY_DSPSS_MACACKE_DELTA_USED */
#define PHY_DSPSS_MACACKE_DELTA_USED__VALUE 16, 0
#define PHY_DSPSS_MACACKE_DELTA_USED__INTERNAL 24, 24
#  define PHY_DSPSS_MACACKE_DELTA_USED__VALUE__RHO_Q 27

/* TX_GUARD_LENGTH */
#  define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_FC_10 192
#  define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_FC_AV (1374 + 372)
#  define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_417 (417 + 372)
#  define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_567 (567 + 372)
#  define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_3534 (3534 + 372)

/* TX_SYMB_LENGTH */
#  define PHY_DSPSS_TX_SYMB_LENGTH__VALUE_PRE (10 * 384 - 372)
#  define PHY_DSPSS_TX_SYMB_LENGTH__VALUE_PRE_10 (9 * 384 - 372)
#  define PHY_DSPSS_TX_SYMB_LENGTH__VALUE_FC_AV (1374 + 3072)
#  define PHY_DSPSS_TX_SYMB_LENGTH__VALUE_FC_10 (4 * (246 + 384) + 372)
#  define PHY_DSPSS_TX_SYMB_LENGTH__VALUE_DATA (567 + 3072)

/* SPOC_FILTER_SHIFT */
#define PHY_DSPSS_SPOC_FILTER_SHIFT__D_MUL 1, 0
#define PHY_DSPSS_SPOC_FILTER_SHIFT__M_MUL 3, 2
#define PHY_DSPSS_SPOC_FILTER_SHIFT__M_ADD1 5, 4
#define PHY_DSPSS_SPOC_FILTER_SHIFT__M_ADD2 7, 6
#define PHY_DSPSS_SPOC_FILTER_SHIFT__M_ADD3 9, 8
#define PHY_DSPSS_SPOC_FILTER_SHIFT__M_ADD4 11, 10
#define PHY_DSPSS_SPOC_FILTER_SHIFT__M_ADD5 13, 12
#define PHY_DSPSS_SPOC_FILTER_SHIFT__M_ADD6 15, 14
#define PHY_DSPSS_SPOC_FILTER_SHIFT__MAPPOWSE_ADD1 17, 16
#define PHY_DSPSS_SPOC_FILTER_SHIFT__MAPPOWSE_ADD2 19, 18
#define PHY_DSPSS_SPOC_FILTER_SHIFT__MAPPOWSE_ADD3 21, 20
#define PHY_DSPSS_SPOC_FILTER_SHIFT__MAPPOWSE_ADD4 23, 22
#define PHY_DSPSS_SPOC_FILTER_SHIFT__MAPPOWSE_ADD5 25, 24

/* SPOC_OFFSET_BLK_EXP */
#define PHY_DSPSS_SPOC_OFFSET_BLK_EXP__SPOC_TX 6, 0
#define PHY_DSPSS_SPOC_OFFSET_BLK_EXP__MAPPOWSE_TX 14, 7

/* SPOC_SET_REQUEST */
#define PHY_DSPSS_SPOC_SET_REQUEST__NONE 0
#define PHY_DSPSS_SPOC_SET_REQUEST__TX 1
#define PHY_DSPSS_SPOC_SET_REQUEST__RX 2
#define PHY_DSPSS_SPOC_SET_REQUEST__WIENER 3

/* SPOC_DEBUG_MODE */
#define PHY_DSPSS_SPOC_DEBUG_MODE__RX_OR_WIENER_IN_TX_MEMORY 0, 0
#define PHY_DSPSS_SPOC_DEBUG_MODE__D_MATRIX_UNUSED 1, 1
#define PHY_DSPSS_SPOC_DEBUG_MODE__M_MATRIX_UNUSED 2, 2
#define PHY_DSPSS_SPOC_DEBUG_MODE__M_MATRIX_WITHOUT_PHASE 3, 3
#define PHY_DSPSS_SPOC_DEBUG_MODE__BYPASS 4, 4

/* WIENER_CHANNEL_MAX_DETECTION_PARAM */
#define PHY_DSPSS_WIENER_CHANNEL_MAX_DETECTION_PARAM__FREQ_HOLE_WIDTH 7, 0
#define PHY_DSPSS_WIENER_CHANNEL_MAX_DETECTION_PARAM__SOFT_ADDR 16, 8
#define PHY_DSPSS_WIENER_CHANNEL_MAX_DETECTION_PARAM__SOFT_ADDR_SEL 17, 17
#define PHY_DSPSS_WIENER_CHANNEL_MAX_DETECTION_PARAM__ERASING_ON 18, 18

/* WIENER_CHANNEL_MAX_DETECTION_VALUE */
#define PHY_DSPSS_WIENER_CHANNEL_MAX_DETECTION_VALUE__BLOCK_EXP 6, 0
#define PHY_DSPSS_WIENER_CHANNEL_MAX_DETECTION_VALUE__VALUE 24, 7

/* MIA_PARAM */
#define PHY_DSPSS_MIA_PARAM__USE_SNR_IN_LLR 0, 0

/* MIA_SF_X */
#  define PHY_DSPSS_MIA_SF_X__MAX (1u << 10)

/*** PB DMA ***/

/* CTRL_CONFIG */
#define PHY_PBDMA_CTRL_CONFIG__START_DATA 0, 0
#define PHY_PBDMA_CTRL_CONFIG__START_CHANDATA 1, 1
#define PHY_PBDMA_CTRL_CONFIG__CHANDATA_WAIT_START 2, 2
#define PHY_PBDMA_CTRL_CONFIG__AES_BYPASS 3, 3
#define PHY_PBDMA_CTRL_CONFIG__TX_WRONG_CRC_EN 4, 4
#define PHY_PBDMA_CTRL_CONFIG__IV_3_REG 5, 5
#define PHY_PBDMA_CTRL_CONFIG__IV_012_REG 6, 6
#define PHY_PBDMA_CTRL_CONFIG__HPROT 10, 7
#  define PHY_PBDMA_CTRL_CONFIG__HPROT__DEFAULT 1
#  define PHY_PBDMA_CTRL_CONFIG__DEFAULT 0

/* STATUS_ERROR */
#define PHY_PBDMA_STATUS_ERROR__PB_NULL 0, 0
#define PHY_PBDMA_STATUS_ERROR__RX_HEADER_LOAD_ERROR 1, 1
#define PHY_PBDMA_STATUS_ERROR__AHB_RESPONSE_ERROR 2, 2
#define PHY_PBDMA_STATUS_ERROR__PB_CRC_ERROR 3, 3
#define PHY_PBDMA_STATUS_ERROR__CURRENT_PB_INDEX 11, 4
#define PHY_PBDMA_STATUS_ERROR__CHANDATA_TYPE_FORBIDDEN 12, 12
#define PHY_PBDMA_STATUS_ERROR__CHANDATA_SIZE_FORBIDDEN 13, 13
#define PHY_PBDMA_STATUS_ERROR__PB_NB_TOTAL_NULL 14, 14
#define PHY_PBDMA_STATUS_ERROR__FSM_STATE 17, 16
#define PHY_PBDMA_STATUS_ERROR__PB_IT 18, 18
#define PHY_PBDMA_STATUS_ERROR__END_RX_PB 20, 20
#define PHY_PBDMA_STATUS_ERROR__END_TX_PB 21, 21
#define PHY_PBDMA_STATUS_ERROR__END_CHANDATA 22, 22
#define PHY_PBDMA_STATUS_ERROR__NULL_PB_INDEX 31, 24
#  define PHY_PBDMA_STATUS_ERROR__FSM_STATE__IDLE 0
#  define PHY_PBDMA_STATUS_ERROR__FSM_STATE__CHANDATA 1
#  define PHY_PBDMA_STATUS_ERROR__FSM_STATE__RX 2
#  define PHY_PBDMA_STATUS_ERROR__FSM_STATE__TX 3

/* CONFIG_PB */
#define PHY_PBDMA_CONFIG_PB__PB_NB_TOTAL 7, 0
#define PHY_PBDMA_CONFIG_PB__PB_NB_READY 15, 8
#define PHY_PBDMA_CONFIG_PB__PB_NB_IT 23, 16

/* DESC_BER_HALFIT */
#define PHY_PBDMA_DESC_BER_HALFIT__BER 15, 0
#define PHY_PBDMA_DESC_BER_HALFIT__HALFIT 20, 16
#define PHY_PBDMA_DESC_BER_HALFIT__CRC_STATUS 21, 21

/*** RESYS ***/

#define PHY_RESYS_GIL_OFFSET 14
#  define PHY_RESYS_GIL_OFFSET__VALUE_417 (417 + 3072)
#  define PHY_RESYS_GIL_OFFSET__VALUE_567 (567 + 3072)
#  define PHY_RESYS_GIL_OFFSET__VALUE_3534 (3534 + 3072)

#endif /* hal_phy_inc_regs_h */