#ifndef synop3504_regdef_h #define synop3504_regdef_h /* GMAC registers, base address is BAR+GmacRegistersBase */ enum GmacRegisters { /** config */ GmacConfig = 0x00, /** frame filter */ GmacFrameFilter = 0x04, /** multi-cast hash table high */ GmacHashHigh = 0x08, /** multi-cast hash table low */ GmacHashLow = 0x0C, /** GMII address */ GmacGmiiAddr = 0x10, /** GMII data */ GmacGmiiData = 0x14, /** Flow control */ GmacFlowControl = 0x18, /** VLAN tag */ GmacVlan = 0x1C, /** Version of Gmac */ GmacVersion = 0x20, /** Gmac interupt status */ GmacIntStatus = 0x38, /** Gmac interupt status */ GmacIntMask = 0x3C, /** address0 high */ GmacAddr0High = 0x40, /** address0 low */ GmacAddr0Low = 0x44, /** address1 high */ GmacAddr1High = 0x48, /** address1 low */ GmacAddr1Low = 0x4C, /** address2 high */ GmacAddr2High = 0x50, /** address2 low */ GmacAddr2Low = 0x54, /** address3 high */ GmacAddr3High = 0x58, /** address3 low */ GmacAddr3Low = 0x5C, /** address4 high */ GmacAddr4High = 0x60, /** address4 low */ GmacAddr4Low = 0x64, /** address5 high */ GmacAddr5High = 0x68, /** address5 low */ GmacAddr5Low = 0x6C, /** address6 high */ GmacAddr6High = 0x70, /** address6 low */ GmacAddr6Low = 0x74, /** address7 high */ GmacAddr7High = 0x78, /** address7 low */ GmacAddr7Low = 0x7C, /** address8 high */ GmacAddr8High = 0x80, /** address8 low */ GmacAddr8Low = 0x84, /** address9 high */ GmacAddr9High = 0x88, /** address9 low */ GmacAddr9Low = 0x8C, /** address10 high */ GmacAddr10High = 0x90, /** address10 low */ GmacAddr10Low = 0x94, /** address11 high */ GmacAddr11High = 0x98, /** address11 low */ GmacAddr11Low = 0x9C, /** address12 high */ GmacAddr12High = 0xA0, /** address12 low */ GmacAddr12Low = 0xA4, /** address13 high */ GmacAddr13High = 0xA8, /** address13 low */ GmacAddr13Low = 0xAC, /** address14 high */ GmacAddr14High = 0xB0, /** address14 low */ GmacAddr14Low = 0xB4, /** address15 high */ GmacAddr15High = 0xB8, /** address15 low */ GmacAddr15Low = 0xBC, /* AN registers */ /** AN Control */ GmacANControl = 0xC0, /** AN Status */ GmacANStatus = 0xC4, /** AN Advertisement */ GmacANAdwert = 0xC8, /** AN Link Partner Abilitye */ GmacANLPA = 0xCC, /** AN Expansion */ GmacANExpansion = 0xD0, }; /* DMA engine registers, base address is BAR+DmaRegistersBase */ enum DmaRegisters { /** CSR0 - Bus Mode */ DmaBusMode = 0x00, /** CSR1 - Transmit Poll Demand */ DmaTxPollDemand = 0x04, /** CSR2 - Receive Poll Demand */ DmaRxPollDemand = 0x08, /** CSR3 - Receive list base address */ DmaRxBaseAddr = 0x0C, /** CSR4 - Transmit list base address */ DmaTxBaseAddr = 0x10, /** CSR5 - Dma status */ DmaStatus = 0x14, /** CSR6 - Dma control */ DmaControl = 0x18, /** CSR7 - Interrupt enable */ DmaInterrupt = 0x1C, /** CSR8 - Missed Frame Counter */ DmaMissedFr = 0x20, /** CSR20 - Current host transmit buffer address */ DmaTxCurrDesc = 0x48, /** CSR20 - Current host transmit buffer address */ DmaRxCurrDesc = 0x4C, /** CSR21 - Current host receive buffer address */ DmaTxCurrBuff = 0x50, /** CSR21 - Current host receive buffer address */ DmaRxCurrBuff = 0x54, /** CSR20 - Current host transmit buffer address */ //DmaTxCurrAddr = 0x50, /** CSR21 - Current host receive buffer address */ //DmaRxCurrAddr = 0x54, }; /********************************************************** * GMAC Network interface registers **********************************************************/ /* GMAC Config register layout */ enum GmacConfigReg { /* Bit description R/W Reset value */ /** Disable watchdog timer RW */ GmacWatchdogDisable = 0x00800000, /** Enable watchdog timer 0 */ GmacWatchdogEnable = 0, /** Disable jabber timer RW */ GmacJabberDisable = 0x00400000, /** Enable jabber timer 0 */ GmacJabberEnable = 0, /** Enable frame bursting RW */ GmacFrameBurstEnable = 0x00200000, /** Disable frame bursting 0 */ GmacFrameBurstDisable = 0, /** Enable jumbo frame RW */ GmacJumboFrameEnable = 0x00100000, /** Disable jumbo frame 0 */ GmacJumboFrameDisable = 0, // CHANGE: Added on 07/28 SNPS /** IFG Config7 - 40 bit times RW 000 */ GmacInterFrameGap7 = 0x000E0000, /** IFG Config6 - 48 bit times */ GmacInterFrameGap6 = 0x000C0000, /** IFG Config5 - 56 bit times */ GmacInterFrameGap5 = 0x000A0000, /** IFG Config4 - 64 bit times */ GmacInterFrameGap4 = 0x00080000, /** IFG Config3 - 72 bit times */ GmacInterFrameGap3 = 0x00040000, /** IFG Config2 - 80 bit times */ GmacInterFrameGap2 = 0x00020000, /** IFG Config1 - 88 bit times */ GmacInterFrameGap1 = 0x00010000, /** IFG Config0 - 96 bit times */ GmacInterFrameGap0 = 000, /** Select MII mode RW */ GmacSelectMii = 0x00008000, /** Select GMII mode 0 */ GmacSelectGmii = 0, // CHANGE: Commented as Endian mode is not register configurable /** Big endian mode RW */ //GmacBigEndian = 0x00004000, /** Little endian 0 */ //GmacLittleEndian = 0, /** Disable receive own packets RW */ GmacDisableRxOwn = 0x00002000, /** Enable receive own packets 0 */ GmacEnableRxOwn = 0, /** Loopback mode RW */ GmacLoopbackOn = 0x00001000, /** Normal mode 0 */ GmacLoopbackOff = 0, /** Full duplex mode RW */ GmacFullDuplex = 0x00000800, /** Half duplex mode 0 */ GmacHalfDuplex = 0, /** Disable retransmission RW */ GmacRetryDisable = 0x00000200, /** Enable retransmission 0 */ GmacRetryEnable = 0, // CHANGE: Commented as Pad / CRC strip is one single bit /** Pad stripping enable RW */ //GmacPadStripEnable = 0x00000100, /** Pad stripping disable 0 */ //GmacPadStripDisable = 0, // CHANGE: 07/28 renamed GmacCrcStrip* GmacPadCrcStrip* /** Pad / Crc stripping enable RW */ GmacPadCrcStripEnable = 0x00000080, /** Pad / Crc stripping disable 0 */ GmacPadCrcStripDisable = 0, /** Back-off limit RW */ GmacBackoffLimit3 = 0x00000060, /** */ GmacBackoffLimit2 = 0x00000040, /** */ GmacBackoffLimit1 = 0x00000020, /** 00 */ GmacBackoffLimit0 = 0, /** Deferral check enable RW */ GmacDeferralCheckEnable = 0x00000010, /** Deferral check disable 0 */ GmacDeferralCheckDisable = 0, /** Transmitter enable RW */ GmacTxEnable = 0x00000008, /** Transmitter disable 0 */ GmacTxDisable = 0, /** Receiver enable RW */ GmacRxEnable = 0x00000004, /** Receiver disable 0 */ GmacRxDisable = 0, }; /* GMAC frame filter register layout */ enum GmacFrameFilterReg { /** Receive all incoming packets RW */ GmacFilterOff = 0x80000000, /** Receive filtered packets only 0 */ GmacFilterOn = 0, // CHANGE: Added on 07/28 SNPS /** Source Address Filter enable RW */ GmacSrcAddrFilterEnable = 0x00000200, /** 0 */ GmacSrcAddrFilterDisable = 0, // CHANGE: Added on 07/28 SNPS /** Inverse Source Address Filter enable RW */ GmacSrcInvAddrFilterEn = 0x00000100, /** 0 */ GmacSrcInvAddrFilterDis = 0, // CHANGE: Changed the control frame config (07/28) /** Forwards control frames that pass AF RW */ GmacPassControl3 = 0x000000C0, /** Forwards all control frames */ GmacPassControl2 = 0x00000080, /** Does not pass control frames */ GmacPassControl1 = 0x00000040, /** Does not pass control frames 00 */ GmacPassControl0 = 00, /** Disable reception of broadcast frames RW */ GmacBroadcastDisable = 0x00000020, /** Enable broadcast frames 0 */ GmacBroadcastEnable = 0, /** Pass all multicast packets RW */ GmacMulticastFilterOff = 0x00000010, /** Pass filtered multicast packets 0 */ GmacMulticastFilterOn = 0, // CHANGE: Changed to Dest Addr Filter Inverse (07/28) /** Inverse filtering for DA RW */ GmacDestAddrFilterInv = 0x00000008, /** Normal filtering for DA 0 */ GmacDestAddrFilterNor = 0, // CHANGE: Changed to Multicast Hash filter (07/28) /** perfom multicast hash filtering RW */ GmacMcastHashFilterOn = 0x00000004, /** perfect filtering only 0 */ GmacMcastHashFilterOff = 0, // CHANGE: Changed to Unicast Hash filter (07/28) /** Unicast Hash filtering only RW */ GmacUcastHashFilterOn = 0x00000002, /** perfect filtering only 0 */ GmacUcastHashFilterOff = 0, /** Receive all valid packets RW */ GmacPromiscuousModeOn = 0x00000001, /** Receive filtered packets only 0 */ GmacPromiscuousModeOff = 0, }; /* GMII address register layout */ enum GmacGmiiAddrReg { /** GMII device address */ GmiiDevMask = 0x0000F800, GmiiDevShift = 11, /** GMII register */ GmiiRegMask = 0x000007C0, GmiiRegShift = 6, // CHANGED: 3-bit config instead of older 2-bit (07/28) /** Application Clock Range 250-300 MHz */ GmiiAppClk5 = 0x00000014, /** 150-250 MHz */ GmiiAppClk4 = 0x00000010, /** 35-60 MHz */ GmiiAppClk3 = 0x0000000C, /** 20-35 MHz */ GmiiAppClk2 = 0x00000008, /** 100-150 MHz */ GmiiAppClk1 = 0x00000004, /** 60-100 MHz */ GmiiAppClk0 = 0, /** Write to register */ GmiiWrite = 0x00000002, /** Read from register */ GmiiRead = 0, /** GMII interface is busy */ GmiiBusy = 0x00000001, }; enum GmacGmiiDataReg /* GMII address register layout */ { GmiiDataMask = 0x0000FFFF, /* GMII Data */ }; /* GMAC flow control register layout */ enum GmacFlowControlReg { /* Bit description R/W Reset value */ /** PAUSE TIME field in the control frame RW 0000 */ GmacPauseTimeMask = 0xFFFF0000, GmacPauseTimeShift = 16, // CHANGED: Added on (07/28) /** threshold for pause tmr 256 slot time RW 00 */ GmacPauseLowThresh3 = 0x00000030, /** 144 slot time */ GmacPauseLowThresh2 = 0x00000020, /** 28 slot time */ GmacPauseLowThresh1 = 0x00000010, /** 4 slot time */ GmacPauseLowThresh0 = 0, /** Detect pause frame with unicast addr. RW */ GmacUnicastPauseFrameOn = 0x00000008, /** Detect only pause frame with multicast addr. 0 */ GmacUnicastPauseFrameOff = 0, /** Enable Rx flow control RW */ GmacRxFlowControlEnable = 0x00000004, /** Disable Rx flow control 0 */ GmacRxFlowControlDisable = 0, /** Enable Tx flow control RW */ GmacTxFlowControlEnable = 0x00000002, /** Disable flow control 0 */ GmacTxFlowControlDisable = 0, /** send pause frame RW 0 */ GmacSendPauseFrame = 0x00000001, }; enum GmacAN { GmacANCLoopback = (1 << 14), GmacANCEnable = (1 << 12), GmacANCRestart = (1 << 9), GmacANSComplete = (1 << 5), GmacANSLink = (1 << 2), GmacANAHalfDuplex = (1 << 6), GmacANAFullDuplex = (1 << 5), }; /********************************************************** * DMA Engine registers **********************************************************/ /* DMA bus mode register */ enum DmaBusModeReg { /* Bit description R/W Reset value */ // CHANGED: Commented as not applicable (07/28) /** Big endian data buffer descriptors RW */ //DmaBigEndianDesc = 0x00100000, /** Little endian data descriptors 0 */ //DmaLittleEndianDesc = 0, // CHANGED: Added on 07/28 /** Fixed Burst SINGLE, INCR4, INCR8 or INCR16 */ DmaFixedBurstEnable = 0x00010000, /** SINGLE, INCR 0 */ DmaFixedBurstDisable = 0, /** Dma burst length = 32 RW */ DmaBurstLength32 = 0x00002000, /** Dma burst length = 16 */ DmaBurstLength16 = 0x00001000, /** Dma burst length = 8 */ DmaBurstLength8 = 0x00000800, /** Dma burst length = 4 */ DmaBurstLength4 = 0x00000400, /** Dma burst length = 2 */ DmaBurstLength2 = 0x00000200, /** Dma burst length = 1 */ DmaBurstLength1 = 0x00000100, /** Dma burst length = 0 0 */ DmaBurstLength0 = 0x00000000, // CHANGED: Commented as not applicable (07/28) /** Big endian data buffers RW */ //DmaBigEndianData = 0x00000080, /** Little endian data buffers 0 */ //DmaLittleEndianData = 0, /** number of dwords to skip RW */ DmaDescriptorSkip16 = 0x00000040, /** between two unchained descriptors */ DmaDescriptorSkip8 = 0x00000020, /** */ DmaDescriptorSkip4 = 0x00000010, /** */ DmaDescriptorSkip2 = 0x00000008, /** */ DmaDescriptorSkip1 = 0x00000004, /** 0 */ DmaDescriptorSkip0 = 0, /** Reset DMA engine RW */ DmaResetOn = 0x00000001, /** 0 */ DmaResetOff = 0, }; /* DMA Status register */ enum DmaStatusReg { /* Bit description R/W Reset value */ // CHANGED: Added on 07/28 /** Line interface interrupt R 0 */ DmaLineIntfIntr = 0x04000000, // CHANGED: Added on 07/28 /** err. 0-data buffer, 1-desc. access R 0 */ DmaErrorBit2 = 0x02000000, /** err. 0-write trnsf, 1-read transfr R 0 */ DmaErrorBit1 = 0x01000000, /** err. 0-Rx DMA, 1-Tx DMA R 0 */ DmaErrorBit0 = 0x00800000, /** Transmit process state R 000 */ DmaTxState = 0x00700000, /** Stopped */ DmaTxStopped = 0x00000000, /** Running - fetching the descriptor */ DmaTxFetching = 0x00100000, /** Running - waiting for end of transmission */ DmaTxWaiting = 0x00200000, /** Running - reading the data from memory */ DmaTxReading = 0x00300000, /** Suspended */ DmaTxSuspended = 0x00600000, /** Running - closing descriptor */ DmaTxClosing = 0x00700000, /** Receive process state R 000 */ DmaRxState = 0x000E0000, /** Stopped */ DmaRxStopped = 0x00000000, /** Running - fetching the descriptor */ DmaRxFetching = 0x00020000, // CHANGED: Commented as not applicable (07/28) /** Running - checking for end of packet */ //DmaRxChecking = 0x00040000, /** Running - waiting for packet */ DmaRxWaiting = 0x00060000, /** Suspended */ DmaRxSuspended = 0x00080000, /** Running - closing descriptor */ DmaRxClosing = 0x000A0000, // CHANGED: Commented as not applicable (07/28) /** Running - flushing the current frame */ //DmaRxFlushing = 0x000C0000, /** Running - queuing the recieve frame into host memory */ DmaRxQueuing = 0x000E0000, /** Normal interrupt summary RW 0 */ DmaIntNormal = 0x00010000, /** Abnormal interrupt summary RW 0 */ DmaIntAbnormal = 0x00008000, /** Early receive interrupt (Normal) RW 0 */ DmaIntEarlyRx = 0x00004000, /** Fatal bus error (Abnormal) RW 0 */ DmaIntBusError = 0x00002000, /** Early transmit interrupt (Abnormal) RW 0 */ DmaIntEarlyTx = 0x00000400, /** Receive Watchdog Timeout (Abnormal) RW 0 */ DmaIntRxWdogTO = 0x00000200, /** Receive process stopped (Abnormal) RW 0 */ DmaIntRxStopped = 0x00000100, /** Receive buffer unavailable (Abnormal) RW 0 */ DmaIntRxNoBuffer = 0x00000080, /** Completion of frame reception (Normal) RW 0 */ DmaIntRxCompleted = 0x00000040, /** Transmit underflow (Abnormal) RW 0 */ DmaIntTxUnderflow = 0x00000020, // CHANGED: Added on 07/28 /** Receive Buffer overflow interrupt RW 0 */ DmaIntRcvOverflow = 0x00000010, /** Transmit Jabber Timeout (Abnormal) RW 0 */ DmaIntTxJabberTO = 0x00000008, /** Transmit buffer unavailable (Normal) RW 0 */ DmaIntTxNoBuffer = 0x00000004, /** Transmit process stopped (Abnormal) RW 0 */ DmaIntTxStopped = 0x00000002, /** Transmit completed (Normal) RW 0 */ DmaIntTxCompleted = 0x00000001, }; /* DMA control register */ enum DmaControlReg { /* Bit description R/W Reset value */ /** Store and forward RW 0 */ DmaStoreAndForward = 0x00200000, /** Start/Stop transmission RW 0 */ DmaTxStart = 0x00002000, // CHANGED: Added on 07/28 /** Forward error frames RW 0 */ DmaFwdErrorFrames = 0x00000080, /** Forward undersize frames RW 0 */ DmaFwdUnderSzFrames = 0x00000040, /** Operate on second frame RW 0 */ DmaTxSecondFrame = 0x00000004, /** Start/Stop reception RW 0 */ DmaRxStart = 0x00000002, }; /* DMA interrupt enable register */ enum DmaInterruptReg { /* Bit description R/W Reset value */ /** Normal interrupt enable RW 0 */ DmaIeNormal = DmaIntNormal, /** Abnormal interrupt enable RW 0 */ DmaIeAbnormal = DmaIntAbnormal, /** Early receive interrupt enable RW 0 */ DmaIeEarlyRx = DmaIntEarlyRx, /** Fatal bus error enable RW 0 */ DmaIeBusError = DmaIntBusError, /** Early transmit interrupt enable RW 0 */ DmaIeEarlyTx = DmaIntEarlyTx, /** Receive Watchdog Timeout enable RW 0 */ DmaIeRxWdogTO = DmaIntRxWdogTO, /** Receive process stopped enable RW 0 */ DmaIeRxStopped = DmaIntRxStopped, /** Receive buffer unavailable enable RW 0 */ DmaIeRxNoBuffer = DmaIntRxNoBuffer, /** Completion of frame reception enable RW 0 */ DmaIeRxCompleted = DmaIntRxCompleted, /** Transmit underflow enable RW 0 */ DmaIeTxUnderflow = DmaIntTxUnderflow, // CHANGED: Added on 07/28 /** Receive Buffer overflow interrupt RW 0 */ DmaIeRxOverflow = DmaIntRcvOverflow, /** Transmit Jabber Timeout enable RW 0 */ DmaIeTxJabberTO = DmaIntTxJabberTO, /** Transmit buffer unavailable enable RW 0 */ DmaIeTxNoBuffer = DmaIntTxNoBuffer, /** Transmit process stopped enable RW 0 */ DmaIeTxStopped = DmaIntTxStopped, /** Transmit completed enable RW 0 */ DmaIeTxCompleted = DmaIntTxCompleted, }; /********************************************************** * DMA Engine descriptors **********************************************************/ /* status word of DMA descriptor */ enum DmaDescriptorStatus { /** Descriptor is owned by DMA engine */ DescOwnByDma = 0x80000000, // CHANGED: Added on 07/29 /** Rx - DA Filter Fail for the received frame E */ DescDAFilterFail = 0x40000000, /** Receive descriptor frame length */ DescFrameLengthMask = 0x3FFF0000, DescFrameLengthShift = 16, /** Error summary bit - OR of the following bits: v */ DescError = 0x00008000, /** Rx - no more descriptors for receive frame E */ DescRxTruncated = 0x00004000, // CHANGED: Added on 07/29 /** Rx - SA Filter Fail for the received frame E */ DescSAFilterFail = 0x00002000, /* added by reyaz */ /** Rx - frame size not matching with length field E */ DescRxLengthError = 0x00001000, /** Rx - frame was damaged due to buffer overflow E */ DescRxDamaged = 0x00000800, // CHANGED: Added on 07/29 /** Rx - received frame is a VLAN frame I */ DescRxVLANTag = 0x00000400, /** Rx - first descriptor of the frame I */ DescRxFirst = 0x00000200, /** Rx - last descriptor of the frame I */ DescRxLast = 0x00000100, /** Rx - frame is longer than 1518 bytes E */ DescRxLongFrame = 0x00000080, /** Rx - late collision occurred during reception E */ DescRxCollision = 0x00000040, /** Rx - Frame type - Ethernet, otherwise 802.3 */ DescRxFrameEther = 0x00000020, /** Rx - watchdog timer expired during reception E */ DescRxWatchdog = 0x00000010, /** Rx - error reported by MII interface E */ DescRxMiiError = 0x00000008, /** Rx - frame contains noninteger multiple of 8 bits */ DescRxDribbling = 0x00000004, /** Rx - CRC error E */ DescRxCrc = 0x00000002, /** Tx - Transmit jabber timeout E */ DescTxTimeout = 0x00004000, // CHANGED: Added on 07/29 /** Tx - DMA/MTL flushed the frame due to SW flush I */ DescTxFrameFlushed = 0x00002000, /** Tx - carrier lost during tramsmission E */ DescTxLostCarrier = 0x00000800, /** Tx - no carrier signal from the tranceiver E */ DescTxNoCarrier = 0x00000400, /** Tx - transmission aborted due to collision E */ DescTxLateCollision = 0x00000200, /** Tx - transmission aborted after 16 collisions E */ DescTxExcCollisions = 0x00000100, /** Tx - VLAN-type frame */ DescTxVLANFrame = 0x00000080, /** Tx - Collision count */ DescTxCollMask = 0x00000078, DescTxCollShift = 3, /** Tx - excessive deferral E */ DescTxExcDeferral = 0x00000004, /** Tx - late data arrival from the memory E */ DescTxUnderflow = 0x00000002, /** Tx - frame transmision deferred */ DescTxDeferred = 0x00000001, }; /* length word of DMA descriptor */ enum DmaDescriptorLength { /** Tx - interrupt on completion */ DescTxIntEnable = 0x80000000, /** Tx - Last segment of the frame */ DescTxLast = 0x40000000, /** Tx - First segment of the frame */ DescTxFirst = 0x20000000, /** Tx - Add CRC disabled (first segment only) */ DescTxDisableCrc = 0x04000000, /** End of descriptors ring */ DescEndOfRing = 0x02000000, /** Second buffer address is chain address */ DescChain = 0x01000000, /** disable padding, added by - reyaz */ DescTxDisablePadd = 0x00800000, /** Buffer 2 size */ DescSize2Mask = 0x003FF800, DescSize2Shift = 11, /** Buffer 1 size */ DescSize1Mask = 0x000007FF, DescSize1Shift = 0, }; /********************************************************** * Initial register values **********************************************************/ enum InitialRegisters { /* Full-duplex mode with perfect filter on */ GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable /* CHANGED: Removed Endian configuration, added single bit config * for PAD/CRC strip */ | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode with perfect filter on */ GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable /* CHANGED: Removed Endian configuration, added single bit config * for PAD/CRC strip */ | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode */ GmacFrameFilterInitFdx = /* CHANGED: Pass control config, dest addr filter normal, added source * address filter, multicast & unicast Hash filter. */ GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff | GmacPromiscuousModeOff | GmacUcastHashFilterOff, /* Full-duplex mode */ GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, /* Full-duplex mode */ GmacGmiiAddrInitFdx = GmiiAppClk3, /* Half-duplex mode with perfect filter on */ GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode with perfect filter on */ GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacLoopbackOff | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode */ GmacFrameFilterInitHdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff | GmacUcastHashFilterOff | GmacPromiscuousModeOff, /* Half-duplex mode */ GmacFlowControlInitHdx = GmacUnicastPauseFrameOff | GmacRxFlowControlDisable | GmacTxFlowControlDisable, /* Half-duplex mode */ GmacGmiiAddrInitHdx = GmiiAppClk3, /* Little-endian mode */ DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaResetOff, /* 1000 Mb/s mode */ DmaControlInit1000 = DmaStoreAndForward | DmaTxSecondFrame, /* 100 Mb/s mode */ DmaControlInit100 = DmaStoreAndForward, /* 10 Mb/s mode */ DmaControlInit10 = DmaStoreAndForward, /* Interrupt groups */ /** Error */ DmaIntErrorMask = DmaIntBusError, /** receiver abnormal interrupt */ DmaIntRxAbnMask = DmaIntRxNoBuffer, /** receiver normal interrupt */ DmaIntRxNormMask = DmaIntRxCompleted, /** receiver stopped */ DmaIntRxStoppedMask = DmaIntRxStopped, /** transmitter abnormal interrupt */ DmaIntTxAbnMask = DmaIntTxUnderflow, /** transmitter normal interrupt */ DmaIntTxNormMask = DmaIntTxCompleted | DmaIntTxNoBuffer, /** receiver stopped */ DmaIntTxStoppedMask = DmaIntTxStopped, DmaIntMask = DmaIntErrorMask | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, DmaIntDisable = 0, }; #endif /* synop3504_regdef_h */