/************************************************************/ /* Spidcom Technologies FILE NAME : vectors.s DESCRIPTION : CRISTINA nominal vectors HISTORY : -------------------------------------------------------------- DATE | AUTHOR | Version | Description -------------------------------------------------------------- 27/01/04 | Petillon | 1.0 | Creation */ /************************************************************/ #include "arm.h" #include "platform.h" /* external refs */ .global _start .global __vectors_start__ .global __vectors_end__ .global handle_irq /* C irq handler */ .global __exc_undef .global __exc_swi .global __exc_pabt .global __exc_dabt .global __exc_fiq /* */ /* Main code stored in SDRAM */ /* */ .section ".text", "ax" __vectors_start__: b __reset_handler /* 0x00: reset exception vector */ b __undef_handler /* 0x04: undefined instruction exception vector */ b __swi_handler /* 0x08: SWI exception vector */ b __pabt_handler /* 0x0C: prefetch abort exception vector */ b __dabt_handler /* 0x10: data abord exception vector */ nop /* 0x14: Reserved */ b __irq_handler /* 0x18: IRQ exception vector */ b __fiq_handler /* 0x1C: FIQ exception vector:not used */ .balign 16 __reset_handler: ldr pc, ._start nop .balign 16 __undef_handler: /* undef mode: use banked r13 to increment counter */ ldr r13, __exc_undef add r13, r13, #1 str r13, __exc_undef /* return from handler */ movs pc, lr nop nop .balign 16 __swi_handler: /* we're in SVC, stack up r0 */ stmfd sp!, {r0} ldr r0, __exc_swi add r0, r0, #1 str r0, __exc_swi ldmfd sp!, {r0} /* return from handler */ movs pc, lr nop nop .balign 16 __pabt_handler: /* abort mode: use banked r13 to increment counter */ ldr r13, __exc_pabt add r13, r13, #1 str r13, __exc_pabt /* return from handler */ subs pc, lr, #4 nop nop .balign 16 __dabt_handler: /* abort mode: use banked r13 to increment counter */ ldr r13, __exc_dabt add r13, r13, #1 str r13, __exc_dabt /* return from handler: DO NOT RETURN TO WRONG INSTRUCTION */ subs pc, lr, #4 nop nop .balign 16 __irq_handler: /* push r0, lr on IRQ stack */ sub lr, lr, #4 stmfd sp!, { r12, lr } /* push lr & spsr */ add lr, lr, #4 mrs r12, spsr stmfd sp!, { r12, lr } /* turn to SVC, with IRQ disabled */ msr cpsr_c, #(MODE_SVC | PSR_I_BIT | PSR_F_BIT) /* push SVC regs */ stmfd sp!, { r0-r12, lr } ldr r12, .__handle_irq blx r12 /* pop SVC regs */ ldmfd sp!, { r0-r12, lr } /* back to IRQ mode, IRQ disabled */ msr cpsr_c, #(MODE_IRQ | PSR_I_BIT | PSR_F_BIT) ldmfd sp!, { r12, lr } msr spsr_cxsf, r12 /* pop r0, lr from IRQ stack and return from handler */ ldmfd sp!, { r12, pc }^ nop nop .balign 16 __fiq_handler: /* fiq mode: use banked r13 to increment counter */ ldr r13, __exc_fiq add r13, r13, #1 str r13, __exc_fiq /* return from handler */ subs pc, lr, #4 nop nop ._start: .word _start .__handle_irq: .word handle_irq __exc_undef: .word 0 __exc_swi: .word 0 __exc_pabt: .word 0 __exc_dabt: .word 0 __exc_fiq: .word 0 __vectors_end__: nop nop nop nop