/************************************************************/ /* Spidcom Technologies FILE NAME : cristina_mem_init.s DESCRIPTION : CRISTINA SDRAM initialization code HISTORY : -------------------------------------------------------------- DATE | AUTHOR | Version | Description -------------------------------------------------------------- 27/01/04 | Petillon | 1.0 | Creation */ /************************************************************/ /* SDRAM address is decomposed as ROW/BANK/COMLUMN */ /* MSB ROW (nb) BANK (2b) COLUMN (mb) DQM (2b) */ /* XXXXXXXXXXXX XX XXXXXXXXX XX */ /* MODE command to configure CAS and BURST in the */ /* SDRAM use ROW in the address */ /* The register value must be shifted by CL+2+2 */ #include "tina_g.h" #include "sdrams.h" #define FLOOR(X,Y) ((X)/(Y)) #define CEIL(X,Y) (((X)+(Y)-1)/(Y)) #define CLK_MHZ ((CLK_AHB)/1000000) .global __platform_memory_init /* */ /* Code executing in Flash */ /* */ .section ".flash", "ax" .align 0 __platform_memory_init: /* Initialization of the SDRAM controller */ /* Minimal SDRAM config. See [PL172] for details of configuration */ mov r0, #SDRAM_CFG_BASE mov r1, #0x00000001 /* Normal memory map */ str r1, [r0] /* Refresh period */ mov r2, #FLOOR(REFRP*CLK_MHZ,1000*16) str r2, [r0, #0x24] mov r1, #0x00000001 /* Command Delay Mode */ str r1, [r0, #0x28] /* tRP */ mov r1, #(CEIL(TRP*CLK_MHZ,1000)-1) str r1, [r0, #0x30] /* tRFC */ mov r3, #(CEIL(TRFC*CLK_MHZ,1000)-1) str r3, [r0, #0x4C] /* tRC */ mov r3, #(CEIL(TRC*CLK_MHZ,1000)-1) str r3, [r0, #0x48] /* tRAS */ mov r4, #(CEIL(TRAS*CLK_MHZ,1000)-1) str r4, [r0, #0x34] /* tXSR */ mov r5, #(CEIL(TXSR*CLK_MHZ,1000)-1) str r5, [r0, #0x38] /* tAPR */ mov r5, #(CEIL(TAPR*CLK_MHZ,1000)-1) str r5, [r0, #0x3C] /* tDAL */ mov r5, #(CEIL(TDAL*CLK_MHZ,1000)-1) str r5, [r0, #0x40] /* tWR */ mov r5, #(CEIL(TWR*CLK_MHZ,1000)-1) str r5, [r0, #0x44] /* tRRD */ mov r5, #(CEIL(TRRD*CLK_MHZ,1000)-1) str r5, [r0, #0x54] ldr r6, __dyn_cfg str r6, [r0, #0x100] /* Dyn config 0 */ str r6, [r0, #0x120] /* Dyn config 1 */ str r6, [r0, #0x140] /* Dyn config 2 */ str r6, [r0, #0x160] /* Dyn config 3 */ mov r7, #(CAS<<8) add r7, r7, #RAS str r7, [r0, #0x104] str r7, [r0, #0x124] str r7, [r0, #0x144] str r7, [r0, #0x164] /* Initialization of SDRAM's */ mov r4, #0x0083 /* r4 = MODE command */ add r5, r4, #0x0100 /* r5 = NOP command */ str r5, [r0, #0x20] /* Issue NOP command to SDRAM */ /* Delay between NOP and PALL */ nop nop nop nop mov r1,#0x1000 _dlyloop1: subs r1,r1,#1 bne _dlyloop1 sub r6, r5, #0x80 /* r6 = PALL (Precharge All) command */ str r6, [r0, #0x20] /* Issue PALL command to SDRAM */ /* Delay between PALL and MODE */ nop nop nop nop mov r1,#0x1000 _dlyloop2: subs r1,r1,#1 bne _dlyloop2 mov r1, #SDRAM_BASE /* For SDRAM CS MODE: */ ldr r2,__mode_reg_val add r1,r1,r2 mov r4, #0x0083 /* r4 = MODE command */ str r4, [r0, #0x20] /* Set SDRAM controler in MODE command */ mov r2, #0x04000000 /* r2 = r1 increment */ ldr r12, [r1], +r2 /* Issue SDRAM CS4 MODE (0x70044000) */ ldr r12, [r1], +r2 /* Issue SDRAM CS5 MODE (0x74044000) not used */ ldr r12, [r1], +r2 /* Issue SDRAM CS6 MODE (0x78044000) not used */ ldr r12, [r1] /* Issue SDRAM CS7 MODE (0x7C044000) not used */ mov r7, #0x00000003 /* r7 = NORMAL command */ str r7, [r0, #0x20] /* Set SDRAM controler in NORMAL mode */ ldr r3, __dyn_cfg orr r3,r3,#0x00080000 /* Turn buffer on */ str r3, [r0, #0x100] /* Dyn config 0 */ str r3, [r0, #0x120] /* Dyn config 1 not used */ str r3, [r0, #0x140] /* Dyn config 2 not used */ str r3, [r0, #0x160] /* Dyn config 3 not used */ /* Delay to wait for MPMC */ nop nop nop nop nop nop nop nop mov r12, #0 ldr r12, [r0, #0x04] /* Check MPMC status equal to 0 */ bx lr __dyn_cfg: .word DYN_CFG __mode_reg_val: .word MODE_REG_VAL