/************************************************************/ /* Spidcom Technologies FILE NAME : boot.S DESCRIPTION : CRISTINA Bootloader boot code HISTORY : -------------------------------------------------------------- DATE | AUTHOR | Version | Description -------------------------------------------------------------- 27/01/04 | Petillon | 1.0 | Creation */ /************************************************************/ #include "arm.h" #include "platform.h" #include "sdrams.h" #include "memory.h" /* external refs */ .global _start .global __data_end__ .global __sdram_lma__ .local rel0 .local rel1 .local __fast_copy /* */ /* Code executing in Flash */ /* */ .section ".flash", "ax" .align 0 __reset: b __platform_boot /* 0x00000000 : reset exception vector */ b __reset /* 0x00000004 : undefined instruction exception vector */ b __reset /* 0x00000008 : SWI exception vector */ b __reset /* 0x0000000C : prefetch abort exception vector */ b __reset /* 0x00000010 : data abord exception vector */ nop /* 0x00000014 : Reserved */ b __reset /* 0x00000018 : IRQ exception vector */ b __reset /* 0x0000001C : FIQ exception vector:not used */ /* Version can be retrieved from binary/flash at 0x00000020 */ __version: .string VERSION_STRING __tx_start: #ifdef CONFIG_ARCH_SPC200C .word 0xA3261820 #else .word 0x31061820 #endif #ifdef PLAB __do_reset_drivers: .word 0x0e7e0010 #endif .balign 16 __platform_boot: /* ensure all interrupts are disabled. */ mrs r0, cpsr orr r0, r0, #(PSR_I_BIT | PSR_F_BIT) /* Disable IRQ & FIQ */ msr cpsr_c, r0 /* Endian Initialization */ mrc p15, 0, r0, c1, c0, 0 #ifdef __BIG_ENDIAN orr r0, r0, #(1 << 7) /* Set big endian if required. */ #else bic r0, r0, #(1 << 7) /* Clear big endian if required. */ #endif mcr p15, 0, r0, c1, c0, 0 /* disable caches and MMU */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #(1 << 12) /* disable I-Cache */ bic r0, r0, #(1 << 2) /* disable D-Cache */ bic r0, r0, #(1 << 0) /* disable MMU */ mcr p15, 0, r0, c1, c0, 0 #ifdef PLAB ldr r0,__do_reset_drivers ldr r1,[r0] cmp r1,#0 #else movs r1,#1 #endif /* Reset the PLC Tx Start to avoid spurious frame transmission */ ldrne r0,__tx_start movne r1, #0 strne r1,[r0] /* tempo for SDRAM reset */ nop nop nop nop nop nop nop nop /* SDRAM initialization (platform dependant) */ bl __platform_memory_init /************************************************************************/ /* INSERT SDRAM TEST CODE HERE */ /* */ /* At this point, the SDRAM is configured an mapped at 0x70000000 */ /* */ /************************************************************************/ /* download main code in SDRAM */ /* first, copy "copy routine" to SDRAM to have performance */ ldr r12, .rel0 /* find fast copy address relative to PC */ ldr r11, .__fast_copy /* in case the code address has changed (versatile) */ sub r12, r11, r12 rel0: add r12, r12, pc sub r12, r12, #8 mov r11, #(SDRAM_BASE & 0xFF000000) /* copy to temporary region in the SDRAM */ add r11, r11, #(SDRAM_BASE & 0x00FF0000) add r11, r11, #SDRAM_TMP_OFFSET ldmia r12, {r0-r10} /* copy 10*4=40 bytes */ stmia r11, {r0-r10} /* NOTE: fast copy code must fit in 40 bytes */ /* perform copy */ ldr r12, .rel1 /* find text address relative to PC */ ldr r13, .__sdram_lma__ /* in case the code address has changed (versatile) */ sub r12, r13, r12 rel1: add r12, r12, pc sub r12, r12, #8 ldr r13, .__text_start__ /* dest addr: start of text section */ ldr r14, .__data_end__ /* end: end of data section */ mov pc, r11 /* jump to fast copy (in SDRAM) */ nop nop nop nop nop nop /* fast copy routine (including start address) must fit in 40 bytes (see NOTE) */ __fast_copy : 1: ldmia r12!, {r0-r11} stmia r13!, {r0-r11} cmp r13, r14 blo 1b /* now the code is copied, jump to it! */ ldr pc, ._start nop nop nop ._start: .word _start /* end of fast copy routine (including start address) */ .rel0: .word rel0 .__fast_copy: .word __fast_copy .rel1: .word rel1 .__sdram_lma__: .word __sdram_lma__ .__text_start__: .word __text_start__ .__data_end__: .word __data_end__