/************************************************************/ /*! \file arm.c \brief Processor state management routines. Provides routines to manage processor state (IRQ, cache, MMU). Usable only in supervisor mode. \author Philippe Petillon (philippe.petillon@spidcom.com) \author (c) Spidcom Technologies \version 1.0 \date 04/02/04 */ /************************************************************/ #include #include "arm.h" void enable_irq() { register uint32_t r; asm("mrs %0, cpsr":"=r"(r)); asm("bic %0, %1, %2":"=r"(r):"r"(r),"i"PSR_I_BIT); asm("msr cpsr_c, %0 "::"r"(r)); } void disable_irq() { register uint32_t r; asm("mrs %0, cpsr":"=r"(r)); asm("orr %0, %1, %2":"=r"(r):"r"(r),"i"PSR_I_BIT); asm("msr cpsr_c, %0 "::"r"(r)); } void enable_icache() { register uint32_t r; asm("mrc p15, 0, %0, c1, c0, 0":"=r"(r)); asm("orr %0, %1, #(1 << 12)":"=r"(r):"r"(r)); asm("mcr p15, 0, %0, c1, c0, 0"::"r"(r)); } void disable_icache() { register uint32_t r; asm("mrc p15, 0, %0, c1, c0, 0":"=r"(r)); asm("bic %0, %1, #(1 << 12)":"=r"(r):"r"(r)); asm("mcr p15, 0, %0, c1, c0, 0"::"r"(r)); } void invalidate_icache() { register uint32_t r; asm("mov %0, #0":"=r"(r)); asm("mcr p15, 0, %0, c7, c5, 0"::"r"(r)); } void enable_dcache() { register uint32_t r; asm("mrc p15, 0, %0, c1, c0, 0":"=r"(r)); asm("orr %0, %1, #(1 << 2)":"=r"(r):"r"(r)); asm("mcr p15, 0, %0, c1, c0, 0"::"r"(r)); } void disable_dcache() { register uint32_t r; asm("mrc p15, 0, %0, c1, c0, 0":"=r"(r)); asm("bic %0, %1, #(1 << 2)":"=r"(r):"r"(r)); asm("mcr p15, 0, %0, c1, c0, 0"::"r"(r)); } void invalidate_dcache() { register uint32_t r; asm("mov %0, #0":"=r"(r)); asm("mcr p15, 0, %0, c7, c6, 0"::"r"(r)); } void enable_mmu() { register uint32_t r; asm("mrc p15, 0, %0, c1, c0, 0":"=r"(r)); asm("orr %0, %1, #(1 << 0)":"=r"(r):"r"(r)); asm("mcr p15, 0, %0, c1, c0, 0"::"r"(r)); } void disable_mmu() { register uint32_t r; asm("mrc p15, 0, %0, c1, c0, 0":"=r"(r)); asm("bic %0, %1, #(1 << 0)":"=r"(r):"r"(r)); asm("mcr p15, 0, %0, c1, c0, 0"::"r"(r)); }