/* * include/asm/arch/nvram.h * * Copyright (C) 2012 MStar Semiconductor. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software Foundation, * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA */ #ifndef __ASM_ARCH_NVRAM_H #define __ASM_ARCH_NVRAM_H /* NVRAM integrity word */ #define SPC300_NVRAM_MAGIC "NVRAM\0\0\0" #define SPC200_NVRAM_MAGIC1 0x0000FEED #define SPC200_NVRAM_MAGIC2 0xDEADBEEF #define SPC200_NVRAM2_MAGIC "NVRAM2\0\0" #define NVRAM_IS_VALID(nvram) (!memcmp((nvram)->magic, SPC300_NVRAM_MAGIC, 8)) #define NVRAM_MTD_NAME "nvram" #ifndef __ASSEMBLY__ enum spc300_gpio_direction_t { SPC300_GPIO_DIRECTION_NONE = 0, SPC300_GPIO_DIRECTION_INPUT = 1, SPC300_GPIO_DIRECTION_OUTPUT = 2, SPC300_GPIO_DIRECTION_BIDIR = 3, }; /* * MSE500 NVRAM is the concatenation of SPC300 and SPC200C NVRAMs. We chose * this solution to avoid any modification in polux or cleopatre software and * limit them to genNVRAM. As a consequence some informations are * duplicated, but, as we have way more flash memory dedicated to NVRAM than * needed, it is acceptable. */ /* /!\ All values are LITTLE-ENDIAN */ typedef struct { /* SPC300 fields. */ #define SPC300_NVRAM_FIRST_FIELD_OFFSET ((uint32_t)(((spidcom_nvram_t *)(0))->magic)) char magic[8]; /* Magic number "NVRAM\0\0\0" */ uint32_t pkg_cfg; /* Package configuration register */ union { struct { uint32_t gpio_0_7_cfg; /* GPIO 0 to 7 configuration register */ uint32_t gpio_8_15_cfg; /* GPIO 8 to 15 configuration register */ } spcpio; struct { uint16_t config_offset; /* Offset of IOMUX config in nvram in bytes */ uint16_t config_size; /* Size of IOMUX config in bytes */ uint32_t reserved; } iomux; } io; uint32_t gpio_allow_dir; /* GPIO allowed directions 0:none 1:in 2:out 3:bi */ union { struct { uint32_t config; /* SDRAM configuration register */ uint32_t timing0; /* SDRAM timing register 0 */ uint32_t timing1; /* SDRAM timing register 1 */ uint32_t refresh; /* SDRAM refresh register */ } sdram; struct { uint16_t config_offset; /* Offset of MIU config in nvram in bytes */ uint16_t config_size; /* Size of MIU config in bytes */ uint32_t ram_size; /* Size of MIU connected RAM in bytes */ uint32_t reserved[2]; } miu; } dram; uint32_t flash_org; /* Flash organization */ uint32_t img_0_offset; /* Offset of first image address */ uint32_t nb_images; /* Max Number of Images present in flash */ char product_name[64]; /* Product short name in string format */ char product_partnb[64]; /* Product part number in string format */ char product_desc[128]; /* Product long description in string format */ char serial_number[64]; /* Product serial number in string format */ uint32_t eth1_phy_addr; /* Address of Ethernet PHY for ETH 1*/ unsigned char eth1_address[6]; /* Ethernet MAC address for ETH 1 */ unsigned char eth1_port_nb; /* Ethernet port number for ETH 1 */ unsigned char reserved1; unsigned char plc_address[6]; /* PowerLine MAC address */ unsigned char reserved2[2]; char device_password[32]; /* HomePlugAV device unique password (DPW) */ char oem_info[64]; /* Additional information for OEM */ unsigned char tonemask[192]; /* HomePlugAV tonemask */ char manufactory_info[64]; /* Name of the product manufacturer */ uint32_t img_max_size; /* Max size of an image in flash */ uint32_t cpu_partnb; /* SPC3x0 partnb */ uint32_t dynamic[256]; /* Dynamic data (see miu_config) */ #define SPC300_NVRAM_LAST_FIELD_OFFSET ((uint32_t)(((spidcom_nvram_t *)(0))->dynamic) + 256 * sizeof (uint32_t)) #ifdef CONFIG_CHIP_FEATURE_EXTRA_NVRAM_FIELDS /* SPC200 fields. */ #define SPC200_NVRAM_FIRST_FIELD_OFFSET ((uint32_t)&(((spidcom_nvram_t *)(0))->magicWord1)) uint32_t magicWord1; uint32_t magicWord2; uint32_t boardNumber; /* board Number */ char serialNumber[64]; /* serial number as tagged on the board */ char sysDescr[256]; /* system description */ char ethPhysAddress[6]; /* MAC Address */ char plcPhysAddress[6]; /* MAC Address */ char reserved[8]; char magicNvram2[8]; /* 0x4e565241 0x4d320000 "NVRAM2" */ char boardDesc[16]; /* board description string */ uint32_t boardId; /* board identification number */ char vendorInfo[64]; /* vendor additional info (OEM) */ uint32_t sdramSize; /* size of SDRAM in MBytes */ unsigned char *imageOffset0; /* address of image #0 in flash */ unsigned char *imageOffset1; /* address of image #1 in flash */ uint32_t afeType; /* Type of AFE design */ uint32_t ethPortNum; /* Number of the eth port */ char manufactoryInfo[64]; /* manufactory info string */ #define SPC200_NVRAM_LAST_FIELD_OFFSET ((uint32_t)(((spidcom_nvram_t *)(0))->manufactoryInfo) + 64 * sizeof (char)) /* MSE500 specific fields. */ uint32_t eth2_phy_addr; /* Address of Ethernet PHY for ETH 2*/ unsigned char eth2_address[6]; /* Ethernet MAC address for ETH 2 */ unsigned char eth2_port_nb; /* Ethernet port number for ETH 2 */ unsigned char reserved3; #endif /* CONFIG_CHIP_FEATURE_EXTRA_NVRAM_FIELDS */ } spidcom_nvram_t; //Currently __attribute__((packed)) not needed /* genNVRAM needs to know the sizes of the "sub-NVRAMs". But, as we only have * one structure now, we can not use a sizeof anymore. */ #define SPC300_NVRAM_SIZE (SPC300_NVRAM_LAST_FIELD_OFFSET - SPC300_NVRAM_FIRST_FIELD_OFFSET) #define SPC200_NVRAM_SIZE (SPC200_NVRAM_LAST_FIELD_OFFSET - SPC200_NVRAM_FIRST_FIELD_OFFSET) #ifdef __KERNEL__ extern spidcom_nvram_t spidcom_nvram; static inline void spidcom_nvram_copy(void* dst, void* src, unsigned int length) { unsigned int burst, rest, i; unsigned long *src32, *dst32; unsigned char *src8, *dst8; src32 = (unsigned long*)src; dst32 = (unsigned long*)dst; burst = length / 4; rest = length % 4; for(i=0 ; i> NVRAM_##name##_SHIFT) & (NVRAM_##name##_MASK)) #define NVRAM_BFINS(name,value,old) \ ( ((old) & ~((NVRAM_##name##_MASK) << NVRAM_##name##_SHIFT)) \ | NVRAM_BF(name,value)) #define MAX_INTERNAL_GPIOS 16 #define MIN_INTERNAL_GPIOS 8 #ifdef CONFIG_CHIP_FEATURE_SPCPIO #define spc300_gpio_max_nb(pkg_cfg) ((NVRAM_BFEXT(PIO, pkg_cfg) < 5) ? \ MAX_INTERNAL_GPIOS : MIN_INTERNAL_GPIOS) #else #define spc300_gpio_max_nb(pkg_cfg) MAX_INTERNAL_GPIOS #endif #define spc300_gpio_direction(gpio_allow_dir,num) \ ((gpio_allow_dir >> (num * NVRAM_GPIO_DIR_NB_BITS)) \ & NVRAM_GPIO_DIR_MASK) #define spc300_gpio_cfg(gpio_cfg,num) \ ((gpio_cfg >> (num * NVRAM_GPIO_CFG_NB_BITS)) \ & NVRAM_GPIO_CFG_MASK) #endif /* __ASSEMBLY__ */ /* * MIU and IOMUX registers are loaded by uboot, using the informations in NVRAM. * NVRAM stores two 32 bits words for each triplet offset/value/mask used to * configure MIU and IOMUX (one 32 bits word for offset and two 16 bits words * for value/mask). * There are special offsets that are interpreted by uboot as commands, * see the defines below. In this case, value and mask are interpreted as * code op operands. * If someone wants to create new code op, be aware that they must be superior * to 0x20000. */ /* Timed wait command. * Operand1 is the time to wait in us (max 65535 us) for a CPU running * at 492 MHz (max speed used). If CPU speed is lower, actual wait will be * longer. * Operand2 is not used. */ #define NVRAM_WAIT_CODE_OP 0x00020000 /* MIU wait init done command. * No operand. */ #define NVRAM_MIU_WAIT_INIT_DONE_CODE_OP 0x00020001 #endif /* __ASM_ARCH_NVRAM_H */