/* * include/asm/arch/irqs.h * * Copyright (C) 2012 MStar Semiconductor. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software Foundation, * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA */ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H #include #include #if defined (CONFIG_CHIP_FEATURE_INT_MAP_V1) #define INT_TIMER_1 0 #define INT_TIMER_2 1 #define INT_GPIO 2 #define INT_UART_1 3 #define INT_UART_2 4 #define INT_SPI 5 #define INT_GPDMA 6 #define INT_I2S_tx_empt 7 #define INT_I2S_tx_or 8 #define INT_MPEG_TS 9 #define INT_MBX 10 #define INT_MBX_ACK 11 #define INT_MBX_WKP 12 #define INT_MBX_WD 13 #define INT_PCM 14 #define INT_ETH 16 #define INT_ETH_PHY 17 #define INT_WDT 31 #define INTMASK_TIMER_1 (1 << INT_TIMER_1) #define INTMASK_TIMER_2 (1 << INT_TIMER_2) #define INTMASK_GPIO (1 << INT_GPIO) #define INTMASK_UART_1 (1 << INT_UART_1) #define INTMASK_UART_2 (1 << INT_UART_2) #define INTMASK_SPI (1 << INT_SPI) #define INTMASK_GPDMA (1 << INT_GPDMA) #define INTMASK_I2S_tx_empt (1 << INT_I2S_tx_empt) #define INTMASK_I2S_tx_or (1 << INT_I2S_tx_or) #define INTMASK_MPEG_TS (1 << INT_MPEG_TS) #define INTMASK_MBX (1 << INT_MBX) #define INTMASK_MBX_ACK (1 << INT_MBX_ACK) #define INTMASK_MBX_WKP (1 << INT_MBX_WKP) #define INTMASK_MBX_WD (1 << INT_MBX_WD) #define INTMASK_PCM (1 << INT_PCM) #define INTMASK_ETH (1 << INT_ETH) #define INTMASK_ETH_PHY (1 << INT_ETH_PHY) #define INTMASK_WDT (1 << INT_WDT) #elif defined (CONFIG_CHIP_FEATURE_INT_MAP_V2) #define INT_TIMER_1 0 #define INT_TIMER_2 1 #define INT_GPIO 2 #define INT_UART_1 3 #define INT_UART_2 4 #define INT_SPI 5 #define INT_GPDMA 6 #define INT_MBX 7 #define INT_MBX_ACK 8 #define INT_MBX_WKP 9 #define INT_MBX_WD 10 #define INT_EMMC 11 #define INT_L2ND2A 12 #define INT_ETH 13 #define INT_ETH_PHY 14 #define INT_SPC200_PLC_PHLIC_0 15 #define INT_SPC200_PLC_PHLIC_1 16 #define INT_SPC200_PLC_PHLIC_2 17 #define INT_SPC200_PLC_PHLIC_3 18 #define INT_SPC200_PLC_PHLIC_4 19 #define INT_SPC200_PLC_PHLIC_5 20 #define INT_SPC200_PLC_PHLIC_6 21 #define INT_SPC200_PLC_PHLIC_7 22 #define INT_SPC200_PLC_PHLIC_8 23 #define INT_SPC200_PLC_PHLIC_9 24 #define INT_SPC200_PLC_PHLIC_10 25 #define INT_SPC200_PLC_PHLIC_11 26 #define INT_SPC200_PLC_PHLIC_12 27 #define INT_SPC200_PLC_PHLIC_13 28 #define INT_SPC200_PLC_RX 29 #define INT_SPC200_PLC_ERR 30 #define INT_WDT 31 #define INT_TIMER_3 32 #define INT_TIMER_4 33 #define INT_ETH2 34 #define INTMASK_TIMER_1 (1 << INT_TIMER_1) #define INTMASK_TIMER_2 (1 << INT_TIMER_2) #define INTMASK_GPIO (1 << INT_GPIO) #define INTMASK_UART_1 (1 << INT_UART_1) #define INTMASK_UART_2 (1 << INT_UART_2) #define INTMASK_SPI (1 << INT_SPI) #define INTMASK_GPDMA (1 << INT_GPDMA) #define INTMASK_MBX (1 << INT_MBX) #define INTMASK_MBX_ACK (1 << INT_MBX_ACK) #define INTMASK_MBX_WKP (1 << INT_MBX_WKP) #define INTMASK_MBX_WD (1 << INT_MBX_WD) #define INTMASK_EMMC (1 << INT_EMMC) #define INTMASK_L2ND2A (1 << INT_L2ND2A) #define INTMASK_ETH (1 << INT_ETH) #define INTMASK_ETH_PHY (1 << INT_ETH_PHY) #define INTMASK_SPC200_PLC_PHLIC_0 (1 << INT_SPC200_PLC_PHLIC_0) #define INTMASK_SPC200_PLC_PHLIC_1 (1 << INT_SPC200_PLC_PHLIC_1) #define INTMASK_SPC200_PLC_PHLIC_2 (1 << INT_SPC200_PLC_PHLIC_2) #define INTMASK_SPC200_PLC_PHLIC_3 (1 << INT_SPC200_PLC_PHLIC_3) #define INTMASK_SPC200_PLC_PHLIC_4 (1 << INT_SPC200_PLC_PHLIC_4) #define INTMASK_SPC200_PLC_PHLIC_5 (1 << INT_SPC200_PLC_PHLIC_5) #define INTMASK_SPC200_PLC_PHLIC_6 (1 << INT_SPC200_PLC_PHLIC_6) #define INTMASK_SPC200_PLC_PHLIC_7 (1 << INT_SPC200_PLC_PHLIC_7) #define INTMASK_SPC200_PLC_PHLIC_8 (1 << INT_SPC200_PLC_PHLIC_8) #define INTMASK_SPC200_PLC_PHLIC_9 (1 << INT_SPC200_PLC_PHLIC_9) #define INTMASK_SPC200_PLC_PHLIC_10 (1 << INT_SPC200_PLC_PHLIC_10) #define INTMASK_SPC200_PLC_PHLIC_11 (1 << INT_SPC200_PLC_PHLIC_11) #define INTMASK_SPC200_PLC_PHLIC_12 (1 << INT_SPC200_PLC_PHLIC_12) #define INTMASK_SPC200_PLC_PHLIC_13 (1 << INT_SPC200_PLC_PHLIC_13) #define INTMASK_SPC200_PLC_RX (1 << INT_SPC200_PLC_RX) #define INTMASK_SPC200_PLC_ERR (1 << INT_SPC200_PLC_ERR) #define INTMASK_WDT (1 << INT_WDT) #else # error "no irqs definition" #endif #define NR_IRQS GIC_LINES_NB #ifndef NO_IRQ #define NO_IRQ ((unsigned int)(-1)) #endif /* NO_IRQ */ #endif /* __ASM_ARCH_IRQS_H */