/* * cpu/spc300/start.S * * Copyright (C) 2009 SPiDCOM Technologies * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * * Author(s): * Drasko DRASKOVIC * */ #include #include #include #include #define ETH_PHY_RESET_WAIT_TIME 600000 /* (((12000 * 147500000) / 1000000) / 3) */ /* ************************************************************************* * * Jump vector table as in table 3.1 in [1] * ************************************************************************* */ .globl _start _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq .balignl 16,0xdeadbeef /* ************************************************************************* * * Startup Code (reset vector) * * do important init only if we don't start from memory! * setup Memory and board specific bits prior to relocation. * relocate armboot to ram * setup stack * ************************************************************************* */ _TEXT_BASE: .word TEXT_BASE .globl _armboot_start _armboot_start: .word _start /* * These are defined in the board-specific linker script. */ .globl _bss_start _bss_start: .word __bss_start .globl _bss_end _bss_end: .word _end #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START IRQ_STACK_START: .word 0x0badc0de /* IRQ stack memory (calculated at run-time) */ .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de #endif /* * the actual reset code */ reset: /* * set the cpu to SVC32 mode */ mrs r0,cpsr bic r0,r0,#0x1f orr r0,r0,#0xd3 msr cpsr,r0 /* * Power-on reset */ /* flush v4 I/D caches */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ /* disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 #ifdef CONFIG_EXEC_FROM_SDRAM /* * We give the possibility to load U-Boot anywhere into the * SDRAM and to execute it without flash. * This allow a first time flashing operation when flash is blank. * To boot from SDRAM, change r10 value to something different from 0 : * r10 = 0 : boot from Flash * r10 != 0 : boot from SDRAM */ mov r10,#0 nop nop nop /* * we can either stop here (after these nops) * with debugger, and change r10 contents to 1, * or sometimes we can do it with JTAG * where we change r10 contents directly * in code (in bin). * That's why check now contents of r10 */ cmp r10,#0 /* * If we are executing from SDRAM (r10 == 1), * so do not call cpu_init_crit, * just jump over fnc call */ bne skip_init_crit bl cpu_init_crit bl first_init_end skip_init_crit: /* As we don't call cpu_init_crit we need to find NVRAM address */ mov ip, lr /* perserve link reg across call */ bl detect_nvram /* r10 will hold the NVRAM address */ mov lr, ip /* restore link */ first_init_end: #else /* * we do sys-critical inits only at reboot, * not when booting from ram! */ #ifdef CONFIG_SKIP_LOWLEVEL_INIT /* As we don't call cpu_init_crit we need to find NVRAM address */ mov ip, lr /* perserve link reg across call */ bl detect_nvram /* r10 will hold the NVRAM address */ mov lr, ip /* restore link */ #else bl cpu_init_crit /* after cpu_init_crit, r10 will hold NVRAM addr, so do not clobber this reg */ #endif #endif #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ beq stack_setup ldr r2, _armboot_start ldr r3, _bss_start sub r2, r3, r2 /* r2 <- size of armboot */ add r2, r0, r2 /* r2 <- source end address */ copy_loop: ldmia r0!, {r3-r9, r11} /* copy from source address [r0] (preserve r10 which holds the address of NVRAM) */ stmia r1!, {r3-r9, r11} /* copy to target address [r1] (preserve r10 which holds the address of NVRAM) */ cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ clbss_l: str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l /* * REMAP (SPI : 0x00000000->0x30000000; SDRAM ALIAS on 0x00000000) */ /* * first jump in SDRAM, but in exact place * to just continue with remap code in SDRAM * (at label in_sdram). * For this, we need to calculate the offsets. */ adr r0, in_sdram adr r1, _start sub r0, r0, r1 /* offset of in_sdram from the _start (in SPI Flash) */ ldr r1, _TEXT_BASE /* now take address at which code starts in SDRAM */ add r1, r1, r0 /* and add this offset to it, to find where in_sdram label is located in SDRAM */ mov pc, r1 /* go to this address in SDRAM (in_sdram label) */ in_sdram: ldr r0, =REGBANK_BASE ldr r1, =0x00000001 str r1, [r0, #RB_BUS_SYS_REMAPPED] /* * Check if a correct NVRAM was found * NVRAM address was under r10 */ bl check_nvram /* we pass NVRAM addr in r10 and wait result under r0 */ cmp r0, #0 bne bl_no_nvram /* * Configure timer prescaler */ bl timer_clock_config /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ /* * Configure GPIOs and PIO * WARNING: NVRAM need to be found and put to r10 */ bl gpio_pio_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ /* * Configure Ethernet IP */ mov ip, lr /* perserve link reg across call */ bl ethernet_config /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ mov lr, ip /* restore link */ /* * Release the resets */ /* ETH reset */ ldr r0, =REGBANK_BASE ldr r1, [r0, #RB_RST_GROUP] bic r1, r1, #RST_INTF /* clear bit 1 of RB_RST_GROUP, sw_rst_intf -> 0 */ str r1, [r0, #RB_RST_GROUP] /* * Force Reset out for PHY Ethernet during 10ms */ ldr r0, =REGBANK_BASE ldr r1, [r0, #RB_RST_MODULE] bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */ str r1, [r0, #RB_RST_MODULE] ldr r0, =REGBANK_BASE ldr r1, [r0, #RB_RST_MODULE] orr r1, r1, #RST_EXT /* set bit 12 of RB_RST_MODULE, sw_rst_ext -> 1 */ str r1, [r0, #RB_RST_MODULE] ldr r0, =ETH_PHY_RESET_WAIT_TIME .Lwaitrst: sub r0, r0, #1 cmp r0, #0 bne .Lwaitrst bl_no_nvram: /* EXT reset */ ldr r0, =REGBANK_BASE ldr r1, [r0, #RB_RST_MODULE] bic r1, r1, #RST_ETH /* clear bit 8 of RB_RST_MODULE, sw_rst_eth -> 0 */ bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */ str r1, [r0, #RB_RST_MODULE] /* * call the set-up function in lib_arm/board.c * we will never return from this function normally */ ldr pc, _start_armboot _start_armboot: .word start_armboot /* ************************************************************************* * * CPU_init_critical registers * * setup important registers * setup memory timing * ************************************************************************* */ cpu_init_crit: /* * Speed up SPI and ARM */ ldr r0, =SPI_FREQ ldr r1, =0x00000003 /* divide CLK_AHB (after PLL) by 8 (<20MHz @147MHz)*/ str r1, [r0] ldr r0, =REGBANK_BASE ldr r1, =CLK_DIV_ARM_2 str r1, [r0, #RB_CLK_DIV_ARM] /* 0 -> RB_CLK_DIV_ARM CLK_ARM = CLK_AHB * 2*/ ldr r0, =REGBANK_BASE poll_RB_CLK_DIV_STAT_ARM: ldr r1, [r0, #RB_CLK_DIV_STAT_ARM] cmp r1, #CLK_DIV_ARM_2 bne poll_RB_CLK_DIV_STAT_ARM /* * Detect NVRAM address */ mov ip, lr /* perserve link reg across call */ bl detect_nvram /* r10 will hold the NVRAM address */ mov lr, ip /* restore link */ /* * SDRAM and board specific bits setup prior to relocation. */ mov ip, lr /* perserve link reg across call */ bl sdram_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ mov lr, ip /* restore link */ /* * Synchronise DSP */ mov ip, lr /* perserve link reg across call */ bl dsp_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ mov lr, ip /* restore link */ /* * Do PLL initialization (depending on nvram parameters Xclk and Freq) */ mov ip, lr /* perserve link reg across call */ bl pll_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ mov lr, ip /* restore link */ /* * All vital periphs configured, exit cpu_init_crit */ mov pc, lr /* back to my caller */ /* ************************************************************************* * * GPIO and PIO Initialization * ************************************************************************* */ gpio_pio_init: /* * GPIO init */ ldr r0, =REGBANK_BASE add r0, r0, #RB_GPIO_0_CONFIG-4 mov r2, #0 /* GPIO 0-7*/ ldr r1, [r10, #NVRAM_GPIO_0_7_CFG_OFFSET] /* r1 = gpio_0_7_cfg; loaded from NVRAM */ .Lgpio07: lsr r3, r1, r2 /* r3 = r1 >> r2 */ and r3, r3, #NVRAM_GPIO_MASK /* r3 = gpio_x */ str r3, [r0, #4]! /* r4 -> r0 + 4 and after r0 += 4 */ add r2, r2, #NVRAM_GPIO_SHIFT /* r2 += 4 */ cmp r2, #(NVRAM_GPIO_7_SHIFT+NVRAM_GPIO_SHIFT) /* check if we wrote all 8 gpio fields */ blt .Lgpio07 /* GPIO 8-15*/ ldr r1, [r10, #NVRAM_GPIO_8_15_CFG_OFFSET] /* r1 = gpio_8_15_cfg; loaded from NVRAM */ mov r2, #0 .Lgpio815: lsr r3, r1, r2 /* r3 = r1 >> r2 */ and r3, r3, #NVRAM_GPIO_MASK /* r3 = gpio_x */ str r3, [r0, #4]! /* r3 -> r0 + 4 and after r0 += 4 */ add r2, r2, #NVRAM_GPIO_SHIFT /* r2 += 4 */ cmp r2, #(NVRAM_GPIO_7_SHIFT+NVRAM_GPIO_SHIFT) /* check if we wrote all 8 gpio fields */ blt .Lgpio815 /* * PIO init */ ldr r0, =REGBANK_BASE ldr r1, [r10, #NVRAM_PKG_CFG_OFFSET] /* r1 = pkg_cfg; loaded from NVRAM */ lsr r1, r1, #NVRAM_PIO_SHIFT and r1, #NVRAM_PIO_MASK /* r1 = pio */ str r1, [r0, #RB_PIO_CONFIG] ldr r1, =0x01 str r1, [r0, #RB_PIO_ENABLE] mov pc, lr /* back to my caller */ /* ************************************************************************* * * TIMER PRESCALER Configuration * ************************************************************************* */ timer_clock_config: /* Find Xclk val from NVRAM (struct address is in r10) */ mov r2, #5 /* default timer_clk think that xclk=37,5 */ ldr r1, [r10, #NVRAM_PKG_CFG_OFFSET] /* load pkg_cfg */ lsr r1, r1, #NVRAM_XCLK_SHIFT and r1, r1, #NVRAM_XCLK_MASK /* r1 = xclk */ cmp r1, #NVRAM_XCLK_1875 /* xclk = 18,75MHz ? */ moveq r2, #2 /* yes: timer_clk = xclk/(2*(2+1)) = 3.125MHz */ cmp r1, #NVRAM_XCLK_25 /* xclk = 25MHz ? */ moveq r2, #3 /* yes: timer_clk = xclk/(2*(3+1)) = 3.125MHz */ cmp r1, #NVRAM_XCLK_375 /* xclk = 37,5MHz ? */ moveq r2, #5 /* yes: timer_clk = xclk/(2*(5+1)) = 3.125MHz */ /* store prescaler */ ldr r0, =REGBANK_BASE str r2, [r0, #RB_CLK_DIV_T1] mov pc, lr /* back to my caller */ /* ************************************************************************* * * Interrupt handling * ************************************************************************* */ @ @ IRQ stack frame. @ #define S_FRAME_SIZE 72 #define S_OLD_R0 68 #define S_PSR 64 #define S_PC 60 #define S_LR 56 #define S_SP 52 #define S_IP 48 #define S_FP 44 #define S_R10 40 #define S_R9 36 #define S_R8 32 #define S_R7 28 #define S_R6 24 #define S_R5 20 #define S_R4 16 #define S_R3 12 #define S_R2 8 #define S_R1 4 #define S_R0 0 #define MODE_SVC 0x13 #define I_BIT 0x80 /* * use bad_save_user_regs for abort/prefetch/undef/swi ... * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling */ .macro bad_save_user_regs @ carve out a frame on current user stack sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack add r5, sp, #S_SP mov r1, lr stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr mov r0, sp @ save current stack into r0 (param register) .endm .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. add r8, sp, #S_PC stmdb r8, {sp, lr}^ @ Calling SP, LR str lr, [r8, #0] @ Save calling PC mrs r6, spsr str r6, [r8, #4] @ Save CPSR str r0, [r8, #8] @ Save OLD_R0 mov r0, sp .endm .macro irq_restore_user_regs ldmia sp, {r0 - lr}^ @ Calling r0 - lr mov r0, r0 ldr lr, [sp, #S_PC] @ Get PC add sp, sp, #S_FRAME_SIZE subs pc, lr, #4 @ return & move spsr_svc into cpsr .endm .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr str lr, [r13, #4] @ save spsr in position 1 of saved stack mov r13, #MODE_SVC @ prepare SVC-Mode @ msr spsr_c, r13 msr spsr, r13 @ switch modes, make sure moves will execute mov lr, pc @ capture return pc movs pc, lr @ jump to next instruction & switch modes. .endm .macro get_irq_stack @ setup IRQ stack ldr sp, IRQ_STACK_START .endm .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm /* * exception handlers */ .align 5 undefined_instruction: get_bad_stack bad_save_user_regs bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs bl do_not_used #ifdef CONFIG_USE_IRQ .align 5 irq: get_irq_stack irq_save_user_regs bl do_irq irq_restore_user_regs .align 5 fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs bl do_fiq irq_restore_user_regs #else .align 5 irq: get_bad_stack bad_save_user_regs bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs bl do_fiq #endif