/* * cpu/spc300/eth_init.S * * Copyright (C) 2009 SPiDCOM Technologies * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include #include .file "eth_init.S" .text .arm @ This is ARM code; performs the same action as .code 32 .align 2 @ Align to word boundary; "2" means the number of bits that must be zero .globl ethernet_config .type ethernet_config, %function /* WARNING : Assusme that for macros r0=REGBANK_BASE and r1 is not used */ .macro cmdoff, offset ldr r1, =CLK_CMD_OFF str r1, [r0, #\offset] .endm .macro cmdon, offset ldr r1, =CLK_CMD_ON str r1, [r0, #\offset] .endm .macro setreg, offset, val ldr r1, =\val str r1, [r0, #\offset] .endm .macro checkreg, offset, val 1: ldr r1, [r0, #\offset] cmp r1, #\val bne 1b .endm ethernet_config: ldr r0, =REGBANK_BASE /* * Switch off all Ethernet clock commands */ cmdoff RB_CLK_CMD_ETH_TX_125 checkreg RB_CLK_CMD_ETH_TX_125, CLK_IS_OFF cmdoff RB_CLK_CMD_ETH_TX_EXT checkreg RB_CLK_CMD_ETH_TX_EXT, CLK_IS_OFF cmdoff RB_CLK_CMD_ETH_RX_EXT checkreg RB_CLK_CMD_ETH_RX_EXT, CLK_IS_OFF cmdoff RB_CLK_CMD_ETH_RMII checkreg RB_CLK_CMD_ETH_RMII, CLK_IS_OFF /* * Find Ethernet Mode from NVRAM * we assume that r10 = NVRAM Base Address * default mode is GMII */ ldr r3, [r10, #8] /* find pkg_cfg */ lsr r3, r3, #8 and r3, r3, #3 /* r3 = eth_mode */ cmp r3, #0 beq 10f /* eth_mode = MII */ cmp r3, #1 beq 20f /* eth_mode = RMII */ /* * GMII mode */ /* Enable TX 125MHz clock */ setreg RB_CLK_SEL_ETH_MAC, CLK_SEL_ETH_MAC_125 checkreg RB_CLK_SEL_STAT_ETH_MAC, CLK_SEL_ETH_MAC_125 setreg RB_CLK_SEL_ETH_TX, CLK_SEL_ETH_TX_125 checkreg RB_CLK_SEL_STAT_ETH_TX, CLK_SEL_ETH_TX_125 cmdon RB_CLK_CMD_ETH_TX_125 checkreg RB_CLK_STAT_ETH_TX_125, CLK_IS_ON /* Enable RX ext clock */ setreg RB_CLK_SEL_ETH_RX, CLK_SEL_ETH_RX_EXT checkreg RB_CLK_SEL_STAT_ETH_RX, CLK_SEL_ETH_RX_EXT cmdon RB_CLK_CMD_ETH_RX_EXT checkreg RB_CLK_STAT_ETH_RX_EXT, CLK_IS_ON bal 100f /* * MII mode */ 10: /* Enable TX_ext clock */ setreg RB_CLK_SEL_ETH_TX, CLK_SEL_ETH_TX_EXT checkreg RB_CLK_SEL_STAT_ETH_TX, CLK_SEL_ETH_TX_EXT cmdon RB_CLK_CMD_ETH_TX_EXT checkreg RB_CLK_STAT_ETH_TX_EXT, CLK_IS_ON /* Enable RX_ext clock */ setreg RB_CLK_SEL_ETH_RX, CLK_SEL_ETH_RX_EXT checkreg RB_CLK_SEL_STAT_ETH_RX, CLK_SEL_ETH_RX_EXT cmdon RB_CLK_CMD_ETH_RX_EXT checkreg RB_CLK_STAT_ETH_RX_EXT, CLK_IS_ON bal 100f /* * RMII mode */ 20: /* Enable TX 50MHz clock */ setreg RB_CLK_SEL_ETH_TX, CLK_SEL_ETH_TX_25 checkreg RB_CLK_SEL_STAT_ETH_TX, CLK_SEL_ETH_TX_25 /* Enable RX 50MHz clock */ setreg RB_CLK_SEL_ETH_RX, CLK_SEL_ETH_RX_25 checkreg RB_CLK_SEL_STAT_ETH_RX, CLK_SEL_ETH_RX_25 /* Put RMII clock to 25MHz we assume that RMII is always 100Mbits */ setreg RB_CLK_DIV_ETH_25, CLK_DIV_ETH_25_2 checkreg RB_CLK_DIV_STAT_ETH_25, CLK_DIV_ETH_25_2 setreg RB_CLK_SEL_ETH_MAC, CLK_SEL_ETH_MAC_RMII checkreg RB_CLK_SEL_STAT_ETH_MAC, CLK_SEL_ETH_MAC_RMII /* Enable RMII */ cmdon RB_CLK_CMD_ETH_RMII checkreg RB_CLK_STAT_ETH_RMII, CLK_IS_ON 100: /* Enable PHY Clock */ cmdon RB_CLK_CMD_OUT25 checkreg RB_CLK_STAT_OUT25, CLK_IS_ON mov pc, lr /* back to my caller */