#ifndef synop3504_hw_h #define synop3504_hw_h /* Cleopatre project {{{ * * Copyright (C) 2008 SPiDCOM Technologies * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * * }}} */ /** * \file driver/net/arm/synop3504_hw.h * \brief Hardware access for Synopsys 3504 driver. * \ingroup cleopatre_net_driver. * * Hardware access level part of the Ethernet 3504 Synopsys IP. */ /** Synopsys DMA descriptors for RX */ typedef struct { union { struct { volatile unsigned int err_mac : 1; //[ 0: 0] Rx MAC Address/Payload Checksum Error volatile unsigned int err_crc : 1; //[ 1: 1] CRC error volatile unsigned int err_drib : 1; //[ 2: 2] Dribble error volatile unsigned int err_recv : 1; //[ 3: 3] Receive error volatile unsigned int watchdog : 1; //[ 4: 4] Watchdog event occured volatile unsigned int type : 1; //[ 5: 5] Ethernet-type volatile unsigned int err_coll : 1; //[ 6: 6] Late collision volatile unsigned int err_ipc : 1; //[ 7: 7] IPC checksumm error volatile unsigned int last : 1; //[ 8: 8] last frame descriptor volatile unsigned int first : 1; //[ 9: 9] first frame descriptor volatile unsigned int vlan : 1; //[10:10] VLAN tag volatile unsigned int err_over : 1; //[11:11] overflow error volatile unsigned int err_length: 1; //[12:12] length/type error volatile unsigned int err_sfail : 1; //[13:13] source address fail volatile unsigned int err_desc : 1; //[14:14] Descriptor error volatile unsigned int err : 1; //[15:15] error summary volatile unsigned int length : 14; //[29:16] frame length volatile unsigned int err_dfail : 1; //[30:30] if set - destination address fail volatile unsigned int dma_own : 1; //[31:31] if set - owned by DMA }bf; volatile unsigned int val; }status; union { struct { volatile unsigned int length1 : 11; //[10: 0] Buffer1 length volatile unsigned int length2 : 11; //[21:11] Buffer2 length volatile unsigned int _reserved2 : 2; //[23:22] volatile unsigned int addr2en : 1; //[24:24] Addr2 is the next descr address volatile unsigned int eor : 1; //[25:25] End of ring volatile unsigned int _reserved1 : 5; //[30:26] volatile unsigned int int_dis : 1; //[31:31] Disable Int on Completion }bf; volatile unsigned int val; }ctrl; volatile unsigned int addr1; volatile unsigned int addr2; } __attribute__ ((__packed__)) SynopsysDmaRx; /** Synopsys DMA descriptors for TX */ typedef struct { union { struct { volatile unsigned int deffered : 1; //[ 0: 0] Deffered bit volatile unsigned int err_under : 1; //[ 1: 1] Underflow error volatile unsigned int exc_deff : 1; //[ 2: 2] excessive defferal volatile unsigned int coll_cnt : 4; //[ 6: 3] Collision count volatile unsigned int vlan : 1; //[ 7: 7] VLAN tag volatile unsigned int err_ecoll : 1; //[ 8: 8] Excessive collision volatile unsigned int err_lcoll : 1; //[ 9: 9] Late collision volatile unsigned int err_nocar : 1; //[10:10] No carrier volatile unsigned int err_clost : 1; //[11:11] Carrier lost volatile unsigned int err_plcs : 1; //[12:12] Payload/Checksumm error volatile unsigned int flushed : 1; //[13:13] Frame flushed volatile unsigned int err_jabt : 1; //[14:14] Jabber Timeout volatile unsigned int err : 1; //[15:15] error summary volatile unsigned int err_ip : 1; //[16:16] IP header error volatile unsigned int time_stamp: 1; //[17:17] Tx time stamp status volatile unsigned int _reserved: 13; //[30:18] volatile unsigned int dma_own : 1; //[31:31] if set - owned by DMA }bf; volatile unsigned int val; }status; union { struct { volatile unsigned int length1 : 11; //[10: 0] Buffer1 length volatile unsigned int length2 : 11; //[21:11] Buffer2 length volatile unsigned int ttime_stamp: 1; //[22:22] volatile unsigned int no_pad : 1; //[23:23] Disable padding volatile unsigned int addr2en : 1; //[24:24] Addr2 is the next descr address volatile unsigned int eor : 1; //[25:25] End of ring volatile unsigned int no_crc : 1; //[26:26] Disable CRC volatile unsigned int cs_ctrl : 2; //[28:27] Checksumm insertion control volatile unsigned int first : 1; //[29:29] First frame segment volatile unsigned int last : 1; //[30:30] Last frame segment volatile unsigned int int_oncomp: 1; //[31:31] Enable Int on Completion }bf; volatile unsigned int val; }ctrl; volatile unsigned int addr1; volatile unsigned int addr2; } __attribute__ ((__packed__)) SynopsysDmaTx; /** Synopsys Interrupt status */ typedef union { struct { unsigned int intTxCompleted: 1; //[ 0: 0] Transmit completed (Normal) unsigned int intTxStopped : 1; //[ 1: 1] Transmit process stopped (Abnormal) unsigned int intTxNoBuffer : 1; //[ 2: 2] Transmit buffer unavailable (Normal) unsigned int intTxJabberTO : 1; //[ 3: 3] Transmit Jabber Timeout (Abnormal) unsigned int intRxOverflow : 1; //[ 4: 4] Receive Buffer overflow interrupt unsigned int intTxUnderflow: 1; //[ 5: 5] Transmit underflow (Abnormal) unsigned int intRxCompleted: 1; //[ 6: 6] Completion of frame reception (Normal) unsigned int intRxNoBuffer : 1; //[ 7: 7] Receive buffer unavailable (Abnormal) unsigned int intRxStopped : 1; //[ 8: 8] Receive process stopped (Abnormal) unsigned int intRxWdogTO : 1; //[ 9: 9] Receive Watchdog Timeout (Abnormal) unsigned int intEarlyTx : 1; //[10:10] Early transmit interrupt (Abnormal) unsigned int reserved1 : 2; //[12:11] unsigned int intBusError : 1; //[13:13] Fatal bus error (Abnormal) unsigned int intEarlyRx : 1; //[14:14] Early receive interrupt (Normal) unsigned int intAbnormal : 1; //[15:15] Abnormal interrupt summary unsigned int intNormal : 1; //[16:16] Normal interrupt summary unsigned int rxState : 3; //[19:17] Receive process state unsigned int txState : 3; //[22:20] Transmit process state unsigned int errorBits : 3; //[25:23] Error bits unsigned int lineIntfIntr : 1; //[26:26] Line interface interrupt unsigned int MMCIntr : 1; //[27:27] MMC interrupt unsigned int PMTIntr : 1; //[28:28] PMT interrupt unsigned int tStampTrigInt : 1; //[29:29] Time Stamp Trigger interrupt unsigned int reserved2 : 2; //[31:30] }bf; unsigned int val; }SynopsysIntStatus; /** Synopsys device data */ typedef struct synopsys { uint32_t macbase; //Base address of MAC registers uint32_t dmabase; //Base address of DMA registers uint32_t phyaddr; //PHY device address on MII interface } Synopsys; uint16_t SynopsysMiiRead(Synopsys *synop, uint8_t reg); void SynopsysMiiWrite(Synopsys *synop, uint8_t reg, uint16_t data); /** * Initialisation of the Synopsys device. * \param synop Synopsys device structure. * \param macbase base address of MAC registers. * \param dmabase base address of DMA registers. * \param phyaddr MII phy device address. */ void SynopsysAttach(Synopsys *synop, uint32_t macbase, uint32_t dmabase, uint32_t phyaddr); void SynopsysInit(Synopsys *synop, uint32_t txaddr, uint32_t rxaddr); void SynopsysReset(Synopsys *synop); void SynopsysEnableInt(Synopsys *synop); void SynopsysDisableInt(Synopsys *synop); void SynopsysStartTx(Synopsys *synop); void SynopsysStopTx(Synopsys *synop); void SynopsysRestartTx(Synopsys *synop); void SynopsysStartRx(Synopsys *synop); void SynopsysStopRx(Synopsys *synop); void SynopsysRestartRx(Synopsys *synop); int SynopsysSetupEthernetAddress(Synopsys *synop, uint8_t *addr); int SynopsysSetSpeedDuplex(Synopsys *synop, int speed, int duplex); void SynopsysGetIntStatus(Synopsys *synop, SynopsysIntStatus *status); void SynopsysSetPromiscuousMode(Synopsys *synop, int value); void SynopsysSetMulticastFilter(Synopsys *synop, int value); #endif /* synop3504_hw_h */