#ifndef hal_phy_inc_bridgedma_h #define hal_phy_inc_bridgedma_h /* Cesar project {{{ * * Copyright (C) 2007 Spidcom * * <<>> * * }}} */ /** * \file hal/phy/inc/bridgedma.h * \brief Bridge DMA private header. * \ingroup hal_phy */ #include "hal/phy/bridgedma.h" #include "hal/phy/inc/bridgedma_common.h" #include "hal/phy/inc/bridgedma_it_mgr.h" /** Bridge DMA control and configuration. */ struct phy_bridgedma_ctrl_t { BITFIELDS_WORD( /** Host set start bit and Bridge DMA reset it when finished. */ u32 start:1;, /** Ethernet buffer endianness : TBD if 0, little endian. */ u32 eth_endian:1;, /** Segment endianness : TBD if 0, little endian. */ u32 pb_endian:1;, u32 :1;, /** Hprot, see hardware specification. */ u32 hprot:4;, u32 :24;) }; typedef struct phy_bridgedma_ctrl_t phy_bridgedma_ctrl_t; struct phy_bridgedma_pending_list_t { /** The head of the chain. */ phy_bridgedma_job_t *head; /** The tail of the chain. */ phy_bridgedma_job_t *tail; }; typedef struct phy_bridgedma_pending_list_t phy_bridgedma_pending_list_t; /** Bridge DMA context. */ struct phy_bridgedma_t { /** Bridge DMA common context. */ phy_bridgedma_common_t bridge; /** Interruption manager. */ phy_bridgedma_it_mgr_t it_mgr; /** Pending new list. * Workaround maria:#971. */ phy_bridgedma_pending_list_t jobs_pending; }; #endif /* hal_phy_inc_bridgedma_h */