From f90d1c90f65217429e0f585dd8104a58a9c3974e Mon Sep 17 00:00:00 2001 From: MSE500 Team Date: Thu, 22 Mar 2012 16:35:00 +0100 Subject: cleo/u-boot: add support for MIU controller, refs #2758 --- cleopatre/include/nvram.h | 19 ++- .../include/asm-arm/arch-spc300/nvram.h | 19 ++- cleopatre/tools/genNVRAM/genNVRAM.c | 160 +++++++++++++++++---- cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c | 14 +- cleopatre/u-boot-1.1.6/cpu/spc300/Makefile | 2 +- cleopatre/u-boot-1.1.6/cpu/spc300/miu.S | 66 +++++++++ cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S | 9 ++ cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S | 5 + .../include/asm-arm/arch-spc300/bus_sys.h | 4 + .../u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h | 28 ++++ .../include/asm-arm/arch-spc300/nvram.h | 21 ++- .../u-boot-1.1.6/include/configs/spc300_arch.h | 1 + 12 files changed, 302 insertions(+), 46 deletions(-) create mode 100644 cleopatre/u-boot-1.1.6/cpu/spc300/miu.S create mode 100644 cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h (limited to 'cleopatre') diff --git a/cleopatre/include/nvram.h b/cleopatre/include/nvram.h index 5238009c49..d946ea8e6a 100644 --- a/cleopatre/include/nvram.h +++ b/cleopatre/include/nvram.h @@ -49,10 +49,20 @@ typedef struct uint32_t gpio_0_7_cfg; // SPC300 GPIO 0 to 7 configuration register uint32_t gpio_8_15_cfg; // SPC300 GPIO 8 to 15 configuration register uint32_t gpio_allow_dir; // SPC300 GPIO allowed directions 0:none 1:in 2:out 3:bi - uint32_t sdram_config; // SPC300 SDRAM configuration register - uint32_t sdram_timing0; // SPC300 SDRAM timing register 0 - uint32_t sdram_timing1; // SPC300 SDRAM timing register 1 - uint32_t sdram_refresh; // SPC300 SDRAM refresh register + union { + struct { + uint32_t config; // SPC300 SDRAM configuration register + uint32_t timing0; // SPC300 SDRAM timing register 0 + uint32_t timing1; // SPC300 SDRAM timing register 1 + uint32_t refresh; // SPC300 SDRAM refresh register + } sdram; + struct { + uint16_t config_offset; // Offset of MIU config in nvram + uint16_t config_size; // Size of MIU config in words + uint32_t ram_size; // Size of MIU connected RAM in bytes + uint32_t reserved[2]; + } miu; + } dram; uint32_t flash_org; // Flash organization uint32_t img_0_offset; // Offset of first image address uint32_t nb_images; // Max Number of Images present in flash @@ -73,6 +83,7 @@ typedef struct uint32_t img_max_size; // Max size of an image in // flash uint32_t cpu_partnb; // SPC3x0 partnb + uint32_t dynamic[256]; // Dynamic data (see miu_config) } spc300_nvram_t; //Currently __attribute__((packed)) not needed #ifdef __KERNEL__ diff --git a/cleopatre/linux-2.6.25.10-spc300/include/asm-arm/arch-spc300/nvram.h b/cleopatre/linux-2.6.25.10-spc300/include/asm-arm/arch-spc300/nvram.h index 1860d6f0af..bf4a91e5ab 100644 --- a/cleopatre/linux-2.6.25.10-spc300/include/asm-arm/arch-spc300/nvram.h +++ b/cleopatre/linux-2.6.25.10-spc300/include/asm-arm/arch-spc300/nvram.h @@ -49,10 +49,20 @@ typedef struct uint32_t gpio_0_7_cfg; // SPC300 GPIO 0 to 7 configuration register uint32_t gpio_8_15_cfg; // SPC300 GPIO 8 to 15 configuration register uint32_t gpio_allow_dir; // SPC300 GPIO allowed directions 0:none 1:in 2:out 3:bi - uint32_t sdram_config; // SPC300 SDRAM configuration register - uint32_t sdram_timing0; // SPC300 SDRAM timing register 0 - uint32_t sdram_timing1; // SPC300 SDRAM timing register 1 - uint32_t sdram_refresh; // SPC300 SDRAM refresh register + union { + struct { + uint32_t config; // SPC300 SDRAM configuration register + uint32_t timing0; // SPC300 SDRAM timing register 0 + uint32_t timing1; // SPC300 SDRAM timing register 1 + uint32_t refresh; // SPC300 SDRAM refresh register + } sdram; + struct { + uint16_t config_offset; // Offset of MIU config in nvram + uint16_t config_size; // Size of MIU config in words + uint32_t ram_size; // Size of MIU connected RAM in bytes + uint32_t reserved[2]; + } miu; + } dram; uint32_t flash_org; // Flash organization uint32_t img_0_offset; // Offset of first image address uint32_t nb_images; // Max Number of Images present in flash @@ -71,6 +81,7 @@ typedef struct char manufactory_info[64]; // Name of the product manufacturer uint32_t img_max_size; // Max size of an image in flash uint32_t cpu_partnb; // SPC3x0 partnb + uint32_t dynamic[256]; // Dynamic data (see miu_config) } spc300_nvram_t; //Currently __attribute__((packed)) not needed #ifdef __KERNEL__ diff --git a/cleopatre/tools/genNVRAM/genNVRAM.c b/cleopatre/tools/genNVRAM/genNVRAM.c index 4061d01c11..3ba013b3eb 100644 --- a/cleopatre/tools/genNVRAM/genNVRAM.c +++ b/cleopatre/tools/genNVRAM/genNVRAM.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "nvram.h" @@ -153,10 +154,12 @@ static spc300_nvram_t nvram = { .gpio_0_7_cfg = DEFAULT_GPIO_0_7_CFG, /* SPC300 GPIO 0 to 7 configuration register */ .gpio_8_15_cfg = DEFAULT_GPIO_8_15_CFG, /* SPC300 GPIO 8 to 15 configuration register */ .gpio_allow_dir = DEFAULT_ALLOW_DIR, /* SPC300 GPIO allowed directions */ - .sdram_config = DEFAULT_SDRAM_CONFIG, /* SPC300 SDRAM configuration register */ - .sdram_timing0 = DEFAULT_SDRAM_TIMING0, /* SPC300 SDRAM timing register 0 */ - .sdram_timing1 = DEFAULT_SDRAM_TIMING1, /* SPC300 SDRAM timing register 1 */ - .sdram_refresh = DEFAULT_SDRAM_REFRESH, /* SPC300 SDRAM refresh register */ + .dram.sdram = { + .config = DEFAULT_SDRAM_CONFIG, /* SPC300 SDRAM configuration register */ + .timing0 = DEFAULT_SDRAM_TIMING0, /* SPC300 SDRAM timing register 0 */ + .timing1 = DEFAULT_SDRAM_TIMING1, /* SPC300 SDRAM timing register 1 */ + .refresh = DEFAULT_SDRAM_REFRESH, /* SPC300 SDRAM refresh register */ + }, .flash_org = DEFAULT_FLASH_ORG, /* Flash organization */ .img_0_offset = DEFAULT_IMAGE0_OFFSET, /* offset of first image address */ .nb_images = DEFAULT_NB_IMAGES, /* Max Number of Images present in flash */ @@ -176,6 +179,50 @@ static spc300_nvram_t nvram = { .cpu_partnb = DEFAULT_CPU_PARTNB, /* CPU version (for PRP support) */ }; +/* Next free position in dynamic NVRAM data. */ +static uint32_t *nvram_dynamic = nvram.dynamic; + +static enum +{ + DRAM_NOINIT, + DRAM_SDRAM, + DRAM_MIU, +} dram = DRAM_NOINIT; + +/* + * MIU configurations: pair of offset, value, where offset is relative to + * MIU_REG_BASE. + */ + +uint32_t miu_config_sdram_dini_64m[] = +{ + 0x0004, 0x00000894, + 0x0008, 0x00000185, + 0x000c, 0x00000120, + 0x0020, 0x00000031, + 0x00b4, 0x00002000, + 0x003c, 0x00000c01, + 0x003c, 0x00000c08, + 0x0000, 0x00000008, + 0x0000, 0x0000000c, + 0x0000, 0x0000000e, + 0x0000, 0x0000000f, + (uint32_t)-1 +}; + +struct miu_config_table_t +{ + char *name; + unsigned int ram_size; + uint32_t *config; +}; + +static const struct miu_config_table_t miu_config_table[] = +{ + { "sdram_dini_64m", 64 * 1024 * 1024, miu_config_sdram_dini_64m }, + NULL +}; + /* * Private functions */ @@ -192,6 +239,7 @@ static void print_usage(const char *cmd) " [ --stmg0r SDRAM timing0 register ]\n" " [ --stmg1r SDRAM timing1 register ]\n" " [ --srefr SDRAM refresh register ]\n" + " [ --miu-config MIU controller config ]\n" " [ --forg flash organization ]\n" " [ --img0off first image offset in flash ]\n" " [ --nbimg number of Linux images ]\n" @@ -314,29 +362,81 @@ static int parse_gpiodir(char *arg) return 0; } +static int parse_sdram_check(void) +{ + if (dram != DRAM_NOINIT && dram != DRAM_SDRAM) + { + fprintf (stderr, "Several DRAM controller configuration detected\n"); + return -1; + } + else + { + dram = DRAM_SDRAM; + return 0; + } +} + static int parse_sdramcfg(char *arg) { - nvram.sdram_config = (uint32_t)strtoul(arg, NULL, 0); - return 0; + nvram.dram.sdram.config = (uint32_t)strtoul(arg, NULL, 0); + return parse_sdram_check(); } static int parse_sdramtmg0(char *arg) { - nvram.sdram_timing0 = (uint32_t)strtoul(arg, NULL, 0); - return 0; + nvram.dram.sdram.timing0 = (uint32_t)strtoul(arg, NULL, 0); + return parse_sdram_check(); } static int parse_sdramtmg1(char *arg) { - nvram.sdram_timing1 = (uint32_t)strtoul(arg, NULL, 0); - return 0; + nvram.dram.sdram.timing1 = (uint32_t)strtoul(arg, NULL, 0); + return parse_sdram_check(); } static int parse_sdramrefr(char *arg) { - nvram.sdram_refresh = (uint32_t)strtoul(arg, NULL, 0); - return 0; + nvram.dram.sdram.refresh = (uint32_t)strtoul(arg, NULL, 0); + return parse_sdram_check(); +} + +static int parse_miu_config(char *arg) +{ + if (dram != DRAM_NOINIT) + { + fprintf (stderr, "Several DRAM controller configuration detected\n"); + return -1; + } + dram = DRAM_MIU; + /* Lookup the requested config. */ + const struct miu_config_table_t *p; + for (p = miu_config_table; p->name; p++) + { + if (strcmp(p->name, arg) == 0) + { + int size = 0; + nvram.dram.miu.config_offset = + (uint32_t) (nvram_dynamic - (uint32_t *) &nvram); + nvram.dram.miu.ram_size = p->ram_size; + nvram.dram.miu.reserved[0] = 0; + nvram.dram.miu.reserved[1] = 0; + uint32_t *config; + /* Translate the configuration into NVRAM format, see miu.S in + * u-boot. */ + for (config = p->config; *config != (uint32_t) -1; config += 2) + { + assert (!(config[0] & ~0x3fffc)); + assert (!(config[1] & ~0xffff)); + *nvram_dynamic++ = (config[0] >> 2 << 16) | config[1]; + size++; + } + nvram.dram.miu.config_size = size; + return 0; + } + } + return -1; } + static int parse_forg(char *arg) { unsigned int sector_size; @@ -502,6 +602,7 @@ struct parser parse_table[] = { "stmg0r", parse_sdramtmg0 }, { "stmg1r", parse_sdramtmg1 }, { "srefr", parse_sdramrefr }, + { "miu_config", parse_miu_config }, { "forg", parse_forg }, { "img0off", parse_img0off }, { "nbimg", parse_nbimg }, @@ -575,23 +676,24 @@ int main(int argc, char **argv) { "stmg0r", required_argument, NULL, 7 }, { "stmg1r", required_argument, NULL, 8 }, { "srefr", required_argument, NULL, 9 }, - { "forg", required_argument, NULL, 10 }, - { "img0off", required_argument, NULL, 11 }, - { "nbimg", required_argument, NULL, 12 }, - { "name", required_argument, NULL, 13 }, - { "partnb", required_argument, NULL, 14 }, - { "desc", required_argument, NULL, 15 }, - { "serial", required_argument, NULL, 16 }, - { "phy", required_argument, NULL, 17 }, - { "ethernet", required_argument, NULL, 18 }, - { "plc", required_argument, NULL, 19 }, - { "dpw", required_argument, NULL, 20 }, - { "oem", required_argument, NULL, 21 }, - { "tonemask", required_argument, NULL, 22 }, - { "factory", required_argument, NULL, 23 }, - { "portnb", required_argument, NULL, 24 }, - { "imgmaxsize", required_argument, NULL, 25 }, - { "cpupartnb", required_argument, NULL, 26 }, + { "miu-config", required_argument, NULL, 10 }, + { "forg", required_argument, NULL, 11 }, + { "img0off", required_argument, NULL, 12 }, + { "nbimg", required_argument, NULL, 13 }, + { "name", required_argument, NULL, 14 }, + { "partnb", required_argument, NULL, 15 }, + { "desc", required_argument, NULL, 16 }, + { "serial", required_argument, NULL, 17 }, + { "phy", required_argument, NULL, 18 }, + { "ethernet", required_argument, NULL, 19 }, + { "plc", required_argument, NULL, 20 }, + { "dpw", required_argument, NULL, 21 }, + { "oem", required_argument, NULL, 22 }, + { "tonemask", required_argument, NULL, 23 }, + { "factory", required_argument, NULL, 24 }, + { "portnb", required_argument, NULL, 25 }, + { "imgmaxsize", required_argument, NULL, 26 }, + { "cpupartnb", required_argument, NULL, 27 }, }; while( ( c = getopt_long_only(argc, argv, "", long_opts, &opt_index) ) != -1 ) diff --git a/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c b/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c index 6497625b0a..482838819d 100644 --- a/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c +++ b/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c @@ -40,13 +40,14 @@ void show_boot_progress(int progress) */ ulong get_sdram_size(bd_t *bd) { - spc300_nvram_t *nvram = NULL; + spc300_nvram_t *nvram; + /* We will access to NVRAM through SPI direct access */ + nvram = (spc300_nvram_t *)(bd->bi_nvram_addr); +#if defined (CONFIG_CHIP_FEATURE_SDRAM_CTRL) ulong sconr; ulong row, col, bank, byte; - /* We will access to NVRAM through SPI direct access */ - nvram = (spc300_nvram_t *)(bd->bi_nvram_addr); - sconr = nvram->sdram_config; + sconr = nvram->dram.sdram.config; bank = 1 << ( ( (sconr & SCONR_s_bank_addr_width_RegisterMask) >> SCONR_s_bank_addr_width_BitAddressOffset) + 1); row = 1 << ( ( (sconr & SCONR_s_row_addr_width_RegisterMask) >> SCONR_s_row_addr_width_BitAddressOffset) + 1); @@ -54,6 +55,11 @@ ulong get_sdram_size(bd_t *bd) byte = ( ( 1<<( (sconr & SCONR_s_data_width_RegisterMask) >> SCONR_s_data_width_BitAddressOffset) ) * 2); return (bank * row * col * byte); +#elif defined (CONFIG_CHIP_FEATURE_MIU_CTRL) + return nvram->dram.miu.ram_size; +#else +# error "Unknown DRAM controller" +#endif } /** diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile index 6c4ccc9b1f..ab0922d72b 100644 --- a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile +++ b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile @@ -23,7 +23,7 @@ LIB = lib$(CPU).a START = start.o OBJS = interrupts.o cpu.o timer.o serial.o wdt.o -SOBJS = reset.o pll_init.o eth_init.o nvram.o dsp.o sdram.o +SOBJS = reset.o pll_init.o eth_init.o nvram.o dsp.o sdram.o miu.o all: .depend $(START) $(LIB) diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S new file mode 100644 index 0000000000..ce69ae6892 --- /dev/null +++ b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S @@ -0,0 +1,66 @@ +/* + * cpu/spc300/miu.S + * + * Copyright (C) 2012 SPiDCOM Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Skip file if not using MIU controller. */ +#ifdef CONFIG_CHIP_FEATURE_MIU_CTRL + + .file "miu.S" + + .text + .arm @ This is ARM code; performs the same action as .code 32 + .align 2 @ Align to word boundary; "2" means the number of bits that must be zero + .globl sdram_init + .type sdram_init, %function + + +sdram_init: + ldr r0, =MIU_REG_BASE + ldr r1, [r10, #NVRAM_MIU_CONFIG_OFFSET] + lsr r2, r1, #16 /* r2: config size. */ + lsl r1, r1, #16 + lsrs r1, r1, #16 /* r1: offset in nvram. */ +1: beq 1b /* Infinite loop of death if no MIU config. */ + +1: /* Write registers according to config words. + * Each config word is composed of: + * - bit 31 to 16: an offset in word to add to MIU_REG_BASE, + * - bit 15 to 0: the value to write at this address. */ + ldr r3, [r10, r1, lsl #2] + lsr r4, r3, #16 /* r4: offset. */ + lsl r3, r3, #16 + lsr r3, r3, #16 /* r3: value to write. */ + str r3, [r0, r4, lsl #2] + add r1, r1, #1 + subs r2, r2, #1 + bne 1b + +1: /* Wait until init done. */ + ldr r3, [r0, #MIU_INIT_DONE_REG] + tst r3, #(1 << MIU_INIT_DONE_BIT) + beq 1b + + /* Back to my caller. */ + mov pc, lr + +#endif /* CONFIG_CHIP_FEATURE_MIU_CTRL */ diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S index 92c4a3b28d..f21a751025 100644 --- a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S +++ b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S @@ -107,10 +107,19 @@ nvram_dft: .word 0x00000000 /* gpio_0_7_cfg */ .word 0x00000000 /* gpio_8_15_cfg */ .word 0xffffffff /* gpio_allow_dir*/ +#if defined (CONFIG_CHIP_FEATURE_SDRAM_CTRL) .word 0x001c3168 /* sdram_config */ .word 0x022a569a /* sdram_timing0 */ .word 0x00070008 /* sdram_timing1 */ .word 0x00000410 /* sdram_refresh */ +#elif defined (CONFIG_CHIP_FEATURE_MIU_CTRL) + .word 0 /* miu_config */ + .word 0 /* miu_ram_size */ + .word 0 + .word 0 +#else +# error "Unknown DRAM controller" +#endif .word 0x00000007 /* flash_org */ .word 0x00140000 /* img_0_offset */ .word 0x00000001 /* nb_images */ diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S index 364cfde74a..a61bb8fbc0 100644 --- a/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S +++ b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S @@ -22,6 +22,9 @@ #include #include +/* Skip file if not using SDRAM controller. */ +#ifdef CONFIG_CHIP_FEATURE_SDRAM_CTRL + .file "sdram.S" .text @@ -87,3 +90,5 @@ sdram_init: /* Back to my caller. */ mov pc, lr + +#endif /* CONFIG_CHIP_FEATURE_SDRAM_CTRL */ diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h index e4070dd1e3..b0ce550a14 100644 --- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h +++ b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h @@ -41,6 +41,10 @@ #define TCU_BASE (0x20000000) +#define MIU_REG_BASE (0xC8050000) +#define MIU_ATOP_REG_BASE (0xC8060000) +#include "miu.h" + #define SDRAM_CTRL_BASE (0xE0000000) #include "sdram.h" diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h new file mode 100644 index 0000000000..eb74a5177b --- /dev/null +++ b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h @@ -0,0 +1,28 @@ +/* + * include/asm-arm/arch-spc300/miu.h + * + * Copyright (C) 2012 SPiDCOM Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MIU_H +#define __ASM_ARCH_MIU_H + +#define MIU_INIT_DONE_REG 0 +#define MIU_INIT_DONE_BIT 15 + +#endif /* __ASM_ARCH_MIU_H */ diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/nvram.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/nvram.h index 879fe3f29a..51ece26abe 100644 --- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/nvram.h +++ b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/nvram.h @@ -32,6 +32,8 @@ #define NVRAM_SDRAM_TIMING0_OFFSET 0x1C #define NVRAM_SDRAM_TIMING1_OFFSET 0x20 #define NVRAM_SDRAM_REFRESH_OFFSET 0x24 +#define NVRAM_MIU_CONFIG_OFFSET 0x18 +#define NVRAM_MIU_RAM_SIZE_OFFSET 0x1C #define NVRAM_FLASH_ORG_OFFSET 0x28 #define NVRAM_IMG_0_OFFSET_OFFSET 0x2C #define NVRAM_NB_IMAGES_OFFSET 0x30 @@ -183,10 +185,20 @@ typedef struct uint32_t gpio_0_7_cfg; // SPC300 GPIO 0 to 7 configuration register uint32_t gpio_8_15_cfg; // SPC300 GPIO 8 to 15 configuration register uint32_t gpio_allow_dir; // SPC300 GPIO allowed direction 0:none 1:in 2:out 3:bi - uint32_t sdram_config; // SPC300 SDRAM configuration register - uint32_t sdram_timing0; // SPC300 SDRAM timing register 0 - uint32_t sdram_timing1; // SPC300 SDRAM timing register 1 - uint32_t sdram_refresh; // SPC300 SDRAM refresh register + union { + struct { + uint32_t config; // SPC300 SDRAM configuration register + uint32_t timing0; // SPC300 SDRAM timing register 0 + uint32_t timing1; // SPC300 SDRAM timing register 1 + uint32_t refresh; // SPC300 SDRAM refresh register + } sdram; + struct { + uint16_t config_offset; // Offset of MIU config in nvram + uint16_t config_size; // Size of MIU config in words + uint32_t ram_size; // Size of MIU connected RAM in bytes + uint32_t reserved[2]; + } miu; + } dram; uint32_t flash_org; // Flash organization uint32_t img_0_offset; // Offset of first image address uint32_t nb_images; // Max Number of Images present in flash @@ -205,6 +217,7 @@ typedef struct char manufactory_info[64]; // Name of the product manufacturer uint32_t img_max_size; // Max size of an image in flash uint32_t cpu_partnb; // SPC3x0 partnb + uint32_t dynamic[256]; // Dynamic data (see miu_config) } spc300_nvram_t; //Currently __attribute__((packed)) not needed // Bit manipulation macros diff --git a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h index acedd73c14..15b1814b8c 100644 --- a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h +++ b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h @@ -25,6 +25,7 @@ #define CONFIG_ARCH_SPC300 1 #if defined (CONFIG_CHIP_SPC300) +# define CONFIG_CHIP_FEATURE_SDRAM_CTRL 1 # define CONFIG_CHIP_FEATURE_SYNOP3504 1 # define CONFIG_CHIP_FEATURE_SYNC_DSP_CLOCK 1 # define CONFIG_CHIP_MAX_MASTER_CLOCK 147000000 -- cgit v1.2.3