From 8c1eb022607c0aba81d93b961abbfb47a2dcc325 Mon Sep 17 00:00:00 2001 From: Fisher Cheng Date: Fri, 24 May 2013 16:54:08 +0800 Subject: cleo/devkit: add MTK MT7601U drv source code, refs #4011 - Enable Wireless LAN and Wireless extension in linux26.config --- cleopatre/devkit/mt7601udrv/ate/chips/mt7601_ate.c | 921 +++ cleopatre/devkit/mt7601udrv/ate/common/ate_usb.c | 627 ++ cleopatre/devkit/mt7601udrv/ate/common/rt_ate.c | 6298 ++++++++++++++++++++ cleopatre/devkit/mt7601udrv/ate/common/rt_qa.c | 2497 ++++++++ cleopatre/devkit/mt7601udrv/ate/include/rt_ate.h | 808 +++ cleopatre/devkit/mt7601udrv/ate/include/rt_qa.h | 181 + 6 files changed, 11332 insertions(+) create mode 100644 cleopatre/devkit/mt7601udrv/ate/chips/mt7601_ate.c create mode 100644 cleopatre/devkit/mt7601udrv/ate/common/ate_usb.c create mode 100644 cleopatre/devkit/mt7601udrv/ate/common/rt_ate.c create mode 100644 cleopatre/devkit/mt7601udrv/ate/common/rt_qa.c create mode 100644 cleopatre/devkit/mt7601udrv/ate/include/rt_ate.h create mode 100644 cleopatre/devkit/mt7601udrv/ate/include/rt_qa.h (limited to 'cleopatre/devkit/mt7601udrv/ate') diff --git a/cleopatre/devkit/mt7601udrv/ate/chips/mt7601_ate.c b/cleopatre/devkit/mt7601udrv/ate/chips/mt7601_ate.c new file mode 100644 index 0000000000..208d3968b1 --- /dev/null +++ b/cleopatre/devkit/mt7601udrv/ate/chips/mt7601_ate.c @@ -0,0 +1,921 @@ +/* + *************************************************************************** + * Ralink Tech Inc. + * 4F, No. 2 Technology 5th Rd. + * Science-based Industrial Park + * Hsin-chu, Taiwan, R.O.C. + * + * (c) Copyright 2002-2011, Ralink Technology, Inc. + * + * All rights reserved. Ralink's source code is an unpublished work and the + * use of a copyright notice does not imply otherwise. This source code + * contains confidential trade secret material of Ralink Tech. Any attemp + * or participation in deciphering, decoding, reverse engineering or in any + * way altering the source code is stricitly prohibited, unless the prior + * written consent of Ralink Technology, Inc. is obtained. + *************************************************************************** + + Module Name: + rt5592_ate.c + + Abstract: + Specific ATE funcitons and variables for RT5572/RT5592 + + Revision History: + Who When What + -------- ---------- ---------------------------------------------- +*/ + + +#ifdef MT7601 + +#include "rt_config.h" + +extern MT7601_FREQ_ITEM MT7601_Frequency_Plan[]; +extern UINT32 NUM_OF_MT7601_CHNL; +extern RTMP_REG_PAIR MT7601_BBP_BW20RegTb[]; +extern UCHAR MT7601_BBP_BW20RegTb_Size; +extern RTMP_REG_PAIR MT7601_BBP_BW40RegTb[]; +extern UCHAR MT7601_BBP_BW40RegTb_Size; +extern RTMP_REG_PAIR MT7601_BBP_HighTempBW20RegTb[]; +extern UCHAR MT7601_BBP_HighTempBW20RegTb_Size; +extern RTMP_REG_PAIR MT7601_BBP_HighTempBW40RegTb[]; +extern UCHAR MT7601_BBP_HighTempBW40RegTb_Size; +extern RTMP_REG_PAIR MT7601_BBP_LowTempBW20RegTb[]; +extern UCHAR MT7601_BBP_LowTempBW20RegTb_Size; +extern RTMP_REG_PAIR MT7601_BBP_LowTempBW40RegTb[]; +extern UCHAR MT7601_BBP_LowTempBW40RegTb_Size; + +VOID MT7601ATEAsicSwitchChannel( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 Value = 0; + CHAR TxPwer = 0; + UCHAR index = 0, Channel = 0; + /* added to prevent RF register reading error */ + UCHAR RFValue = 0; + INT IdReg; + RTMP_CHIP_CAP *pChipCap = &pAd->chipCap; + + SYNC_CHANNEL_WITH_QA(pATEInfo, &Channel); + + DBGPRINT(RT_DEBUG_TRACE, ("==> %s: SwitchChannel#%d BW = %x\n", + __FUNCTION__, Channel, pAd->ate.TxWI.TxWIBW)); + + /* fill Tx power value */ + TxPwer = pATEInfo->TxPower0; + + if (Channel > 14) + { + DBGPRINT(RT_DEBUG_ERROR, ("%s: Can't find the Channel#%d \n", __FUNCTION__, Channel)); + return; + } + + for (index = 0; index < NUM_OF_MT7601_CHNL; index++) + { + if (Channel == MT7601_Frequency_Plan[index].Channel) + { + /* Frequeny plan setting */ + AndesRFRandomWrite(pAd, 4, + RF_BANK0, RF_R17, MT7601_Frequency_Plan[index].K_R17, + RF_BANK0, RF_R18, MT7601_Frequency_Plan[index].K_R18, + RF_BANK0, RF_R19, MT7601_Frequency_Plan[index].K_R19, + RF_BANK0, RF_R20, MT7601_Frequency_Plan[index].N_R20); + } + } + + RTMP_IO_READ32(pAd, TX_ALC_CFG_0, &Value); + Value = Value & (~0x3F3F); + Value |= (TxPwer & 0x3F); + RTMP_IO_WRITE32(pAd, TX_ALC_CFG_0, Value); + + /* BBP setting */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); + + //RtmpUpdateFilterCoefficientControl(pAd, Channel); + + /* + vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration. + */ + rlt_rf_write(pAd, RF_BANK0, RF_R04, 0x0A); + rlt_rf_write(pAd, RF_BANK0, RF_R05, 0x20); + rlt_rf_read(pAd, RF_BANK0, RF_R04, &RFValue); + RFValue = RFValue | 0x80; + rlt_rf_write(pAd, RF_BANK0, RF_R04, RFValue); + RTMPusecDelay(2000); + + rtmp_bbp_set_bw(pAd, pAd->ate.TxWI.TxWIBW); + + switch (pAd->ate.TxWI.TxWIBW) + { + case BW_20: + if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_HIGH ) + { + AndesBBPRandomWritePair(pAd, MT7601_BBP_HighTempBW20RegTb, MT7601_BBP_HighTempBW20RegTb_Size); + } + else if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_LOW ) + { + AndesBBPRandomWritePair(pAd, MT7601_BBP_LowTempBW20RegTb, MT7601_BBP_LowTempBW20RegTb_Size); + } + else + { + AndesBBPRandomWritePair(pAd, MT7601_BBP_BW20RegTb, MT7601_BBP_BW20RegTb_Size); + } + + + /* Tx Filter BW */ + AndesCalibrationOP(pAd, ANDES_CALIBRATION_BW, 0x10001); + /* Rx Filter BW */ + AndesCalibrationOP(pAd, ANDES_CALIBRATION_BW, 0x10000); + break; + case BW_40: + if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_HIGH ) + { + AndesBBPRandomWritePair(pAd, MT7601_BBP_HighTempBW40RegTb, MT7601_BBP_HighTempBW40RegTb_Size); + } + else if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_LOW ) + { + AndesBBPRandomWritePair(pAd, MT7601_BBP_LowTempBW40RegTb, MT7601_BBP_LowTempBW40RegTb_Size); + } + else + { + AndesBBPRandomWritePair(pAd, MT7601_BBP_BW40RegTb, MT7601_BBP_BW40RegTb_Size); + } + + /* Tx Filter BW */ + AndesCalibrationOP(pAd, ANDES_CALIBRATION_BW, 0x10101); + /* Rx Filter BW */ + AndesCalibrationOP(pAd, ANDES_CALIBRATION_BW, 0x10100); + + break; + default: + break; + } + + ATEAsicSetTxRxPath(pAd); + + DBGPRINT(RT_DEBUG_TRACE, ("<== %s: SwitchChannel#%d\n", + __FUNCTION__, Channel)); + +} + + +INT MT7601ATETxPwrHandler( + IN PRTMP_ADAPTER pAd, + IN char index) +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR TxPower = 0; + UCHAR MaxPower; + UINT32 RegValue = 0; + UCHAR Channel = pATEInfo->Channel; + +#ifdef RALINK_QA + if ((pATEInfo->bQATxStart == TRUE) || (pATEInfo->bQARxStart == TRUE)) + { + return 0; + } + else +#endif /* RALINK_QA */ + if (index == 0) + { + TxPower = pATEInfo->TxPower0; + } + else + { + DBGPRINT_ERR(("%s : Only TxPower0 and TxPower1 are adjustable !\n", __FUNCTION__)); + DBGPRINT_ERR(("%s : TxPower%d is out of range !\n", __FUNCTION__, index)); + return -1; + } + + if (Channel <= 14) /* G band */ + { + +#ifdef RTMP_INTERNAL_TX_ALC + if ( pATEInfo->bAutoTxAlc == FALSE ) + { + RTMP_IO_READ32(pAd, TX_ALC_CFG_1, &RegValue); + RegValue &= ~(0xFFFF); + RTMP_IO_WRITE32(pAd, TX_ALC_CFG_1, RegValue); + } + else + { + RTMP_IO_WRITE32(pAd, TX_ALC_CFG_1, pAd->chipCap.TxALCData.InitTxAlcCfg1); + } +#endif /* RTMP_INTERNAL_TX_ALC */ + + RTMP_IO_READ32(pAd, TX_ALC_CFG_0, &RegValue); + MaxPower = RegValue >> 24; + RegValue = RegValue & (~0x3F3F); + if ( TxPower > MaxPower ) + TxPower = MaxPower; + RegValue |= (TxPower & 0x3F); + RTMP_IO_WRITE32(pAd, TX_ALC_CFG_0, RegValue); + + } + + DBGPRINT(RT_DEBUG_TRACE, ("%s : (TxPower%d=%d)\n", __FUNCTION__, index, TxPower)); + + return 0; +} + + +/* +========================================================================== + Description: + Set RT5370 and RT5372 and RT5390 and RT5392 ATE RF BW + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT MT7601_Set_ATE_TX_BW_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + INT powerIndex; + UCHAR value = 0; + UCHAR BBPCurrentBW; + INT IdReg; + RTMP_CHIP_CAP *pChipCap = &pAd->chipCap; + + + BBPCurrentBW = simple_strtol(arg, 0, 10); + + if ((BBPCurrentBW == 0)) + { + pAd->ate.TxWI.TxWIBW = BW_20; + } + else + { + pAd->ate.TxWI.TxWIBW = BW_40; + } + + if ((pAd->ate.TxWI.TxWIPHYMODE == MODE_CCK) && (pAd->ate.TxWI.TxWIBW == BW_40)) + { + DBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_BW_Proc!! Warning!! CCK only supports 20MHZ!!\nBandwidth switch to 20\n")); + pAd->ate.TxWI.TxWIBW = BW_20; + } + + if (pAd->ate.TxWI.TxWIBW == BW_20) + { + if (pAd->ate.Channel <= 14) + { + /* BW=20;G band */ + for (powerIndex=0; powerIndexTx20MPwrCfgGBand[powerIndex] == 0xffffffff) + continue; + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgGBand[powerIndex]); + RtmpOsMsDelay(5); + } + } + + /* BW=20 */ + { + /* Set BBP R4 bit[4:3]=0:0 */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, &value); + value &= (~0x18); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value); + } + + if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_HIGH ) + { + for(IdReg=0; IdReg < MT7601_BBP_HighTempBW20RegTb_Size; IdReg++) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, MT7601_BBP_HighTempBW20RegTb[IdReg].Register, + MT7601_BBP_HighTempBW20RegTb[IdReg].Value); + } + } + else if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_LOW ) + { + for(IdReg=0; IdReg < MT7601_BBP_LowTempBW20RegTb_Size; IdReg++) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, MT7601_BBP_LowTempBW20RegTb[IdReg].Register, + MT7601_BBP_LowTempBW20RegTb[IdReg].Value); + } + } + else + { + for(IdReg=0; IdReg < MT7601_BBP_BW20RegTb_Size; IdReg++) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, MT7601_BBP_BW20RegTb[IdReg].Register, + MT7601_BBP_BW20RegTb[IdReg].Value); + } + } + + /* Please don't move this block backward. */ + /* BBP_R4 should be overwritten for every chip if the condition matched. */ + if (pAd->ate.Channel == 14) + { + INT TxMode = pAd->ate.TxWI.TxWIPHYMODE; + + if (TxMode == MODE_CCK) + { + /* when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1 */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, &value); + value |= 0x20; /* set bit5=1 */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value); + } + } + } + /* If bandwidth = 40M, set RF Reg4 bit 21 = 0. */ + else if (pAd->ate.TxWI.TxWIBW == BW_40) + { + if (pAd->ate.Channel <= 14) + { + /* BW=40;G band */ + for (powerIndex=0; powerIndexTx40MPwrCfgGBand[powerIndex] == 0xffffffff) + continue; + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgGBand[powerIndex]); + RtmpOsMsDelay(5); + } + } + + { + /* Set BBP R4 bit[4:3]=1:0 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value); + value &= (~0x18); + value |= 0x10; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value); + } + + if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_HIGH ) + { + for(IdReg=0; IdReg < MT7601_BBP_HighTempBW40RegTb_Size; IdReg++) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, MT7601_BBP_HighTempBW40RegTb[IdReg].Register, + MT7601_BBP_HighTempBW40RegTb[IdReg].Value); + } + } + else if ( pChipCap->TemperatureMode == TEMPERATURE_MODE_LOW ) + { + for(IdReg=0; IdReg < MT7601_BBP_LowTempBW40RegTb_Size; IdReg++) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, MT7601_BBP_LowTempBW40RegTb[IdReg].Register, + MT7601_BBP_LowTempBW40RegTb[IdReg].Value); + } + } + else + { + for(IdReg=0; IdReg < MT7601_BBP_BW40RegTb_Size; IdReg++) + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, MT7601_BBP_BW40RegTb[IdReg].Register, + MT7601_BBP_BW40RegTb[IdReg].Value); + } + } + + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_BW_Proc (BBPCurrentBW = %d)\n", pAd->ate.TxWI.TxWIBW)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_BW_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + + + + + +#ifdef RTMP_INTERNAL_TX_ALC + + +BOOLEAN MT7601ATEGetTssiCompensationParam( + IN PRTMP_ADAPTER pAd, + OUT PCHAR TssiLinear0, + OUT PCHAR TssiLinear1, + OUT PINT32 TargetPower) +{ +#define MAX_TSSI_WAITING_COUNT 40 + UCHAR RFReg, BBPReg; + UCHAR PacketType; + UCHAR BbpR47; + UCHAR TxRate; + INT32 Power; + UINT count; + UCHAR ch = 0; + MT7601_TX_ALC_DATA *pTxALCData = &pAd->chipCap.TxALCData; + + if ((pAd->ate.Channel >= 1) && (pAd->ate.Channel <= 14)) + { + ch = pAd->ate.Channel; + } + else + { + ch = 1; + + DBGPRINT(RT_DEBUG_ERROR, ("%s::Incorrect channel #%d\n", __FUNCTION__, pAd->ate.Channel)); + } + + if ( pTxALCData->TssiTriggered == 0 ) + { + if ( RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_MCU_SEND_IN_BAND_CMD) ) + { + MT7601_EnableTSSI(pAd); + pTxALCData->TssiTriggered = 1; + } + + return FALSE; + } + + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R47, &BBPReg); + if(BBPReg & 0x10) + { + printk("#\n"); + + return FALSE; + } + + /* 4. Read TSSI */ + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R47, &BbpR47); + BbpR47 = (BbpR47 & ~0x07); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, BbpR47); + RTMPusecDelay(500); + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, TssiLinear0); + + + /* 5. Read Temperature */ + BbpR47 = (BbpR47 & ~0x07) | 0x04; + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, BbpR47); + RTMPusecDelay(500); + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &(pAd->chipCap.CurrentTemperBbpR49)); + + BbpR47 = (BbpR47 & ~0x07) | 0x01; + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, BbpR47); + RTMPusecDelay(500); + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &PacketType); + + DBGPRINT(RT_DEBUG_TRACE, ("TSSI = 0x%X\n", *TssiLinear0)); + DBGPRINT(RT_DEBUG_TRACE, ("temperature = 0x%X\n", pAd->chipCap.CurrentTemperBbpR49)); + //DBGPRINT(RT_DEBUG_TRACE, ("PacketType = 0x%X\n", PacketType)); + + Power = pAd->ate.TxPower0; + + //DBGPRINT(RT_DEBUG_TRACE, ("Channel Desire Power = %d\n", Power)); + + switch ( PacketType & 0x03) + { + case 0: + TxRate = (PacketType >> 2) & 0x03; + DBGPRINT(RT_DEBUG_TRACE, ("tx_11b_rate: %x\n", TxRate)); + switch (TxRate) + { + case 0: // 1 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_CCK_1M : BW20_MCS_POWER_CCK_1M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_CCK_1M; + break; + case 1: // 2 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_CCK_2M : BW20_MCS_POWER_CCK_2M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_CCK_2M; + break; + case 2: // 5.5 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_CCK_5M : BW20_MCS_POWER_CCK_5M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_CCK_5M; + break; + case 3: // 11Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_CCK_11M : BW20_MCS_POWER_CCK_11M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_CCK_11M; + break; + } + + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R178, &BBPReg); + if ( BBPReg == 0 ) + { + Power += 24576; // 3 * 8192 + } + else + { + Power += 819; //0.1 x 8192; + } + break; + case 1: + TxRate = (PacketType >> 4) & 0x0F; + DBGPRINT(RT_DEBUG_TRACE, ("tx_11g_rate: %x\n", TxRate)); + switch ( TxRate ) + { + case 0xB: // 6 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_6M : BW20_MCS_POWER_OFDM_6M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_6M; + break; + case 0xF: // 9 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_9M : BW20_MCS_POWER_OFDM_9M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_9M; + break; + case 0xA: // 12 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_12M : BW20_MCS_POWER_OFDM_12M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_12M; + break; + case 0xE: // 18 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_18M : BW20_MCS_POWER_OFDM_18M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_18M; + break; + case 0x9: // 24 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_24M : BW20_MCS_POWER_OFDM_24M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_24M; + break; + case 0xD: // 36 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_36M : BW20_MCS_POWER_OFDM_36M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_36M; + break; + case 0x8: // 48 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_48M : BW20_MCS_POWER_OFDM_48M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_48M; + break; + case 0xC: // 54 Mbps + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_OFDM_54M : BW20_MCS_POWER_OFDM_54M; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_OFDM_54M; + break; + } + break; + default: + BbpR47 = (BbpR47 & ~0x07) | 0x02; + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, BbpR47); + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &TxRate); + DBGPRINT(RT_DEBUG_TRACE, ("tx_11n_rate: %x\n", TxRate)); + TxRate &= 0x7F; // TxRate[7] is bandwidth + switch ( TxRate ) + { + case 0x0: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS0: BW20_MCS_POWER_HT_MCS0; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS0; + break; + case 0x1: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS1: BW20_MCS_POWER_HT_MCS1; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS1; + break; + case 0x2: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS2: BW20_MCS_POWER_HT_MCS2; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS2; + break; + case 0x3: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS3: BW20_MCS_POWER_HT_MCS3; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS3; + break; + case 0x4: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS4: BW20_MCS_POWER_HT_MCS4; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS4; + break; + case 0x5: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS5: BW20_MCS_POWER_HT_MCS5; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS5; + break; + case 0x6: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS6: BW20_MCS_POWER_HT_MCS6; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS6; + break; + case 0x7: + Power += (pAd->ate.TxWI.TxWIBW == BW_40)? BW40_MCS_POWER_HT_MCS7: BW20_MCS_POWER_HT_MCS7; + Power = Power << 12; + DBGPRINT(RT_DEBUG_TRACE, ("Channel PWR + MCS PWR = %x\n", Power)); + Power += RF_PA_MODE_HT_MCS7; + break; + + } + break; + } + + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BBPReg); + switch ( BBPReg & 0x3 ) + { + case 1: + Power -= 49152; // -6 dB*8192 + break; + case 2: + Power -= 98304; //-12 dB*8192 + break; + case 3: + Power += 49152; // 6 dB*8192 + break; + case 0: + default: + break; + } + + Power += pTxALCData->MT7601_TSSI_T0_Delta_Offset; + + *TargetPower = Power; + DBGPRINT(RT_DEBUG_TRACE, ("TargetPower: 0x%x(%d)\n", *TargetPower, *TargetPower)); + + return TRUE; + +} + + +VOID MT7601ATEAsicTxAlcGetAutoAgcOffset( + IN PRTMP_ADAPTER pAd) +{ + INT32 TargetPower, CurrentPower, PowerDiff; + UCHAR TssiLinear0, TssiLinear1; + CHAR tssi_offset; + INT16 tssi_db, tssi_m_dc; + UINT32 value; + UCHAR ch = 0; + MT7601_TX_ALC_DATA *pTxALCData = &pAd->chipCap.TxALCData; + PATE_INFO pATEInfo = &(pAd->ate); + + //if (pATEInfo->OneSecPeriodicRound % 4 == 0) + { + + if ((pAd->ate.Channel >= 1) && (pAd->ate.Channel <= 14)) + { + ch = pAd->ate.Channel; + } + else + { + ch = 1; + + DBGPRINT(RT_DEBUG_ERROR, ("%s::Incorrect channel #%d\n", __FUNCTION__, pAd->ate.Channel)); + } + + // if base power is lower than 10 dBm use High VGA + if(pAd->TxPower[ch - 1].Power <= 20) + pTxALCData->TSSI_USE_HVGA = 1; + else + pTxALCData->TSSI_USE_HVGA = 0; + + if (MT7601ATEGetTssiCompensationParam(pAd, &TssiLinear0 , &TssiLinear1, &TargetPower) == FALSE ) + return; + + tssi_m_dc = TssiLinear0 - ((pTxALCData->TSSI_USE_HVGA == 1) ? pTxALCData->TssiDC0_HVGA : pTxALCData->TssiDC0); + + + tssi_db = lin2dBd(tssi_m_dc); + + if ( ch <= 4 ) + tssi_offset = pTxALCData->MT7601_TSSI_OFFSET[0]; + else if ( ch >= 9 ) + tssi_offset = pTxALCData->MT7601_TSSI_OFFSET[2]; + else + tssi_offset = pTxALCData->MT7601_TSSI_OFFSET[1]; + + if(pTxALCData->TSSI_USE_HVGA == 1) + tssi_db -= pTxALCData->TSSI_DBOFFSET_HVGA; + + CurrentPower = (pTxALCData->TssiSlope*tssi_db) + (tssi_offset << 9); + + DBGPRINT(RT_DEBUG_TRACE, ("CurrentPower: %d\n", CurrentPower)); + + PowerDiff = TargetPower - CurrentPower; + + DBGPRINT(RT_DEBUG_TRACE, ("PowerDiff: %d\n", PowerDiff)); + + if((TssiLinear0 > 126) && ( PowerDiff > 0)) // upper saturation + { + DBGPRINT(RT_DEBUG_ERROR, ("%s :: upper saturation.\n", __FUNCTION__)); + PowerDiff = 0; + } + else + { + //if(((TssiLinear0 -TssiDC0) < 1) && (PowerDiff < 0)) // lower saturation + if(((TssiLinear0 -((pTxALCData->TSSI_USE_HVGA == 1) ? pTxALCData->TssiDC0_HVGA : pTxALCData->TssiDC0)) < 1) && (PowerDiff < 0)) // lower saturation + { + DBGPRINT(RT_DEBUG_ERROR, ("%s :: lower saturation.\n", __FUNCTION__)); + PowerDiff = 0; + } + } + + if( ((pTxALCData->PowerDiffPre ^ PowerDiff) < 0 ) + && ( (PowerDiff < 4096) && (PowerDiff > -4096)) // +- 0.5 + && ( (pTxALCData->PowerDiffPre < 4096) && (pTxALCData->PowerDiffPre > -4096))) // +- 0.5 + { + if((PowerDiff > 0) && ((PowerDiff + pTxALCData->PowerDiffPre) >= 0)) + PowerDiff = 0; + else if((PowerDiff < 0) && ((PowerDiff + pTxALCData->PowerDiffPre) < 0)) + PowerDiff = 0; + else + pTxALCData->PowerDiffPre = PowerDiff; + } + else + { + pTxALCData->PowerDiffPre = PowerDiff; + } + + PowerDiff = PowerDiff + ((PowerDiff>0)?2048:-2048); + PowerDiff = PowerDiff / 4096; + + DBGPRINT(RT_DEBUG_TRACE, ("final PowerDiff: %d(0x%x)\n", PowerDiff, PowerDiff)); + + RTMP_IO_READ32(pAd, TX_ALC_CFG_1, &value); + CurrentPower = (value & 0x3F); + CurrentPower = CurrentPower > 0x1F ? CurrentPower - 0x40 : CurrentPower; + PowerDiff += CurrentPower; + if ( PowerDiff > 31 ) + PowerDiff = 31; + if ( PowerDiff < -32 ) + PowerDiff = -32; + //PowerDiff = PowerDiff + (value & 0x3F); + value = (value & ~0x3F) | (PowerDiff & 0x3F); + RTMP_IO_WRITE32(pAd, TX_ALC_CFG_1, value); + DBGPRINT(RT_DEBUG_TRACE, ("MAC 13b4: 0x%x\n", value)); + + //MT7601AsicTemperatureCompensation(pAd); + + if ( RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_MCU_SEND_IN_BAND_CMD) ) + { + MT7601_EnableTSSI(pAd); + pTxALCData->TssiTriggered = 1; + } + + } + + +} +#endif /* RTMP_INTERNAL_TX_ALC */ + + +VOID MT7601ATEAsicTemperatureCompensation( + IN PRTMP_ADAPTER pAd) +{ + RTMP_CHIP_CAP *pChipCap = &pAd->chipCap; + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->OneSecPeriodicRound % 4 == 0) + { +#ifdef RTMP_INTERNAL_TX_ALC + if ( pAd->TxPowerCtrl.bInternalTxALC == FALSE ) +#endif /* RTMP_INTERNAL_TX_ALC */ + { + MT7601_Read_Temperature(pAd, &pChipCap->CurrentTemperBbpR49); + } + + MT7601AsicTemperatureCompensation(pAd, FALSE); + } +} + +/* + ========================================================================== + Description: + Gives CCK TX rate 2 more dB TX power. + This routine works only in LINK UP in INFRASTRUCTURE mode. + + calculate desired Tx power in RF R3.Tx0~5, should consider - + 0. if current radio is a noisy environment (pAd->DrsCounters.fNoisyEnvironment) + 1. TxPowerPercentage + 2. auto calibration based on TSSI feedback + 3. extra 2 db for CCK + 4. -10 db upon very-short distance (AvgRSSI >= -40db) to AP + + NOTE: Since this routine requires the value of (pAd->DrsCounters.fNoisyEnvironment), + it should be called AFTER MlmeDynamicTxRatSwitching() + ========================================================================== + */ + +VOID MT7601ATEAsicAdjustTxPower( + IN PRTMP_ADAPTER pAd) +{ + CHAR DeltaPwr = 0; + CHAR TxAgcCompensate = 0; + CHAR DeltaPowerByBbpR1 = 0; + CHAR TotalDeltaPower = 0; /* (non-positive number) including the transmit power controlled by the MAC and the BBP R1 */ + CONFIGURATION_OF_TX_POWER_CONTROL_OVER_MAC CfgOfTxPwrCtrlOverMAC = {0}; + + +#ifdef RTMP_INTERNAL_TX_ALC + /* Get temperature compensation delta power value */ + MT7601ATEAsicTxAlcGetAutoAgcOffset(pAd); +#endif /* RTMP_INTERNAL_TX_ALC */ + +} + + +/* +========================================================================== + Description: + Set MT7601 ATE RF central frequency offset + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT MT7601_Set_ATE_TX_FREQ_OFFSET_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR RFFreqOffset = 0; + ULONG R4 = 0; + UCHAR RFValue = 0; + UCHAR PreRFValue = 0; + RFFreqOffset = simple_strtol(arg, 0, 10); + + pAd->ate.RFFreqOffset = RFFreqOffset; + + if ( IS_MT7601(pAd)) + { + rlt_rf_write(pAd, RF_BANK0, RF_R12, pAd->ate.RFFreqOffset); + + rlt_rf_write(pAd, RF_BANK0, RF_R04, 0x0A); + rlt_rf_write(pAd, RF_BANK0, RF_R05, 0x20); + rlt_rf_read(pAd, RF_BANK0, RF_R04, &RFValue); + RFValue = RFValue | 0x80; /* vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration. */ + rlt_rf_write(pAd, RF_BANK0, RF_R04, RFValue); + RTMPusecDelay(2000); + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_FREQOFFSET_Proc (RFFreqOffset = %d)\n", pAd->ate.RFFreqOffset)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_FREQOFFSET_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +VOID MT7601ATERxVGAInit( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR R66 = 0x14; + CHAR LNAGain = GET_LNA_GAIN(pAd); + + //RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x14); + + ATEBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL); + + + return; +} + + +VOID MT7601ATEAsicSetTxRxPath( + IN PRTMP_ADAPTER pAd) +{ + UCHAR BbpValue = 0; + + AsicSetRxAnt(pAd, pAd->ate.RxAntennaSel); +} + + +struct _ATE_CHIP_STRUCT MT7601ATE = +{ + /* functions */ + .ChannelSwitch = MT7601ATEAsicSwitchChannel, + .TxPwrHandler = MT7601ATETxPwrHandler, + .TssiCalibration = NULL, + .ExtendedTssiCalibration = NULL /* RT5572_ATETssiCalibrationExtend */, + .RxVGAInit = MT7601ATERxVGAInit, + .AsicSetTxRxPath = MT7601ATEAsicSetTxRxPath, + .AdjustTxPower = MT7601ATEAsicAdjustTxPower, + //.AsicExtraPowerOverMAC = DefaultATEAsicExtraPowerOverMAC, + .Set_BW_Proc = MT7601_Set_ATE_TX_BW_Proc, + .Set_FREQ_OFFSET_Proc = MT7601_Set_ATE_TX_FREQ_OFFSET_Proc, + .TemperCompensation = MT7601ATEAsicTemperatureCompensation, + + /* variables */ + .maxTxPwrCnt = 5, + .bBBPStoreTXCARR = FALSE, + .bBBPStoreTXCARRSUPP = FALSE, + .bBBPStoreTXCONT = FALSE, + .bBBPLoadATESTOP = FALSE,/* ralink debug */ +}; + + +#endif /* MT7601 */ + diff --git a/cleopatre/devkit/mt7601udrv/ate/common/ate_usb.c b/cleopatre/devkit/mt7601udrv/ate/common/ate_usb.c new file mode 100644 index 0000000000..a7cd163ed1 --- /dev/null +++ b/cleopatre/devkit/mt7601udrv/ate/common/ate_usb.c @@ -0,0 +1,627 @@ +/* + *************************************************************************** + * Ralink Tech Inc. + * 4F, No. 2 Technology 5th Rd. + * Science-based Industrial Park + * Hsin-chu, Taiwan, R.O.C. + * + * (c) Copyright 2002-2006, Ralink Technology, Inc. + * + * All rights reserved. Ralink's source code is an unpublished work and the + * use of a copyright notice does not imply otherwise. This source code + * contains confidential trade secret material of Ralink Tech. Any attemp + * or participation in deciphering, decoding, reverse engineering or in any + * way altering the source code is stricitly prohibited, unless the prior + * written consent of Ralink Technology, Inc. is obtained. + *************************************************************************** + + Module Name: + ate_usb.c + + Abstract: + + Revision History: + Who When What + -------- ---------- ---------------------------------------------- + Name Date Modification logs +*/ + +#ifdef RTMP_MAC_USB + +#include "rt_config.h" + +extern UCHAR EpToQueue[]; +/* 802.11 MAC Header, Type:Data, Length:24bytes + 6 bytes QOS/HTC + 2 bytes padding */ +extern UCHAR TemplateFrame[32]; + +INT TxDmaBusy( + IN PRTMP_ADAPTER pAd) +{ + INT result; + USB_DMA_CFG_STRUC UsbCfg; + + RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); /* disable DMA */ + result = (UsbCfg.field.TxBusy) ? TRUE : FALSE; + + return result; +} + + +INT RxDmaBusy( + IN PRTMP_ADAPTER pAd) +{ + INT result; + USB_DMA_CFG_STRUC UsbCfg; + + RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); /* disable DMA */ + result = (UsbCfg.field.RxBusy) ? TRUE : FALSE; + + return result; +} + + +VOID RtmpDmaEnable( + IN PRTMP_ADAPTER pAd, + IN INT Enable) +{ + BOOLEAN value; + ULONG WaitCnt; + USB_DMA_CFG_STRUC UsbCfg; + + value = Enable > 0 ? 1 : 0; + + /* check DMA is in busy mode. */ + WaitCnt = 0; + + while (TxDmaBusy(pAd) || RxDmaBusy(pAd)) + { + RTMPusecDelay(10); + if (WaitCnt++ > 100) + break; + } + RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); /* disable DMA */ + UsbCfg.field.TxBulkEn = value; + UsbCfg.field.RxBulkEn = value; + RTMP_IO_WRITE32(pAd, USB_DMA_CFG, UsbCfg.word); /* abort all TX rings */ + RtmpOsMsDelay(5); + + return; +} + + +static VOID ATEWriteTxWI( + IN PRTMP_ADAPTER pAd, + IN TXWI_STRUC *pTxWI, + IN BOOLEAN FRAG, + IN BOOLEAN InsTimestamp, + IN BOOLEAN AMPDU, + IN BOOLEAN Ack, + IN BOOLEAN NSeq, /* HW new a sequence. */ + IN UCHAR BASize, + IN UCHAR WCID, + IN ULONG Length, + IN UCHAR PID, + IN UCHAR MIMOps, + IN UCHAR Txopmode, + IN BOOLEAN CfAck, + IN HTTRANSMIT_SETTING Transmit) +{ + OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED); + pTxWI->TxWIFRAG= FRAG; + pTxWI->TxWITS= InsTimestamp; + pTxWI->TxWIAMPDU = AMPDU; + + pTxWI->TxWIMIMOps = PWR_ACTIVE; + pTxWI->TxWIMpduDensity = 4; + pTxWI->TxWIACK = Ack; + pTxWI->TxWITXOP = Txopmode; + pTxWI->TxWINSEQ = NSeq; + //pTxWI->TxWIBAWinSize = BASize; + pTxWI->TxWIBAWinSize = 21; + + pTxWI->TxWIWirelessCliID = WCID; + pTxWI->TxWIMPDUByteCnt = Length; + //pTxWI->TxWIPacketId = PID; + pTxWI->TxWIPacketId = 7; + + pTxWI->TxWIBW = Transmit.field.BW; + pTxWI->TxWIShortGI = Transmit.field.ShortGI; + pTxWI->TxWISTBC= Transmit.field.STBC; + + pTxWI->TxWIMCS = Transmit.field.MCS; + pTxWI->TxWIPHYMODE= Transmit.field.MODE; + pTxWI->TxWICFACK = CfAck; + + return; +} + + +/* +======================================================================== + Routine Description: + Write TxInfo for ATE mode. + + Return Value: + None +======================================================================== +*/ +static VOID ATEWriteTxInfo( + IN PRTMP_ADAPTER pAd, + IN TXINFO_STRUC *pTxInfo, + IN USHORT USBDMApktLen, + IN BOOLEAN bWiv, + IN UCHAR QueueSel, + IN UCHAR NextValid, + IN UCHAR TxBurst) +{ +#ifdef RLT_MAC + struct _TXINFO_NMAC_PKT *nmac_info; + + nmac_info = (struct _TXINFO_NMAC_PKT *)pTxInfo; + nmac_info->pkt_80211 = 1; + nmac_info->info_type = 0; + nmac_info->d_port = 0; + nmac_info->cso = 0; + nmac_info->tso = 0; +#endif /* RLT_MAC */ + +#ifdef RTMP_MAC + /* ATE doesn't support checksum offload. */ + pTxInfo->TxInfoCSO = 1; + pTxInfo->TxInfoUSO = 0; + pTxInfo->TxInfoTCPOffset = 0; + pTxInfo->TxInfoIPOffset = 0; +#endif /* RTMP_MAC */ + + pTxInfo->TxInfoPktLen = USBDMApktLen; + pTxInfo->TxInfoQSEL = QueueSel; + + if (QueueSel != FIFO_EDCA) + DBGPRINT(RT_DEBUG_TRACE, ("======= QueueSel != FIFO_EDCA =======\n")); + + pTxInfo->TxInfoUDMANextVld = NextValid; + pTxInfo->TxInfoUDMATxburst = TxBurst; + pTxInfo->TxInfoWIV = bWiv; +#ifndef USB_BULK_BUF_ALIGMENT + pTxInfo->TxInfoSwLstRnd = 0; +#else + pTxInfo->bFragLasAlignmentsectiontRound = 0; +#endif /* USB_BULK_BUF_ALIGMENT */ + + return; +} + + +INT ATESetUpFrame( + IN PRTMP_ADAPTER pAd, + IN UINT32 TxIdx) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT pos = 0; + PTX_CONTEXT pNullContext; + PUCHAR pDest; + HTTRANSMIT_SETTING TxHTPhyMode; + TXWI_STRUC *pTxWI; + TXINFO_STRUC *pTxInfo; + UINT32 TransferBufferLength, OrgBufferLength = 0; + UCHAR padLen = 0; + UINT8 TXWISize = pAd->chipCap.TXWISize; +#ifdef RALINK_QA + PHEADER_802_11 pHeader80211 = NULL; +#endif /* RALINK_QA */ + + if ((RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) || + (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)) || + (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) || + (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) + { + return -1; + } + + /* We always use QID_AC_BE and FIFO_EDCA in ATE mode. */ + + pNullContext = &(pAd->NullContext[0]); + ASSERT(pNullContext != NULL); + + if (pNullContext->InUse == FALSE) + { + /* set the in use bit */ + pNullContext->InUse = TRUE; + NdisZeroMemory(&(pAd->NullFrame), sizeof(HEADER_802_11)); + + /* fill 802.11 header */ +#ifdef RALINK_QA + if (pATEInfo->bQATxStart == TRUE) + { + pHeader80211 = NdisMoveMemory(&(pAd->NullFrame), + pATEInfo->Header, pATEInfo->HLen); + } + else +#endif /* RALINK_QA */ + { + NdisMoveMemory(&(pAd->NullFrame), TemplateFrame, + sizeof(HEADER_802_11)); + } + +#ifdef RT_BIG_ENDIAN + RTMPFrameEndianChange(pAd, (PUCHAR)&(pAd->NullFrame), DIR_READ, FALSE); +#endif /* RT_BIG_ENDIAN */ + +#ifdef RALINK_QA + if (pATEInfo->bQATxStart == TRUE) + { + /* modify sequence number... */ + if (pATEInfo->TxDoneCount == 0) + { + pATEInfo->seq = pHeader80211->Sequence; + } + else + { + pHeader80211->Sequence = ++pATEInfo->seq; + } + /* We already got all the address fields from QA GUI. */ + } + else +#endif /* RALINK_QA */ + { + COPY_MAC_ADDR(pAd->NullFrame.Addr1, pATEInfo->Addr1); + COPY_MAC_ADDR(pAd->NullFrame.Addr2, pATEInfo->Addr2); + COPY_MAC_ADDR(pAd->NullFrame.Addr3, pATEInfo->Addr3); + } + + RTMPZeroMemory(&pAd->NullContext[0].TransferBuffer->field.WirelessPacket[0], TX_BUFFER_NORMSIZE); + pTxInfo = (TXINFO_STRUC *)&pAd->NullContext[0].TransferBuffer->field.WirelessPacket[0]; + +#ifdef RALINK_QA + if (pATEInfo->bQATxStart == TRUE) + { + /* Avoid to exceed the range of WirelessPacket[]. */ + ASSERT(pATEInfo->TxInfo.TxInfoPktLen <= (MAX_FRAME_SIZE - 34/* == 2312 */)); + NdisMoveMemory(pTxInfo, &(pATEInfo->TxInfo), sizeof(pATEInfo->TxInfo)); + } + else +#endif /* RALINK_QA */ + { + /* Avoid to exceed the range of WirelessPacket[]. */ + ASSERT(pATEInfo->TxLength <= (MAX_FRAME_SIZE - 34/* == 2312 */)); + + /* pTxInfo->TxInfoPktLen will be updated to include padding later */ + ATEWriteTxInfo(pAd, pTxInfo, (USHORT)(TXWISize + pATEInfo->TxLength) + , TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE); + pTxInfo->TxInfoQSEL = FIFO_EDCA; + } + + pTxWI = (TXWI_STRUC *)&pAd->NullContext[0].TransferBuffer->field.WirelessPacket[TXINFO_SIZE]; + + /* fill TxWI */ + if (pATEInfo->bQATxStart == TRUE) + { + TxHTPhyMode.field.BW = pATEInfo->TxWI.TxWIBW; + TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.TxWIShortGI; + TxHTPhyMode.field.STBC = pATEInfo->TxWI.TxWISTBC; + TxHTPhyMode.field.MCS = pATEInfo->TxWI.TxWIMCS; + TxHTPhyMode.field.MODE = pATEInfo->TxWI.TxWIPHYMODE; + ATEWriteTxWI(pAd, pTxWI, pATEInfo->TxWI.TxWIFRAG, pATEInfo->TxWI.TxWITS, + pATEInfo->TxWI.TxWIAMPDU, pATEInfo->TxWI.TxWIACK, pATEInfo->TxWI.TxWINSEQ, + pATEInfo->TxWI.TxWIBAWinSize, BSSID_WCID, + pATEInfo->TxWI.TxWIMPDUByteCnt/* include 802.11 header */, + pATEInfo->TxWI.TxWIPacketId, + 0, pATEInfo->TxWI.TxWITXOP/*IFS_HTTXOP*/, pATEInfo->TxWI.TxWICFACK + /*FALSE*/, TxHTPhyMode); + } + else + { + TxHTPhyMode.field.BW = pATEInfo->TxWI.TxWIBW; + TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.TxWIShortGI; + TxHTPhyMode.field.STBC = 0; + TxHTPhyMode.field.MCS = pATEInfo->TxWI.TxWIMCS; + TxHTPhyMode.field.MODE = pATEInfo->TxWI.TxWIPHYMODE; + + ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE + /* No ack required. */, FALSE, 0, BSSID_WCID, pATEInfo->TxLength, + 0, 0, IFS_HTTXOP, FALSE, TxHTPhyMode); + } + + hex_dump("ATE", pAd->NullContext[0].TransferBuffer->field.WirelessPacket, 24); + dump_txinfo(pAd, pTxInfo); + dumpTxWI(pAd, pTxWI); + + + RTMPMoveMemory(&pAd->NullContext[0].TransferBuffer->field.WirelessPacket[TXINFO_SIZE + TXWISize], + &pAd->NullFrame, sizeof(HEADER_802_11)); + + pDest = &(pAd->NullContext[0].TransferBuffer->field.WirelessPacket[TXINFO_SIZE + TXWISize + sizeof(HEADER_802_11)]); + + /* prepare frame payload */ +#ifdef RALINK_QA + if (pATEInfo->bQATxStart == TRUE) + { + /* copy the pattern one by one to the frame payload */ + if ((pATEInfo->PLen != 0) && (pATEInfo->DLen != 0)) + { + for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen) + { + RTMPMoveMemory(pDest, pATEInfo->Pattern, pATEInfo->PLen); + pDest += pATEInfo->PLen; + } + } + TransferBufferLength = TXINFO_SIZE + TXWISize + pATEInfo->TxWI.TxWIMPDUByteCnt; + } + else +#endif /* RALINK_QA */ + { + for (pos = 0; pos < (pATEInfo->TxLength - sizeof(HEADER_802_11)); pos++) + { + /* default payload is 0xA5 */ + *pDest = pATEInfo->Payload; + pDest += 1; + } + TransferBufferLength = TXINFO_SIZE + TXWISize + pATEInfo->TxLength; + } + + OrgBufferLength = TransferBufferLength; + TransferBufferLength = (TransferBufferLength + 3) & (~3); + + /* Always add 4 extra bytes at every packet. */ + padLen = TransferBufferLength - OrgBufferLength + 4;/* 4 == last packet padding */ + + /* + RTMP_PKT_TAIL_PADDING == 11. + [11 == 3(max 4 byte padding) + 4(last packet padding) + 4(MaxBulkOutsize align padding)] + */ + ASSERT((padLen <= (RTMP_PKT_TAIL_PADDING - 4/* 4 == MaxBulkOutsize alignment padding */))); + + /* Now memzero all extra padding bytes. */ + NdisZeroMemory(pDest, padLen); + pDest += padLen; + + /* Update pTxInfo->TxInfoPktLen to include padding. */ + pTxInfo->TxInfoPktLen = TransferBufferLength - TXINFO_SIZE; + + TransferBufferLength += 4; + + /* If TransferBufferLength is multiple of 64, add extra 4 bytes again. */ + if ((TransferBufferLength % pAd->BulkOutMaxPacketSize) == 0) + { + NdisZeroMemory(pDest, 4); + TransferBufferLength += 4; + } + + /* Fill out frame length information for global Bulk out arbitor. */ + pAd->NullContext[0].BulkOutSize = TransferBufferLength; + } + +#ifdef RT_BIG_ENDIAN + RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI); + RTMPFrameEndianChange(pAd, (((PUCHAR)pTxInfo) + TXWISize + TXINFO_SIZE), DIR_WRITE, FALSE); + RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO); +#endif /* RT_BIG_ENDIAN */ + + hex_dump("ATE TX", &pAd->NullContext[0].TransferBuffer->field.WirelessPacket[0], TXWISize + TXINFO_SIZE); + + return 0; +} + + +/* +======================================================================== + + Routine Description: + + Arguments: + + Return Value: + None + + Note: + +======================================================================== +*/ +VOID ATE_RTUSBBulkOutDataPacket( + IN PRTMP_ADAPTER pAd, + IN UCHAR BulkOutPipeId) +{ + PTX_CONTEXT pNullContext = &(pAd->NullContext[0]); + PURB pUrb; + INT ret = 0; + ULONG IrqFlags; + + + ASSERT(BulkOutPipeId == 0); + + /* Build up the frame first. */ + BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags); + + if (pAd->BulkOutPending[BulkOutPipeId] == TRUE) + { + BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags); + return; + } + + pAd->BulkOutPending[BulkOutPipeId] = TRUE; + BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags); + + /* Increase total transmit byte counter. */ + pAd->RalinkCounters.OneSecTransmittedByteCount += pNullContext->BulkOutSize; + pAd->RalinkCounters.TransmittedByteCount += pNullContext->BulkOutSize; + + /* Clear ATE frame bulk out flag. */ + RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE); + + /* Init Tx context descriptor. */ + pNullContext->IRPPending = TRUE; + RTUSBInitTxDesc(pAd, pNullContext, BulkOutPipeId, + (usb_complete_t)RTUSBBulkOutDataPacketComplete); + pUrb = pNullContext->pUrb; + + if ((ret = RTUSB_SUBMIT_URB(pUrb))!=0) + { + DBGPRINT_ERR(("ATE_RTUSBBulkOutDataPacket: Submit Tx URB failed %d\n", ret)); + return; + } + + pAd->BulkOutReq++; + + return; +} + + +/* +======================================================================== + + Routine Description: + + Arguments: + + Return Value: + None + + Note: + +======================================================================== +*/ +VOID ATE_RTUSBCancelPendingBulkInIRP( + IN PRTMP_ADAPTER pAd) +{ + PRX_CONTEXT pRxContext = NULL; + UINT rx_ring_index; + + DBGPRINT(RT_DEBUG_TRACE, ("--->ATE_RTUSBCancelPendingBulkInIRP\n")); + + for (rx_ring_index = 0; rx_ring_index < (RX_RING_SIZE); rx_ring_index++) + { + pRxContext = &(pAd->RxContext[rx_ring_index]); + + if (pRxContext->IRPPending == TRUE) + { + RTUSB_UNLINK_URB(pRxContext->pUrb); + pRxContext->IRPPending = FALSE; + pRxContext->InUse = FALSE; + } + } + + DBGPRINT(RT_DEBUG_TRACE, ("<---ATE_RTUSBCancelPendingBulkInIRP\n")); + + return; +} + + +/* +======================================================================== + + Routine Description: + + Arguments: + + Return Value: + None + + Note: + +======================================================================== +*/ +VOID ATEResetBulkIn( + IN PRTMP_ADAPTER pAd) +{ + if ((pAd->PendingRx > 0) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) + { + DBGPRINT_ERR(("ATE : BulkIn IRP Pending!!!\n")); + ATE_RTUSBCancelPendingBulkInIRP(pAd); + RtmpOsMsDelay(100); + pAd->PendingRx = 0; + } + + return; +} + + +/* +======================================================================== + + Routine Description: + + Arguments: + + Return Value: + + Note: + +======================================================================== +*/ +INT ATEResetBulkOut( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + PTX_CONTEXT pNullContext = &(pAd->NullContext); + INT ret=0; + + pNullContext->IRPPending = TRUE; + + /* + If driver is still in ATE TXFRAME mode, + keep on transmitting ATE frames. + */ + DBGPRINT(RT_DEBUG_TRACE, ("pATEInfo->Mode == %d\npAd->ContinBulkOut == %d\npAd->BulkOutRemained == %d\n", + pATEInfo->Mode, pAd->ContinBulkOut, atomic_read(&pAd->BulkOutRemained))); + + if ((pATEInfo->Mode == ATE_TXFRAME) && ((pAd->ContinBulkOut == TRUE) || (atomic_read(&pAd->BulkOutRemained) > 0))) + { + DBGPRINT(RT_DEBUG_TRACE, ("After CMDTHREAD_RESET_BULK_OUT, continue to bulk out frames !\n")); + + /* Init Tx context descriptor. */ + RTUSBInitTxDesc(pAd, pNullContext, 0/* pAd->bulkResetPipeid */, (usb_complete_t)RTUSBBulkOutDataPacketComplete); + + if ((ret = RTUSB_SUBMIT_URB(pNullContext->pUrb))!=0) + { + DBGPRINT_ERR(("ATE_RTUSBBulkOutDataPacket: Submit Tx URB failed %d\n", ret)); + } + + pAd->BulkOutReq++; + } + + return ret; +} + + +/* +======================================================================== + + Routine Description: + + Arguments: + + Return Value: + + IRQL = + + Note: + +======================================================================== +*/ +VOID RTUSBRejectPendingPackets( + IN PRTMP_ADAPTER pAd) +{ + UCHAR Index; + PQUEUE_ENTRY pEntry; + PNDIS_PACKET pPacket; + PQUEUE_HEADER pQueue; + + + for (Index = 0; Index < 4; Index++) + { + NdisAcquireSpinLock(&pAd->TxSwQueueLock[Index]); + while (pAd->TxSwQueue[Index].Head != NULL) + { + pQueue = (PQUEUE_HEADER) &(pAd->TxSwQueue[Index]); + pEntry = RemoveHeadQueue(pQueue); + pPacket = QUEUE_ENTRY_TO_PACKET(pEntry); + RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE); + } + NdisReleaseSpinLock(&pAd->TxSwQueueLock[Index]); + + } + +} + +#endif /* RTMP_MAC_USB */ + diff --git a/cleopatre/devkit/mt7601udrv/ate/common/rt_ate.c b/cleopatre/devkit/mt7601udrv/ate/common/rt_ate.c new file mode 100644 index 0000000000..fb4af7843b --- /dev/null +++ b/cleopatre/devkit/mt7601udrv/ate/common/rt_ate.c @@ -0,0 +1,6298 @@ +/* + *************************************************************************** + * Ralink Tech Inc. + * 4F, No. 2 Technology 5th Rd. + * Science-based Industrial Park + * Hsin-chu, Taiwan, R.O.C. + * + * (c) Copyright 2002-2010, Ralink Technology, Inc. + * + * All rights reserved. Ralink's source code is an unpublished work and the + * use of a copyright notice does not imply otherwise. This source code + * contains confidential trade secret material of Ralink Tech. Any attemp + * or participation in deciphering, decoding, reverse engineering or in any + * way altering the source code is stricitly prohibited, unless the prior + * written consent of Ralink Technology, Inc. is obtained. + *************************************************************************** + + Module Name: + rt_ate.c + + Abstract: + + Revision History: + Who When What + -------- ---------- ---------------------------------------------- + Name Date Modification logs +*/ +#include "rt_config.h" + +#define ATE_BBP_REG_NUM 168 +UCHAR restore_BBP[ATE_BBP_REG_NUM]={0}; + +/* 802.11 MAC Header, Type:Data, Length:24bytes + 6 bytes QOS/HTC + 2 bytes padding */ +UCHAR TemplateFrame[32] = {0x08,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x00,0xAA,0xBB,0x12,0x34,0x56,0x00,0x11,0x22,0xAA,0xBB,0xCC,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; + +extern FREQUENCY_ITEM *FreqItems3020; +extern UCHAR NUM_OF_3020_CHNL; + +static UINT32 Default_TX_PIN_CFG; +#define RA_TX_PIN_CFG 0x1328 +#define TXCONT_TX_PIN_CFG_A 0x040C0050 +#define TXCONT_TX_PIN_CFG_G 0x080C00A0 + +#define ATE_TASK_EXEC_INTV 100 // 1000 -> 100 + +static CHAR CCKRateTable[] = {0, 1, 2, 3, 8, 9, 10, 11, -1}; /* CCK Mode. */ +static CHAR OFDMRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, -1}; /* OFDM Mode. */ +#ifdef DOT11N_SS3_SUPPORT +static CHAR HTMIXRateTable3T3R[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, -1}; /* HT Mix Mode for 3*3. */ +#endif /* DOT11N_SS3_SUPPORT */ +static CHAR HTMIXRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}; /* HT Mix Mode. */ + +#ifdef RTMP_INTERNAL_TX_ALC + +/* The desired TSSI over CCK */ +extern CHAR desiredTSSIOverCCK[4]; + +/* The desired TSSI over OFDM */ +extern CHAR desiredTSSIOverOFDM[8]; + +/* The desired TSSI over HT */ +extern CHAR desiredTSSIOverHT[8]; + +/* The desired TSSI over HT using STBC */ +extern CHAR desiredTSSIOverHTUsingSTBC[8]; + +/* The Tx power tuning entry*/ +extern TX_POWER_TUNING_ENTRY_STRUCT TxPowerTuningTable[]; + +/* +========================================================================== + Description: + Get the desired TSSI based on ATE setting. + + Arguments: + pAd + + Return Value: + The desired TSSI +========================================================================== + */ + #ifdef MT7601 +CHAR ATEGetDesiredTSSI( + IN PRTMP_ADAPTER pAd) +{ + DBGPRINT(RT_DEBUG_ERROR, ("%s::Currently not support singledriver.\n", __FUNCTION__)); + return 0; + + } + #else +CHAR ATEGetDesiredTSSI( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR desiredTSSI = 0; + UCHAR MCS = 0; + UCHAR MaxMCS = 7; + + MCS = (UCHAR)(pATEInfo->TxWI.TxWIMCS); + + if (pATEInfo->TxWI.TxWIPHYMODE == MODE_CCK) + { + if (MCS > 3) /* boundary verification */ + { + DBGPRINT_ERR(("%s: incorrect MCS: MCS = %d\n", + __FUNCTION__, + MCS)); + + MCS = 0; + } + + desiredTSSI = desiredTSSIOverCCK[MCS]; + } + else if (pATEInfo->TxWI.TxWIPHYMODE == MODE_OFDM) + { + if (MCS > 7) /* boundary verification */ + { + DBGPRINT_ERR(("%s: incorrect MCS: MCS = %d\n", + __FUNCTION__, + MCS)); + + MCS = 0; + } + + desiredTSSI = desiredTSSIOverOFDM[MCS]; + } + else if ((pATEInfo->TxWI.TxWIPHYMODE == MODE_HTMIX) || (pATEInfo->TxWI.TxWIPHYMODE == MODE_HTGREENFIELD)) + { + if (pATEInfo->TxWI.TxWISTBC == STBC_NONE) + { + if (MCS > MaxMCS) /* boundary verification */ + { + DBGPRINT_ERR(("%s: incorrect MCS: MCS = %d\n", + __FUNCTION__, + MCS)); + + MCS = 0; + } + + desiredTSSI = desiredTSSIOverHT[MCS]; + } + else + { + if (MCS > MaxMCS) /* boundary verification */ + { + DBGPRINT_ERR(("%s: incorrect MCS: MCS = %d\n", + __FUNCTION__, + MCS)); + + MCS = 0; + } + + desiredTSSI = desiredTSSIOverHTUsingSTBC[MCS]; + } + + + /* + For HT BW40 MCS 7 with/without STBC configuration, + the desired TSSI value should subtract one from the formula. + */ + if ((pATEInfo->TxWI.TxWIBW == BW_40) && (MCS == MCS_7)) + { + desiredTSSI -= 1; + } + } + + DBGPRINT(RT_DEBUG_TRACE, ("%s: desiredTSSI = %d, Latest Tx setting: MODE = %d, MCS = %d, STBC = %d\n", + __FUNCTION__, + desiredTSSI, + pATEInfo->TxWI.TxWIPHYMODE, + pATEInfo->TxWI.TxWIMCS, + pATEInfo->TxWI.TxWISTBC)); + + + return desiredTSSI; +} +#endif /* MT7601 */ + +#endif /* RTMP_INTERNAL_TX_ALC */ + + +/* +========================================================================== + Description: + Gives CCK TX rate 2 more dB TX power. + This routine works only in ATE mode. + + calculate desired Tx power in RF R3.Tx0~5, should consider - + 0. TxPowerPercentage + 1. auto calibration based on TSSI feedback + 2. extra 2 db for CCK + 3. -10 db upon very-short distance (AvgRSSI >= -40db) to AP + +========================================================================== +*/ +VOID DefaultATEAsicAdjustTxPower( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + PATE_CHIP_STRUCT pChipStruct = pATEInfo->pChipStruct; + INT index = 0, inner_index = 0, maxTxPwrCnt; + CHAR DeltaPwr = 0; + BOOLEAN bAutoTxAgc = FALSE; + UCHAR TssiRef, *pTssiMinusBoundary, *pTssiPlusBoundary, TxAgcStep; + UCHAR BbpR49 = 0, idx; + PCHAR pTxAgcCompensate; + ULONG TxPwr[9]; /* NOTE: the TxPwr array size should be the maxima value of all supported chipset!!!! */ + CHAR Value; +#ifdef RTMP_INTERNAL_TX_ALC + /* (non-positive number) including the transmit power controlled by the MAC and the BBP R1 */ + CHAR TotalDeltaPower = 0; + UCHAR desiredTSSI = 0, currentTSSI = 0; + const TX_POWER_TUNING_ENTRY_STRUCT *TxPowerTuningTable = pAd->chipCap.TxPowerTuningTable_2G; + PTX_POWER_TUNING_ENTRY_STRUCT pTxPowerTuningEntry = NULL; + UCHAR RFValue = 0, TmpValue = 0; +#endif /* RTMP_INTERNAL_TX_ALC */ + + maxTxPwrCnt = pChipStruct->maxTxPwrCnt; + + if (pATEInfo->TxWI.TxWIBW == BW_40) + { + if (pATEInfo->Channel > 14) + { + for (index =0 ; index < maxTxPwrCnt; index ++) + { + TxPwr[index] = pAd->Tx40MPwrCfgABand[index]; + } + } + else + { + for (index =0 ; index < maxTxPwrCnt; index ++) + { + TxPwr[index] = pAd->Tx40MPwrCfgGBand[index]; + } + } + } + else + { + if (pATEInfo->Channel > 14) + { + for (index =0 ; index < maxTxPwrCnt; index ++) + { + TxPwr[index] = pAd->Tx20MPwrCfgABand[index]; + } + } + else + { + for (index =0 ; index < maxTxPwrCnt; index ++) + { + TxPwr[index] = pAd->Tx20MPwrCfgGBand[index]; + } + } + } + +#ifdef RTMP_INTERNAL_TX_ALC + /* Locate the internal Tx ALC tuning entry */ + if (pAd->TxPowerCtrl.bInternalTxALC == TRUE) + { + { + desiredTSSI = ATEGetDesiredTSSI(pAd); + + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49); + + currentTSSI = BbpR49 & 0x1F; + + if (pAd->TxPowerCtrl.bExtendedTssiMode == TRUE) /* Per-channel TSSI */ + { + if ((pATEInfo->Channel >= 1) && (pATEInfo->Channel <= 14)) + { + DBGPRINT(RT_DEBUG_TRACE, ("%s: bExtendedTssiMode = %d, original desiredTSSI = %d, CentralChannel = %d, PerChTxPwrOffset = %d\n", + __FUNCTION__, + pAd->TxPowerCtrl.bExtendedTssiMode, + desiredTSSI, + pATEInfo->Channel, + pAd->TxPowerCtrl.PerChTxPwrOffset[pATEInfo->Channel])); + + desiredTSSI += pAd->TxPowerCtrl.PerChTxPwrOffset[pATEInfo->Channel]; + } + } + + if (desiredTSSI > 0x1F) + { + desiredTSSI = 0x1F; + } + + if (desiredTSSI > currentTSSI) + { + pAd->TxPowerCtrl.idxTxPowerTable++; + } + + if (desiredTSSI < currentTSSI) + { + pAd->TxPowerCtrl.idxTxPowerTable--; + } + + if (pAd->TxPowerCtrl.idxTxPowerTable < LOWERBOUND_TX_POWER_TUNING_ENTRY) + { + pAd->TxPowerCtrl.idxTxPowerTable = LOWERBOUND_TX_POWER_TUNING_ENTRY; + } + + if (pAd->TxPowerCtrl.idxTxPowerTable >= UPPERBOUND_TX_POWER_TUNING_ENTRY(pAd)) + { + pAd->TxPowerCtrl.idxTxPowerTable = UPPERBOUND_TX_POWER_TUNING_ENTRY(pAd); + } + + /* Valid pAd->TxPowerCtrl.idxTxPowerTable: -30 ~ 45 */ + pTxPowerTuningEntry = &TxPowerTuningTable[pAd->TxPowerCtrl.idxTxPowerTable + TX_POWER_TUNING_ENTRY_OFFSET]; /* zero-based array */ + pAd->TxPowerCtrl.RF_TX_ALC = pTxPowerTuningEntry->RF_TX_ALC; + pAd->TxPowerCtrl.MAC_PowerDelta = pTxPowerTuningEntry->MAC_PowerDelta; + + DBGPRINT(RT_DEBUG_TRACE, ("pAd->TxPowerCtrl.idxTxPowerTable = %d, pAd->TxPowerCtrl.RF_TX_ALC = %d, pAd->TxPowerCtrl.MAC_PowerDelta = %d\n", + pAd->TxPowerCtrl.idxTxPowerTable, pAd->TxPowerCtrl.RF_TX_ALC, pAd->TxPowerCtrl.MAC_PowerDelta )); + + /* Tx power adjustment over RF */ + /* In ATE mode, only adjust TX0_ALC by default. */ + if (IS_RT5350(pAd)) + { + DBGPRINT(RT_DEBUG_ERROR, ("MT7601 Bata driver not support RT30xxReadRFRegister() and RT30xxWriteRFRegister().\n")); + } + else if (IS_RT3352(pAd)) + { + DBGPRINT(RT_DEBUG_ERROR, ("MT7601 Bata driver not support RT30xxReadRFRegister() and RT30xxWriteRFRegister().\n")); + } + else + { + DBGPRINT(RT_DEBUG_ERROR, ("MT7601 Bata driver not support RT30xxReadRFRegister() and RT30xxWriteRFRegister().\n")); + } + + /* Tx power adjustment over MAC */ + TotalDeltaPower += pAd->TxPowerCtrl.MAC_PowerDelta; + + DBGPRINT(RT_DEBUG_TRACE, ("%s: desiredTSSI = %d, currentTSSI = %d, idxTxPowerTable = %d, {RF_TX_ALC = %d, MAC_PowerDelta = %d}\n", + __FUNCTION__, + desiredTSSI, + currentTSSI, + pAd->TxPowerCtrl.idxTxPowerTable, + pTxPowerTuningEntry->RF_TX_ALC, + pTxPowerTuningEntry->MAC_PowerDelta)); + } + } +#endif /* RTMP_INTERNAL_TX_ALC */ + + /* TX power compensation for temperature variation based on TSSI. */ + /* Do it per 4 seconds. */ + if (pATEInfo->OneSecPeriodicRound % 4 == 0) + { + if (pATEInfo->Channel <= 14) + { + /* bg channel */ + bAutoTxAgc = pAd->bAutoTxAgcG; + TssiRef = pAd->TssiRefG; + pTssiMinusBoundary = &pAd->TssiMinusBoundaryG[0]; + pTssiPlusBoundary = &pAd->TssiPlusBoundaryG[0]; + TxAgcStep = pAd->TxAgcStepG; + pTxAgcCompensate = &pAd->TxAgcCompensateG; + } + else + { + /* a channel */ + bAutoTxAgc = pAd->bAutoTxAgcA; + TssiRef = pAd->TssiRefA; + pTssiMinusBoundary = &pAd->TssiMinusBoundaryA[0]; + pTssiPlusBoundary = &pAd->TssiPlusBoundaryA[0]; + TxAgcStep = pAd->TxAgcStepA; + pTxAgcCompensate = &pAd->TxAgcCompensateA; + } + + if (bAutoTxAgc) + { + /* BbpR49 is unsigned char. */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49); + + /* (p) TssiPlusBoundaryG[0] = 0 = (m) TssiMinusBoundaryG[0] */ + /* compensate: +4 +3 +2 +1 0 -1 -2 -3 -4 * steps */ + /* step value is defined in pAd->TxAgcStepG for tx power value */ + + /* [4]+1+[4] p4 p3 p2 p1 o1 m1 m2 m3 m4 */ + /* ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0 + above value are examined in mass factory production */ + /* [4] [3] [2] [1] [0] [1] [2] [3] [4] */ + + /* plus is 0x10 ~ 0x40, minus is 0x60 ~ 0x90 */ + /* if value is between p1 ~ o1 or o1 ~ s1, no need to adjust tx power */ + /* if value is 0x65, tx power will be -= TxAgcStep*(2-1) */ + + if (BbpR49 > pTssiMinusBoundary[1]) + { + /* Reading is larger than the reference value. */ + /* Check for how large we need to decrease the Tx power. */ + for (idx = 1; idx < 5; idx++) + { + /* Found the range. */ + if (BbpR49 <= pTssiMinusBoundary[idx]) + break; + } + + /* The index is the step we should decrease, idx = 0 means there is nothing to compensate. */ + *pTxAgcCompensate = -(TxAgcStep * (idx-1)); + + DeltaPwr += (*pTxAgcCompensate); + DBGPRINT(RT_DEBUG_TRACE, ("-- Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = -%d\n", + BbpR49, TssiRef, TxAgcStep, idx-1)); + } + else if (BbpR49 < pTssiPlusBoundary[1]) + { + /* Reading is smaller than the reference value. */ + /* Check for how large we need to increase the Tx power. */ + for (idx = 1; idx < 5; idx++) + { + /* Found the range. */ + if (BbpR49 >= pTssiPlusBoundary[idx]) + break; + } + + /* The index is the step we should increase, idx = 0 means there is nothing to compensate. */ + *pTxAgcCompensate = TxAgcStep * (idx-1); + DeltaPwr += (*pTxAgcCompensate); + DBGPRINT(RT_DEBUG_TRACE, ("++ Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n", + BbpR49, TssiRef, TxAgcStep, idx-1)); + } + else + { + *pTxAgcCompensate = 0; + DBGPRINT(RT_DEBUG_TRACE, (" Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n", + BbpR49, TssiRef, TxAgcStep, 0)); + } + } + } + else + { + if (pATEInfo->Channel <= 14) + { + bAutoTxAgc = pAd->bAutoTxAgcG; + pTxAgcCompensate = &pAd->TxAgcCompensateG; + } + else + { + bAutoTxAgc = pAd->bAutoTxAgcA; + pTxAgcCompensate = &pAd->TxAgcCompensateA; + } + + if (bAutoTxAgc) + DeltaPwr += (*pTxAgcCompensate); + } + + /* Reset different new tx power for different TX rate. */ + for (index=0; index> inner_index*4) & 0x0F); /* 0 ~ 15 */ + +#ifdef RTMP_INTERNAL_TX_ALC + /* + The upper bounds of the MAC 0x1314~0x1324 + are variable when the STA uses the internal Tx ALC. + */ + if (pAd->TxPowerCtrl.bInternalTxALC == TRUE) + { + switch (TX_PWR_CFG_0 + (index * 4)) + { + case TX_PWR_CFG_0: + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xE) + { + Value = 0xE; + } + else + { + Value += TotalDeltaPower; + } + } + break; + + case TX_PWR_CFG_1: + { + if ((inner_index >= 0) && (inner_index <= 3)) + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xC) + { + Value = 0xC; + } + else + { + Value += TotalDeltaPower; + } + } + else + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xE) + { + Value = 0xE; + } + else + { + Value += TotalDeltaPower; + } + } + } + break; + + case TX_PWR_CFG_2: + { + if ((inner_index == 0) || (inner_index == 2) || (inner_index == 3)) + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xC) + { + Value = 0xC; + } + else + { + Value += TotalDeltaPower; + } + } + else + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xE) + { + Value = 0xE; + } + else + { + Value += TotalDeltaPower; + } + } + } + break; + + case TX_PWR_CFG_3: + { + if ((inner_index == 0) || (inner_index == 2) || (inner_index == 3) || + ((inner_index >= 4) && (inner_index <= 7))) + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xC) + { + Value = 0xC; + } + else + { + Value += TotalDeltaPower; + } + } + else + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xE) + { + Value = 0xE; + } + else + { + Value += TotalDeltaPower; + } + } + } + break; + + case TX_PWR_CFG_4: + { + if ((Value + TotalDeltaPower) < 0) + { + Value = 0; + } + else if ((Value + TotalDeltaPower) > 0xC) + { + Value = 0xC; + } + else + { + Value += TotalDeltaPower; + } + } + break; + + default: + { + /* do nothing */ + DBGPRINT_ERR(("%s : unknown register = 0x%X\n", + __FUNCTION__, + (TX_PWR_CFG_0 + (index << 2)))); + } + break; + } + } + else +#endif /* RTMP_INTERNAL_TX_ALC */ + { + if ((Value + DeltaPwr) < 0) + { + Value = 0; /* min */ + } + else if ((Value + DeltaPwr) > 0xF) + { + Value = 0xF; /* max */ + } + else + { + Value += DeltaPwr; /* temperature compensation */ + } + } + + /* fill new value to CSR offset */ + TxPwr[index] = (TxPwr[index] & ~(0x0000000F << inner_index*4)) | (Value << inner_index*4); + } + + /* write tx power value to CSR */ + /* + TX_PWR_CFG_0 (8 tx rate) for TX power for OFDM 12M/18M + TX power for OFDM 6M/9M + TX power for CCK5.5M/11M + TX power for CCK1M/2M + */ + /* TX_PWR_CFG_1 ~ TX_PWR_CFG_4 */ +#ifdef DOT11N_SS3_SUPPORT + if (IS_RT2883(pAd) || IS_RT3883(pAd)) + { + if (index == 5) + { + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_5, TxPwr[index]); + } + else if (index == 6) + { + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_6, TxPwr[index]); + } + else + { + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + (index << 2), TxPwr[index]); + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0_EXT + (index << 2), (TxPwr[index] & 0xf0f0f0f0) >> 4); + } + } + else + { + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + (index << 2), TxPwr[index]); + } +#else + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + (index << 2), TxPwr[index]); +#endif /* DOT11N_SS3_SUPPORT */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATEAsicAdjustTxPower - DeltaPwr=%d, offset=0x%x, TxPwr=%lx, BbpR1=%x, round=%ld, pTxAgcCompensate=%d \n", + DeltaPwr, TX_PWR_CFG_0 + (index << 2), TxPwr[index], BbpR49, pATEInfo->OneSecPeriodicRound, *pTxAgcCompensate)); + + } + } + +} + + +/* +========================================================================== + Description: + Gives CCK TX rate 2 more dB TX power. + This routine works only in ATE mode. + + calculate desired Tx power in RF R3.Tx0~5, should consider - + 0. TxPowerPercentage + 1. auto calibration based on TSSI feedback + 2. extra 2 db for CCK + 3. -10 db upon very-short distance (AvgRSSI >= -40db) to AP + +========================================================================== +*/ +VOID ATEAsicAdjustTxPower( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->AdjustTxPower != NULL) + pATEInfo->pChipStruct->AdjustTxPower(pAd); + else + DBGPRINT_ERR(("%s: AdjustTxPower() for this chipset does not exist !\n", __FUNCTION__)); + + return; +} + + +CHAR ATEConvertToRssi( + IN PRTMP_ADAPTER pAd, + IN CHAR Rssi, + IN UCHAR RssiNumber) +{ + UCHAR RssiOffset, LNAGain; + + /* Rssi equals to zero should be an invalid value */ + if (Rssi == 0 || (RssiNumber >= 3)) + return -99; + + LNAGain = GET_LNA_GAIN(pAd); + if (pAd->LatchRfRegs.Channel > 14) + RssiOffset = pAd->ARssiOffset[RssiNumber]; + else + RssiOffset = pAd->BGRssiOffset[RssiNumber]; + + return (-12 - RssiOffset - LNAGain - Rssi); +} + + +VOID ATESampleRssi( + IN RTMP_ADAPTER *pAd, + IN RXWI_STRUC *pRxWI) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pRxWI->RxWIRSSI0 != 0) + { + pATEInfo->LastRssi0 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RxWIRSSI0, RSSI_0); + pATEInfo->AvgRssi0X8 = (pATEInfo->AvgRssi0X8 - pATEInfo->AvgRssi0) + pATEInfo->LastRssi0; + pATEInfo->AvgRssi0 = pATEInfo->AvgRssi0X8 >> 3; + } + + if (pRxWI->RxWIRSSI1 != 0) + { + pATEInfo->LastRssi1 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RxWIRSSI1, RSSI_1); + pATEInfo->AvgRssi1X8 = (pATEInfo->AvgRssi1X8 - pATEInfo->AvgRssi1) + pATEInfo->LastRssi1; + pATEInfo->AvgRssi1 = pATEInfo->AvgRssi1X8 >> 3; + } + + if (pRxWI->RxWIRSSI2 != 0) + { + pATEInfo->LastRssi2 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RxWIRSSI2, RSSI_2); + pATEInfo->AvgRssi2X8 = (pATEInfo->AvgRssi2X8 - pATEInfo->AvgRssi2) + pATEInfo->LastRssi2; + pATEInfo->AvgRssi2 = pATEInfo->AvgRssi2X8 >> 3; + } + + pATEInfo->LastSNR0 = (CHAR)(pRxWI->RxWIRSSI0); + pATEInfo->LastSNR1 = (CHAR)(pRxWI->RxWIRSSI1); +#ifdef DOT11N_SS3_SUPPORT + pATEInfo->LastSNR2 = (CHAR)(pRxWI->RxWIRSSI2); +#endif /* DOT11N_SS3_SUPPORT */ + + pATEInfo->NumOfAvgRssiSample ++; + + return; +} + + +VOID rt_ee_read_all(PRTMP_ADAPTER pAd, USHORT *Data) +{ + USHORT offset = 0; + USHORT value; + + + for (offset = 0; offset < (EEPROM_SIZE >> 1);) + { + RT28xx_EEPROM_READ16(pAd, (offset << 1), value); + Data[offset] = value; + offset++; + } + + return; +} + + +VOID rt_ee_write_all(PRTMP_ADAPTER pAd, USHORT *Data) +{ + USHORT offset = 0; + USHORT value; + + +#ifdef RTMP_FLASH_SUPPORT + if (pAd->infType == RTMP_DEV_INF_USB) + { + /* for RT3352+RT3572 solution */ + rtmp_ee_flash_write_all(pAd, Data); + return; + } +#endif /* RTMP_FLASH_SUPPORT */ + +#ifdef RTMP_USB_SUPPORT + if (pAd->infType == RTMP_DEV_INF_USB) + { +#ifdef MT7601 + if ( IS_MT7601(pAd) ) + { + USHORT length = 0x100; + UCHAR *ptr = (UCHAR *)Data; + UCHAR index; + UCHAR AllFF[16] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + for ( offset = 0 ; offset < length ; offset += 16 ) + { + if ( memcmp( ptr, AllFF, 16 ) ) + { + for ( index = 0 ; index < 16 ; index += 2 ) + { + value = *(USHORT *)(ptr + index); + eFuseWrite(pAd, offset + index ,&value, 2); + } + } + + ptr += 16; + } + pAd->bCalFreeIC = FALSE; + return; + } + else +#endif /* MT7601 */ + { + USHORT offset = 0; + USHORT length = EEPROM_SIZE; + + RTUSBWriteEEPROM(pAd, offset, (UCHAR *)Data, length); + return; + } + } +#endif /* RTMP_USB_SUPPORT */ + + for (offset = 0; offset < (EEPROM_SIZE >> 1);) + { + value = Data[offset]; + RT28xx_EEPROM_WRITE16(pAd, (offset << 1), value); + offset++; + } + + return; +} + + +VOID rt_ee_write_bulk(PRTMP_ADAPTER pAd, USHORT *Data, USHORT offset, USHORT length) +{ + USHORT pos; + USHORT value; + USHORT len = length; + + + for (pos = 0; pos < (len >> 1);) + { + value = Data[pos]; + RT28xx_EEPROM_WRITE16(pAd, offset+(pos*2), value); + pos++; + } + + return; +} + + +VOID RtmpRfIoWrite( + IN PRTMP_ADAPTER pAd) +{ + /* Set RF value 1's set R3[bit2] = [0] */ + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2); + RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04))); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4); + + RTMPusecDelay(200); + + /* Set RF value 2's set R3[bit2] = [1] */ + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2); + RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 | 0x04)); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4); + + RTMPusecDelay(200); + + /* Set RF value 3's set R3[bit2] = [0] */ + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2); + RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04))); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4); + + return; +} + + +VOID DefaultATEAsicSetTxRxPath( + IN PRTMP_ADAPTER pAd) +{ + +} + + +VOID ATEAsicSetTxRxPath( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->AsicSetTxRxPath != NULL) + pATEInfo->pChipStruct->AsicSetTxRxPath(pAd); + + return; +} + + +/* +========================================================================== + Description: + + Default AsicSwitchChannel() dedicated for ATE. + +========================================================================== +*/ +VOID DefaultATEAsicSwitchChannel( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 Value = 0; + CHAR TxPwer = 0, TxPwer2 = 0; + UCHAR BbpValue = 0, R66 = 0x30, Channel = 0; + + SYNC_CHANNEL_WITH_QA(pATEInfo, &Channel); + + /* fill Tx power value */ + TxPwer = pATEInfo->TxPower0; + TxPwer2 = pATEInfo->TxPower1; + + /* Change BBP setting during switch from a->g, g->a */ + if (Channel <= 14) + { + UINT32 TxPinCfg = 0x00050F0A;/* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */ + + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); + + /* Rx High power VGA offset for LNA select */ + if (pAd->NicConfig2.field.ExternalLNAForG) + { + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); + } + else + { + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); + } + + /* 2.4 G band selection PIN */ + RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); + Value &= (~0x6); + Value |= (0x04); + RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); + + /* Turn off unused PA or LNA when only 1T or 1R. */ + if (pAd->Antenna.field.TxPath == 1) + { + TxPinCfg &= 0xFFFFFFF3; + } + if (pAd->Antenna.field.RxPath == 1) + { + TxPinCfg &= 0xFFFFF3FF; + } + + /* calibration power unbalance issues */ + if (pAd->Antenna.field.TxPath == 2) + { + if (pATEInfo->TxAntennaSel == 1) + { + TxPinCfg &= 0xFFFFFFF7; + } + else if (pATEInfo->TxAntennaSel == 2) + { + TxPinCfg &= 0xFFFFFFFD; + } + } + + RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); + } + /* channel > 14 */ + else + { + UINT32 TxPinCfg = 0x00050F05;/* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */ + + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); + + /* According the Rory's suggestion to solve the middle range issue. */ + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0); + + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2); + + /* Rx High power VGA offset for LNA select */ + if (pAd->NicConfig2.field.ExternalLNAForA) + { + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); + } + else + { + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); + } + + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue); + ASSERT((BbpValue == 0x04)); + + /* 5 G band selection PIN, bit1 and bit2 are complement */ + RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); + Value &= (~0x6); + Value |= (0x02); + RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); + + /* Turn off unused PA or LNA when only 1T or 1R. */ + if (pAd->Antenna.field.TxPath == 1) + { + TxPinCfg &= 0xFFFFFFF3; + } + + if (pAd->Antenna.field.RxPath == 1) + { + TxPinCfg &= 0xFFFFF3FF; + } + + RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); + } + + /* R66 should be set according to Channel. */ + if (Channel <= 14) + { + /* BG band */ + R66 = 0x2E + GET_LNA_GAIN(pAd); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66); + } + else + { + /* A band, BW == 20 */ + if (pATEInfo->TxWI.TxWIBW == BW_20) + { + R66 = (UCHAR)(0x32 + (GET_LNA_GAIN(pAd)*5)/3); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66); + } + else + { + /* A band, BW == 40 */ + R66 = (UCHAR)(0x3A + (GET_LNA_GAIN(pAd)*5)/3); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66); + } + } + + RtmpOsMsDelay(1); + +} + + +/* +========================================================================== + Description: + + AsicSwitchChannel() dedicated for ATE. + +========================================================================== +*/ +VOID ATEAsicSwitchChannel( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->ChannelSwitch != NULL) + pATEInfo->pChipStruct->ChannelSwitch(pAd); + + return; +} + + +VOID BbpSoftReset( + IN PRTMP_ADAPTER pAd) +{ + UCHAR BbpData = 0; + + /* Soft reset, set BBP R21 bit0=1->0 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData); + BbpData |= 0x00000001; /* set bit0=1 */ + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData); + + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData); + BbpData &= ~(0x00000001); /* set bit0=0 */ + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData); + + return; +} + + +static VOID BbpHardReset( + IN PRTMP_ADAPTER pAd) +{ + UINT32 MacData = 0; + + + RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData); + MacData = MacData | 0x00000002; + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData); + + RtmpOsMsDelay(10); + + RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData); + MacData = MacData & ~(0x00000002); + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData); + + return; +} + + +static int CheckMCSValid( + IN PRTMP_ADAPTER pAd, + IN UCHAR Mode, + IN UCHAR Mcs) +{ + int index; + PCHAR pRateTab = NULL; + + switch (Mode) + { + case MODE_CCK: + pRateTab = CCKRateTable; + break; + case MODE_OFDM: + pRateTab = OFDMRateTable; + break; + + case 2: /*MODE_HTMIX*/ + case 3: /*MODE_HTGREENFIELD*/ +#ifdef DOT11N_SS3_SUPPORT + if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd)) + pRateTab = HTMIXRateTable3T3R; + else +#endif /* DOT11N_SS3_SUPPORT */ + pRateTab = HTMIXRateTable; + break; + + default: + DBGPRINT_ERR(("unrecognizable Tx Mode %d\n", Mode)); + return -1; + break; + } + + index = 0; + while (pRateTab[index] != -1) + { + if (pRateTab[index] == Mcs) + return 0; + index++; + } + + return -1; +} + + +INT DefaultATETxPwrHandler( + IN PRTMP_ADAPTER pAd, + IN char index) +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR TxPower = 0; + +#ifdef RALINK_QA + if ((pATEInfo->bQATxStart == TRUE) || (pATEInfo->bQARxStart == TRUE)) + { + /* + When QA is used for Tx, pATEInfo->TxPower0/1 and real tx power + are not synchronized. + */ + return 0; + } + else +#endif /* RALINK_QA */ + + if (index == 0) + { + TxPower = pATEInfo->TxPower0; + } + else if (index == 1) + { + TxPower = pATEInfo->TxPower1; + } + else + { + DBGPRINT_ERR(("%s : Only TxPower0 and TxPower1 are adjustable !\n", __FUNCTION__)); + DBGPRINT_ERR(("TxPower%d is out of range !\n", index)); + return -1; + } + + + DBGPRINT(RT_DEBUG_TRACE, ("<--- %s\n", __FUNCTION__)); + + return 0; +} + + +INT ATETxPwrHandler( + IN PRTMP_ADAPTER pAd, + IN char index) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->TxPwrHandler != NULL) + pATEInfo->pChipStruct->TxPwrHandler(pAd, index); + + return 0; +} + + +/* +======================================================================== + + Routine Description: + Set Japan filter coefficients if needed. + Note: + This routine should only be called when + entering TXFRAME mode or TXCONT mode. + +======================================================================== +*/ +static VOID SetJapanFilter( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR BbpData = 0; + + /* + If Channel=14 and Bandwidth=20M and Mode=CCK, set BBP R4 bit5=1 + (Japan Tx filter coefficients)when (TXFRAME or TXCONT). + */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BbpData); + + if ((pATEInfo->TxWI.TxWIPHYMODE == MODE_CCK) && (pATEInfo->Channel == 14) && (pATEInfo->TxWI.TxWIBW == BW_20)) + { + BbpData |= 0x20; /* turn on */ + DBGPRINT(RT_DEBUG_TRACE, ("SetJapanFilter!!!\n")); + } + else + { + BbpData &= 0xdf; /* turn off */ + DBGPRINT(RT_DEBUG_TRACE, ("ClearJapanFilter!!!\n")); + } + + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData); + + return; +} + + +/* +======================================================================== + + Routine Description: + Disable protection for ATE. +======================================================================== +*/ +VOID ATEDisableAsicProtect( + IN PRTMP_ADAPTER pAd) +{ + PROT_CFG_STRUC ProtCfg, ProtCfg4; + UINT32 Protect[6]; + USHORT offset; + UCHAR step; + UINT32 MacReg = 0; + + /* Config ASIC RTS threshold register */ + RTMP_IO_READ32(pAd, TX_RTS_CFG, &MacReg); + MacReg &= 0xFF0000FF; + MacReg |= (0xFFF << 8); + RTMP_IO_WRITE32(pAd, TX_RTS_CFG, MacReg); + + /* Initial common protection settings */ + RTMPZeroMemory(Protect, sizeof(Protect)); + ProtCfg4.word = 0; + ProtCfg.word = 0; + ProtCfg.field.TxopAllowGF40 = 1; + ProtCfg.field.TxopAllowGF20 = 1; + ProtCfg.field.TxopAllowMM40 = 1; + ProtCfg.field.TxopAllowMM20 = 1; + ProtCfg.field.TxopAllowOfdm = 1; + ProtCfg.field.TxopAllowCck = 1; + ProtCfg.field.RTSThEn = 1; + ProtCfg.field.ProtectNav = ASIC_SHORTNAV; + + /* Handle legacy(B/G) protection */ + ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate; + ProtCfg.field.ProtectCtrl = 0; + Protect[0] = ProtCfg.word; + Protect[1] = ProtCfg.word; + /* CTS-self is not used */ + pAd->FlgCtsEnabled = 0; + + /* + NO PROTECT + 1.All STAs in the BSS are 20/40 MHz HT + 2. in a 20/40MHz BSS + 3. all STAs are 20MHz in a 20MHz BSS + Pure HT. no protection. + */ + /* + MM20_PROT_CFG + Reserved (31:27) + PROT_TXOP(25:20) -- 010111 + PROT_NAV(19:18) -- 01 (Short NAV protection) + PROT_CTRL(17:16) -- 00 (None) + PROT_RATE(15:0) -- 0x4004 (OFDM 24M) + */ + Protect[2] = 0x01744004; + + /* + MM40_PROT_CFG + Reserved (31:27) + PROT_TXOP(25:20) -- 111111 + PROT_NAV(19:18) -- 01 (Short NAV protection) + PROT_CTRL(17:16) -- 00 (None) + PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M) + */ + Protect[3] = 0x03f44084; + + /* + CF20_PROT_CFG + Reserved (31:27) + PROT_TXOP(25:20) -- 010111 + PROT_NAV(19:18) -- 01 (Short NAV protection) + PROT_CTRL(17:16) -- 00 (None) + PROT_RATE(15:0) -- 0x4004 (OFDM 24M) + */ + Protect[4] = 0x01744004; + + /* + CF40_PROT_CFG + Reserved (31:27) + PROT_TXOP(25:20) -- 111111 + PROT_NAV(19:18) -- 01 (Short NAV protection) + PROT_CTRL(17:16) -- 00 (None) + PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M) + */ + Protect[5] = 0x03f44084; + + pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE; + + offset = CCK_PROT_CFG; + for (step = 0;step < 6;step++) + RTMP_IO_WRITE32(pAd, offset + step*4, Protect[step]); + + return; +} + + +#ifdef CONFIG_AP_SUPPORT +/* +========================================================================== + Description: + Used only by ATE to disassociate all STAs and stop AP service. + Note: +========================================================================== +*/ +VOID ATEAPStop( + IN PRTMP_ADAPTER pAd) +{ + BOOLEAN Cancelled; + UINT32 Value = 0; + INT apidx = 0; + + DBGPRINT(RT_DEBUG_TRACE, ("!!! ATEAPStop !!!\n")); + + /* To prevent MCU to modify BBP registers w/o indications from driver. */ +#ifdef DFS_SUPPORT + NewRadarDetectionStop(pAd); +#endif /* DFS_SUPPORT */ + +#ifdef CONFIG_AP_SUPPORT +#ifdef CARRIER_DETECTION_SUPPORT + if (pAd->CommonCfg.CarrierDetect.Enable == TRUE) + { + CarrierDetectionStop(pAd); + } +#endif /* CARRIER_DETECTION_SUPPORT */ +#endif /* CONFIG_AP_SUPPORT */ + + +#ifdef WDS_SUPPORT + WdsDown(pAd); +#endif /* WDS_SUPPORT */ + +#ifdef APCLI_SUPPORT + ApCliIfDown(pAd); +#endif /* APCLI_SUPPORT */ + + MacTableReset(pAd); + + /* Disable pre-tbtt interrupt */ + RTMP_IO_READ32(pAd, INT_TIMER_EN, &Value); + Value &=0xe; + RTMP_IO_WRITE32(pAd, INT_TIMER_EN, Value); + /* Disable piggyback */ + RTMPSetPiggyBack(pAd, FALSE); + + ATEDisableAsicProtect(pAd); + + if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) + { + AsicDisableSync(pAd); + +#ifdef LED_CONTROL_SUPPORT + /* Set LED */ + RTMPSetLED(pAd, LED_LINK_DOWN); +#endif /* LED_CONTROL_SUPPORT */ + } + +#ifdef RTMP_MAC_USB + /* For USB, we need to clear the beacon sync buffer. */ + RTUSBBssBeaconExit(pAd); +#endif /* RTMP_MAC_USB */ + + for (apidx = 0; apidx < MAX_MBSSID_NUM(pAd); apidx++) + { + if (pAd->ApCfg.MBSSID[apidx].REKEYTimerRunning == TRUE) + { + RTMPCancelTimer(&pAd->ApCfg.MBSSID[apidx].REKEYTimer, &Cancelled); + pAd->ApCfg.MBSSID[apidx].REKEYTimerRunning = FALSE; + } + } + + if (pAd->ApCfg.CMTimerRunning == TRUE) + { + RTMPCancelTimer(&pAd->ApCfg.CounterMeasureTimer, &Cancelled); + pAd->ApCfg.CMTimerRunning = FALSE; + } + +#ifdef WAPI_SUPPORT + RTMPCancelWapiRekeyTimerAction(pAd, NULL); +#endif /* WAPI_SUPPORT */ + + /* Cancel the Timer, to make sure the timer was not queued. */ + OPSTATUS_CLEAR_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED); + RTMP_IndicateMediaState(pAd, NdisMediaStateDisconnected); + + if (pAd->ApCfg.ApQuickResponeForRateUpTimerRunning == TRUE) + RTMPCancelTimer(&pAd->ApCfg.ApQuickResponeForRateUpTimer, &Cancelled); + +#ifdef IDS_SUPPORT + /* if necessary, cancel IDS timer */ + RTMPIdsStop(pAd); +#endif /* IDS_SUPPORT */ + + +#ifdef GREENAP_SUPPORT + if (pAd->ApCfg.bGreenAPEnable == TRUE) + { + RTMP_CHIP_DISABLE_AP_MIMOPS(pAd); + pAd->ApCfg.GreenAPLevel=GREENAP_WITHOUT_ANY_STAS_CONNECT; + pAd->ApCfg.bGreenAPEnable = FALSE; + } +#endif /* GREENAP_SUPPORT */ + + +} +#endif /* CONFIG_AP_SUPPORT */ + + + + + + +static NDIS_STATUS ATESTART( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0, atemode=0, temp=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; +#ifdef RTMP_MAC_USB + UCHAR LoopCount=0; +#endif /* RTMP_MAC_USB */ + PATE_CHIP_STRUCT pChipStruct = pATEInfo->pChipStruct; + BOOLEAN Cancelled; + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + +#ifdef RTMP_MAC_USB + RTMP_OS_NETDEV_STOP_QUEUE(pAd->net_dev); +#endif /* RTMP_MAC_USB */ + + atemode = pATEInfo->Mode; + pATEInfo->Mode = ATE_START; + + if (atemode == ATE_STOP) + { + /* DUT just enters ATE mode from normal mode. */ + /* Only at this moment, we need to switch back to the channel of normal mode. */ + AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); + /* empty function */ + AsicLockChannel(pAd, pAd->CommonCfg.Channel); + } + +#ifdef RTMP_MAC_USB + +#ifdef MT7601 + MT7601DisableTxRx(pAd, GUIRADIO_OFF); +#endif /* MT7601 */ + + + /* one second is enough for waiting bulk-in urb */ + while ((pAd->PendingRx > 0) && (LoopCount < 2)) + { + /* delay 0.5 seconds */ + OS_WAIT(500); + LoopCount++; + } +#endif /* RTMP_MAC_USB */ + + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Disable auto responder */ + RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &temp); + temp = temp & 0xFFFFFFFE; + RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, temp); + + ATE_MAC_TX_CTS_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + if (atemode == ATE_TXCARR) + { + if (pChipStruct->bBBPStoreTXCARR == TRUE) + { + UINT32 bbp_index=0; + UCHAR RestoreRfICType=pAd->RfIcType; + + BbpHardReset(pAd); + + /* Restore All BBP Value */ + for (bbp_index=0;bbp_indexRfIcType=RestoreRfICType; + } + + if (pATEInfo->TxMethod == TX_METHOD_1) + { + /* No Carrier Test set BBP R22 bit6=0, bit[5~0]=0x0 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData); + BbpData &= 0xFFFFFF80; /* clear bit6, bit[5~0] */ + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData); + + BbpSoftReset(pAd); + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, Default_TX_PIN_CFG); + } + else + { + /* No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0 */ + ATE_BBP_RESET_TX_MODE(pAd, BBP_R22, &BbpData); + } + } + else if (atemode == ATE_TXCARRSUPP) + { + if (pChipStruct->bBBPStoreTXCARRSUPP == TRUE) + { + UINT32 bbp_index=0; + UCHAR RestoreRfICType=pAd->RfIcType; + + BbpHardReset(pAd); + + /* Restore All BBP Value */ + for (bbp_index=0;bbp_indexRfIcType=RestoreRfICType; + } + + /* No Cont. TX set BBP R22 bit7=0 */ + ATE_BBP_STOP_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + + /* No Carrier Suppression set BBP R24 bit0=0 */ + ATE_BBP_CTS_TX_SIN_WAVE_DISABLE(pAd, BBP_R24, &BbpData); + + if (pATEInfo->TxMethod == TX_METHOD_1) + { + BbpSoftReset(pAd); + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, Default_TX_PIN_CFG); + } + } + + /* + We should free some resource which was allocated + when ATE_TXFRAME , ATE_STOP, and ATE_TXCONT. + */ + else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP)) + { + if (atemode == ATE_TXCONT) + { + if (pChipStruct->bBBPStoreTXCONT == TRUE) + { + UINT32 bbp_index=0; + UCHAR RestoreRfICType=pAd->RfIcType; + + BbpHardReset(pAd); + + /* Restore All BBP Value */ + for (bbp_index=0;bbp_indexRfIcType=RestoreRfICType; + } + + /* Not Cont. TX anymore, so set BBP R22 bit7=0 */ + ATE_BBP_STOP_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + + if (pATEInfo->TxMethod == TX_METHOD_1) + { + BbpSoftReset(pAd); + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, Default_TX_PIN_CFG); + } + } + + /* Abort Tx, Rx DMA. */ + RtmpDmaEnable(pAd, 0); + + /* Start Tx, RX DMA */ + RtmpDmaEnable(pAd, 1); + } + +#ifdef RTMP_MAC_USB +/* pAd->ContinBulkIn = FALSE; */ + RTUSBRejectPendingPackets(pAd); + RTUSBCleanUpDataBulkOutQueue(pAd); + + + RTUSBCleanUpMLMEBulkOutQueue(pAd); + + + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Abort Tx, RX DMA. */ + /* If disable DMA TX and RX, in-band command not word */ + //RtmpDmaEnable(pAd, 0); + + /* Disable Tx */ + ATE_MAC_TX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* + Make sure there are no pending bulk in/out IRPs before we go on. + pAd->BulkFlags != 0 : wait bulk out finish + */ + while ((pAd->PendingRx > 0)) + { + ATE_RTUSBCancelPendingBulkInIRP(pAd); + + /* delay 0.5 seconds */ + RtmpOsMsDelay(500); + pAd->PendingRx = 0; + } + + while (((pAd->BulkOutPending[0] == TRUE) || + (pAd->BulkOutPending[1] == TRUE) || + (pAd->BulkOutPending[2] == TRUE) || + (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) + /* pAd->BulkFlags != 0 : wait bulk out finish */ + { + do + { + /* + pAd->BulkOutPending[y] will be set to FALSE + in RTUSBCancelPendingBulkOutIRP(pAd) + */ + RTUSBCancelPendingBulkOutIRP(pAd); + } while (FALSE); + + } + + ASSERT(pAd->PendingRx == 0); +#endif /* RTMP_MAC_USB */ + + /* reset Rx statistics. */ + pATEInfo->LastSNR0 = 0; + pATEInfo->LastSNR1 = 0; +#ifdef DOT11N_SS3_SUPPORT + pATEInfo->LastSNR2 = 0; +#endif /* DOT11N_SS3_SUPPORT */ + pATEInfo->LastRssi0 = 0; + pATEInfo->LastRssi1 = 0; + pATEInfo->LastRssi2 = 0; + pATEInfo->AvgRssi0 = 0; + pATEInfo->AvgRssi1 = 0; + pATEInfo->AvgRssi2 = 0; + pATEInfo->AvgRssi0X8 = 0; + pATEInfo->AvgRssi1X8 = 0; + pATEInfo->AvgRssi2X8 = 0; + pATEInfo->NumOfAvgRssiSample = 0; + +#ifdef RALINK_QA + /* Tx frame */ + pATEInfo->bQATxStart = FALSE; + pATEInfo->bQARxStart = FALSE; + pATEInfo->seq = 0; + + /* counters */ + pATEInfo->U2M = 0; + pATEInfo->OtherData = 0; + pATEInfo->Beacon = 0; + pATEInfo->OtherCount = 0; + pATEInfo->TxAc0 = 0; + pATEInfo->TxAc1 = 0; + pATEInfo->TxAc2 = 0; + pATEInfo->TxAc3 = 0; + pATEInfo->TxHCCA = 0; + pATEInfo->TxMgmt = 0; + pATEInfo->RSSI0 = 0; + pATEInfo->RSSI1 = 0; + pATEInfo->RSSI2 = 0; + pATEInfo->SNR0 = 0; + pATEInfo->SNR1 = 0; +#ifdef DOT11N_SS3_SUPPORT + pATEInfo->SNR2 = 0; +#endif /* DOT11N_SS3_SUPPORT */ + pATEInfo->IPG = 200; + + /* control */ + pATEInfo->TxDoneCount = 0; + /* TxStatus : 0 --> task is idle, 1 --> task is running */ + pATEInfo->TxStatus = 0; +#endif /* RALINK_QA */ + + /* Soft reset BBP. */ + BbpSoftReset(pAd); + +#ifdef CONFIG_AP_SUPPORT + + /* Set IPG 200 by default. */ + Set_ATE_IPG_Proc(pAd, "200"); + if (atemode == ATE_STOP) + ATEAPStop(pAd); +#endif /* CONFIG_AP_SUPPORT */ + + + if ((atemode == ATE_STOP) && (pATEInfo->PeriodicTimer.State == FALSE)) + { + /* Do it for the first time entering ATE mode */ + pATEInfo->PeriodicTimer.State = TRUE; + } + + if (pATEInfo->PeriodicTimer.State == TRUE) + { + /* + For rx statistics, we cancel pAd->Mlme.PeriodicTimer + and set pAd->ate.PeriodicTimer. + */ + RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled); + /* Init ATE periodic timer */ + RTMPInitTimer(pAd, &pAd->ate.PeriodicTimer, GET_TIMER_FUNCTION(ATEPeriodicExec), pAd, TRUE); + /* Set ATE periodic timer */ + RTMPSetTimer(&pAd->ate.PeriodicTimer, ATE_TASK_EXEC_INTV); + } + else + { + DBGPRINT(RT_DEBUG_TRACE, ("We are still in ATE mode, ")); + DBGPRINT(RT_DEBUG_TRACE, ("so we keep ATE periodic timer running.\n")); + } + +#ifdef LED_CONTROL_SUPPORT + RTMPExitLEDMode(pAd); +#endif /* LED_CONTROL_SUPPORT */ + + +#ifdef RTMP_MAC_USB + /* Default value in BBP R22 is 0x0. */ + ATE_BBP_RESET_TX_MODE(pAd, BBP_R22, &BbpData); + + /* Clear bit4 to stop continuous Tx production test. */ + ATE_MAC_TX_CTS_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Clear ATE Bulk in/out counter and continue setup */ + InterlockedExchange(&pAd->BulkOutRemained, 0); + + /* NdisAcquireSpinLock()/NdisReleaseSpinLock() need only one argument in RT28xx */ + NdisAcquireSpinLock(&pAd->GenericLock); + pAd->ContinBulkOut = FALSE; + pAd->ContinBulkIn = FALSE; + NdisReleaseSpinLock(&pAd->GenericLock); + + RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE); +#endif /* RTMP_MAC_USB */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +static NDIS_STATUS ATESTOP( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0, ring_index=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; + PATE_CHIP_STRUCT pChipStruct = pATEInfo->pChipStruct; + BOOLEAN Cancelled; + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + if (pChipStruct->bBBPLoadATESTOP == TRUE) + { + UINT32 bbp_index=0; + UCHAR RestoreRfICType=pAd->RfIcType; + + BbpHardReset(pAd); + + /* Supposed that we have had a record in restore_BBP[] */ + /* restore all BBP value */ + for (bbp_index=0;bbp_indexRfIcType=RestoreRfICType; + } + + + InterlockedExchange(&pAd->BulkOutRemained, 0); + NdisAcquireSpinLock(&pAd->GenericLock); + pAd->ContinBulkOut = FALSE; + //pAd->ContinBulkIn = FALSE; + NdisReleaseSpinLock(&pAd->GenericLock); + + /* Default value in BBP R22 is 0x0. */ + ATE_BBP_RESET_TX_MODE(pAd, BBP_R22, &BbpData); + +#ifdef MT7601 + MT7601DisableTxRx(pAd, GUIRADIO_OFF); +#else + /* Clear bit4 to stop continuous Tx production test. */ + ATE_MAC_TX_CTS_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Abort Tx, RX DMA */ + RtmpDmaEnable(pAd, 0); + + /* Disable Tx */ + ATE_MAC_TX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); +#endif /* MT7601 */ + + pAd->ContinBulkIn = FALSE; + + + if (pATEInfo->PeriodicTimer.State == FALSE) + { + /* + For rx statistics, we cancel pAd->Mlme.PeriodicTimer + and set pATEInfo->PeriodicTimer in stead of. + Now we recover it before we leave ATE mode. + */ + RTMPCancelTimer(&pATEInfo->PeriodicTimer, &Cancelled); + /* Init MLME periodic timer */ + RTMPInitTimer(pAd, &pAd->Mlme.PeriodicTimer, GET_TIMER_FUNCTION(MlmePeriodicExec), pAd, TRUE); + /* Set MLME periodic timer */ + RTMPSetTimer(&pAd->Mlme.PeriodicTimer, MLME_TASK_EXEC_INTV); + } + else + { + /* ATE periodic timer has been cancelled. */ + Status = NDIS_STATUS_FAILURE; + DBGPRINT_ERR(("Initialization of MLME periodic timer failed, Status[=0x%08x]\n", Status)); + + return Status; + } + + +#ifdef RTMP_MAC_USB + /* + Make sure there are no pending bulk in/out IRPs before we go on. + pAd->BulkFlags != 0 : wait bulk out finish + */ +/* pAd->ContinBulkIn = FALSE; */ + + if (pAd->PendingRx > 0) + { + ATE_RTUSBCancelPendingBulkInIRP(pAd); + //RtmpOsMsDelay(500); + } + + while (((pAd->BulkOutPending[0] == TRUE) || + (pAd->BulkOutPending[1] == TRUE) || + (pAd->BulkOutPending[2] == TRUE) || + (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) + /* pAd->BulkFlags != 0 : wait bulk out finish */ + { + do + { + RTUSBCancelPendingBulkOutIRP(pAd); + } while (FALSE); + + RtmpOsMsDelay(500); + } + + ASSERT(pAd->PendingRx == 0); +/*=========================================================================*/ +/* Reset Rx RING */ +/*=========================================================================*/ + pAd->PendingRx = 0; + /* Next Rx Read index */ + pAd->NextRxBulkInReadIndex = 0; + /* Rx Bulk pointer */ + pAd->NextRxBulkInIndex = RX_RING_SIZE - 1; + pAd->NextRxBulkInPosition = 0; + for (ring_index = 0; ring_index < (RX_RING_SIZE); ring_index++) + { + PRX_CONTEXT pRxContext = &(pAd->RxContext[ring_index]); + NdisZeroMemory(pRxContext->TransferBuffer, MAX_RXBULK_SIZE); + + pRxContext->pAd = pAd; + pRxContext->pIrp = NULL; + pRxContext->BulkInOffset = 0; + pRxContext->bRxHandling = FALSE; + pRxContext->InUse = FALSE; + pRxContext->IRPPending = FALSE; + pRxContext->Readable = FALSE; + } + +/*=========================================================================*/ +/* Reset Tx RING */ +/*=========================================================================*/ + do + { + RTUSBCancelPendingBulkOutIRP(pAd); + } while (FALSE); + + /* Enable auto responder. */ + RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &MacData); + MacData = MacData | (0x01); + RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, MacData); + + AsicEnableBssSync(pAd); + BbpSoftReset(pAd); + { + + /* + ===> refer to MlmeRestartStateMachine(). + When we entered ATE_START mode, PeriodicTimer was not cancelled. + So we don't have to set it here. + */ + + ASSERT(pAd->CommonCfg.Channel != 0); + + AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); + + /* empty function */ + AsicLockChannel(pAd, pAd->CommonCfg.Channel); + +#ifdef CONFIG_AP_SUPPORT + APStartUp(pAd); +#endif /* CONFIG_AP_SUPPORT */ + + } + + /* Clear ATE Bulk in/out counter and continue setup. */ + + /* Wait 50ms to prevent next URB to bulkout during HW reset. */ + /* todo : remove this if not necessary */ + RtmpOsMsDelay(50); + + pATEInfo->Mode = ATE_STOP; +#endif /* RTMP_MAC_USB */ + +#ifdef CONFIG_AP_SUPPORT + /* restore RX_FILTR_CFG */ + RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, APNORMAL); +#endif /* CONFIG_AP_SUPPORT */ + + + /* Enable Tx */ + ATE_MAC_TX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Enable Tx, Rx DMA. */ + RtmpDmaEnable(pAd, 1); + + /* Enable Rx */ + ATE_MAC_RX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + + +#ifdef RTMP_MAC_USB + /* Wait 10ms for all of the bulk-in URBs to complete. */ + RtmpOsMsDelay(10); + + /* Everything is ready to start normal Tx/Rx. */ + RTUSBBulkReceive(pAd); +#endif /* RTMP_MAC_USB */ + RTMP_OS_NETDEV_START_QUEUE(pAd->net_dev); + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +static NDIS_STATUS TXCARR( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; + PATE_CHIP_STRUCT pChipStruct = pATEInfo->pChipStruct; + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + pATEInfo->Mode = ATE_TXCARR; + + if (pChipStruct->bBBPStoreTXCARR == TRUE) + { + UINT32 bbp_index=0; + + /* Zero All BBP Value */ + for (bbp_index=0;bbp_indexbQATxStart == FALSE) + { + if ((!IS_RT3883(pAd)) && (!IS_RT3352(pAd)) && (!IS_RT5350(pAd)) && (!IS_RT3593(pAd))) + BbpSoftReset(pAd);/* Soft reset BBP. */ + + if (pATEInfo->TxMethod == TX_METHOD_1) + { + /* store the original value of RA_TX_PIN_CFG */ + RTMP_IO_READ32(pAd, RA_TX_PIN_CFG, &Default_TX_PIN_CFG); + + /* give RA_TX_PIN_CFG(0x1328) a proper value. */ + if (pATEInfo->Channel <= 14) + { + /* G band */ + MacData = TXCONT_TX_PIN_CFG_G; + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, MacData); + } + else + { + /* A band */ + MacData = TXCONT_TX_PIN_CFG_A; + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, MacData); + } + + /* Carrier Test set BBP R22 bit6=1, bit[5~0]=0x01 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData); + BbpData &= 0xFFFFFF80; /* bit6, bit[5~0] */ + BbpData |= 0x00000041; /* set bit6=1, bit[5~0]=0x01 */ + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData); + } + else + { + /* Carrier Test set BBP R22 bit7=1, bit6=1, bit[5~0]=0x01 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData); + BbpData &= 0xFFFFFF00; /* clear bit7, bit6, bit[5~0] */ + BbpData |= 0x000000C1; /* set bit7=1, bit6=1, bit[5~0]=0x01 */ + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData); + + /* Set MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 1. */ + ATE_MAC_TX_CTS_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + } + } + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +static NDIS_STATUS TXCONT( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; + PATE_CHIP_STRUCT pChipStruct = pATEInfo->pChipStruct; + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + if (pATEInfo->bQATxStart == TRUE) + { + /* + set MAC_SYS_CTRL(0x1004) bit4(Continuous Tx Production Test) + and bit2(MAC TX enable) back to zero. + */ + ATE_MAC_TX_CTS_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + ATE_MAC_TX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* set BBP R22 bit7=0 */ + ATE_BBP_STOP_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + } + else + { + if (pATEInfo->TxMethod == TX_METHOD_1) + { + /* store the original value of RA_TX_PIN_CFG */ + RTMP_IO_READ32(pAd, RA_TX_PIN_CFG, &Default_TX_PIN_CFG); + } + } + + if (pChipStruct->bBBPStoreTXCONT == TRUE) + { + UINT32 bbp_index=0; + + /* Zero All BBP Value */ + for(bbp_index=0;bbp_indexMode = ATE_TXCONT; + pATEInfo->TxCount = 50; + + if ((!IS_RT3883(pAd)) && (!IS_RT3352(pAd)) && (!IS_RT5350(pAd)) && (!IS_RT3593(pAd))) + BbpSoftReset(pAd);/* Soft reset BBP. */ + + /* Abort Tx, RX DMA. */ + RtmpDmaEnable(pAd, 0); + + + /* Do it after Tx/Rx DMA is aborted. */ + pATEInfo->TxDoneCount = 0; + + /* Only needed if we have to send some normal frames. */ + SetJapanFilter(pAd); + + +#ifdef RTMP_MAC_USB + /* Setup frame format. */ + ATESetUpFrame(pAd, 0); +#endif /* RTMP_MAC_USB */ + + /* Enable Tx */ + ATE_MAC_TX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Start Tx, Rx DMA. */ + RtmpDmaEnable(pAd, 1); + +#ifdef RTMP_MAC_USB + InterlockedExchange(&pAd->BulkOutRemained, pATEInfo->TxCount); +#endif /* RTMP_MAC_USB */ + +#ifdef RALINK_QA + if (pATEInfo->bQATxStart == TRUE) + { + pATEInfo->TxStatus = 1; + } +#endif /* RALINK_QA */ + + +#ifdef RTMP_MAC_USB + NdisAcquireSpinLock(&pAd->GenericLock); + pAd->ContinBulkOut = FALSE; + NdisReleaseSpinLock(&pAd->GenericLock); + + RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE); + + /* Kick bulk out */ + RTUSBKickBulkOut(pAd); + + /* To make sure all the 50 frames have been bulk out before executing step 2 */ + while (atomic_read(&pAd->BulkOutRemained) > 0) + { + RtmpOsMsDelay(5); + } +#endif /* RTMP_MAC_USB */ + + if (pATEInfo->TxMethod == TX_METHOD_1) + { + /* give RA_TX_PIN_CFG(0x1328) a proper value. */ + if (pATEInfo->Channel <= 14) + { + /* G band */ + MacData = TXCONT_TX_PIN_CFG_G; + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, MacData); + } + else + { + /* A band */ + MacData = TXCONT_TX_PIN_CFG_A; + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, MacData); + } + + /* Cont. TX set BBP R22 bit7=1 */ + ATE_BBP_START_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + } + else + { + /* Step 2: send more 50 packets then start Continuous Tx Mode. */ + /* Abort Tx, RX DMA. */ + RtmpDmaEnable(pAd, 0); + + /* Cont. TX set BBP R22 bit7=1 */ + ATE_BBP_START_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + + pATEInfo->TxCount = 50; + + pATEInfo->TxDoneCount = 0; + SetJapanFilter(pAd); + + +#ifdef RTMP_MAC_USB + /* Build up Tx frame. */ + ATESetUpFrame(pAd, 0); +#endif /* RTMP_MAC_USB */ + + /* Enable Tx */ + ATE_MAC_TX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Start Tx, Rx DMA. */ + RtmpDmaEnable(pAd, 1); + +#ifdef RTMP_MAC_USB + InterlockedExchange(&pAd->BulkOutRemained, pATEInfo->TxCount); +#endif /* RTMP_MAC_USB */ +#ifdef RALINK_QA + if (pATEInfo->bQATxStart == TRUE) + { + pATEInfo->TxStatus = 1; + } +#endif /* RALINK_QA */ + + +#ifdef RTMP_MAC_USB + NdisAcquireSpinLock(&pAd->GenericLock); + pAd->ContinBulkOut = FALSE; + NdisReleaseSpinLock(&pAd->GenericLock); + + RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE); + /* Kick bulk out */ + RTUSBKickBulkOut(pAd); + + /* Let pAd->BulkOutRemained be consumed to zero. */ +#endif /* RTMP_MAC_USB */ + RTMPusecDelay(500); + + /* enable continuous tx production test */ + ATE_MAC_TX_CTS_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + } + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +static NDIS_STATUS TXCARS( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; + PATE_CHIP_STRUCT pChipStruct = pATEInfo->pChipStruct; + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + pATEInfo->Mode = ATE_TXCARRSUPP; + + if (pChipStruct->bBBPStoreTXCARRSUPP == TRUE) + { + UINT32 bbp_index=0; + + /* Zero All BBP Value */ + for (bbp_index=0;bbp_indexbQATxStart == FALSE) + { + if (!IS_RT3883(pAd) && !IS_RT3593(pAd)) + { + /* RT3883 and RT3593 do not need BbpSoftReset() */ + /* Soft reset BBP. */ + BbpSoftReset(pAd); + } + + if (pATEInfo->TxMethod == TX_METHOD_1) + { + /* store the original value of RA_TX_PIN_CFG */ + RTMP_IO_READ32(pAd, RA_TX_PIN_CFG, &Default_TX_PIN_CFG); + + /* give RA_TX_PIN_CFG(0x1328) a proper value. */ + if (pATEInfo->Channel <= 14) + { + /* G band */ + MacData = TXCONT_TX_PIN_CFG_G; + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, MacData); + } + else + { + /* A band */ + MacData = TXCONT_TX_PIN_CFG_A; + RTMP_IO_WRITE32(pAd, RA_TX_PIN_CFG, MacData); + } + + /* Carrier Suppression set BBP R22 bit7=1 (Enable Continuous Tx Mode) */ + ATE_BBP_START_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + + /* Carrier Suppression set BBP R24 bit0=1 (TX continuously send out 5.5MHZ sin save) */ + ATE_BBP_CTS_TX_SIN_WAVE_ENABLE(pAd, BBP_R24, &BbpData); + } + else + { + /* Carrier Suppression set BBP R22 bit7=1 (Enable Continuous Tx Mode) */ + ATE_BBP_START_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + + /* Carrier Suppression set BBP R24 bit0=1 (TX continuously send out 5.5MHZ sin save) */ + ATE_BBP_CTS_TX_SIN_WAVE_ENABLE(pAd, BBP_R24, &BbpData); + + /* Set MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 1. */ + ATE_MAC_TX_CTS_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + } + } + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +static NDIS_STATUS TXFRAME( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0; +#ifdef RTMP_MAC_USB + ULONG IrqFlags = 0; +#endif /* RTMP_MAC_USB */ + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; + STRING IPGStr[8] = {0}; +#ifdef RTMP_INTERNAL_TX_ALC +#if defined(RT3350) || defined(RT3352) + UCHAR RFValue, BBP49Value; + CHAR ChannelPower = pATEInfo->TxPower0; + CHAR *TssiRefPerChannel = pATEInfo->TssiRefPerChannel; + UCHAR CurrentChannel = pATEInfo->Channel; +#endif /* defined(RT3350) || defined(RT3352) */ +#endif /* RTMP_INTERNAL_TX_ALC */ +#ifdef RTMP_TEMPERATURE_COMPENSATION +#endif /* RTMP_TEMPERATURE_COMPENSATION */ + +#ifdef RTMP_INTERNAL_TX_ALC +#if defined(RT3350) || defined(RT3352) + if (pATEInfo->bTSSICalbrEnableG == TRUE) + { + if ((!IS_RT3350(pAd)) && (!IS_RT3352(pAd))) + { + DBGPRINT_ERR(("Not support TSSI calibration since not 3350/3352 chip!!!\n")); + Status = NDIS_STATUS_FAILURE; + + return Status; + } + + /* Internal TSSI 0 */ + RFValue = (0x3 | 0x0 << 2 | 0x3 << 4); + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R27, RFValue); + + RFValue = (0x3 | 0x0 << 2); + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R28, RFValue); + + /* set BBP R49[7] = 1 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpData); + BBP49Value = BbpData; + BbpData |= 0x80; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R49, BbpData); + } +#endif /* defined(RT3350) || defined(RT3352) */ +#endif /* RTMP_INTERNAL_TX_ALC */ + +#ifdef RTMP_TEMPERATURE_COMPENSATION +#endif /* RTMP_TEMPERATURE_COMPENSATION */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s(Count=%u)\n", __FUNCTION__, pATEInfo->TxCount)); + pATEInfo->Mode |= ATE_TXFRAME; + + if (pATEInfo->bQATxStart == FALSE) + { + /* set IPG to sync tx power with QA tools */ + /* default value of IPG is 200 */ + snprintf(IPGStr, sizeof(IPGStr), "%u", pATEInfo->IPG); + DBGPRINT(RT_DEBUG_TRACE, ("IPGstr=%s\n", IPGStr)); + Set_ATE_IPG_Proc(pAd, IPGStr); + } + + +#ifdef RTMP_MAC_USB + /* Soft reset BBP. */ + BbpSoftReset(pAd); + + /* Default value in BBP R22 is 0x0. */ + ATE_BBP_RESET_TX_MODE(pAd, BBP_R22, &BbpData); + + /* Clear bit4 to stop continuous Tx production test. */ + ATE_MAC_TX_CTS_DISABLE(pAd, MAC_SYS_CTRL, &MacData); +#endif /* RTMP_MAC_USB */ + +#ifdef RALINK_QA + /* add this for LoopBack mode */ + if (pATEInfo->bQARxStart == FALSE) + { +#ifdef TXBF_SUPPORT + /* Enable Rx if Sending Sounding. Otherwise Disable */ + if (pATEInfo->txSoundingMode != 0) + { + ATE_MAC_RX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + } + else +#endif /* TXBF_SUPPORT */ + { + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + } + } + + if (pATEInfo->bQATxStart == TRUE) + { + pATEInfo->TxStatus = 1; + } +#else +#ifdef TXBF_SUPPORT + /* Enable Rx if Sending Sounding. Otherwise Disable */ + if (pATEInfo->txSoundingMode != 0) + { + ATE_MAC_RX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + } + else +#endif /* TXBF_SUPPORT */ + { + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + } +#endif /* RALINK_QA */ + + +#ifdef RTMP_MAC_USB + /* Enable Tx */ + ATE_MAC_TX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + + SetJapanFilter(pAd); + + /* Abort Tx, RX DMA. */ + RtmpDmaEnable(pAd, 0); + + pATEInfo->TxDoneCount = 0; + + /* Setup frame format. */ + ATESetUpFrame(pAd, 0); + + /* Start Tx, RX DMA. */ + RtmpDmaEnable(pAd, 1); + + /* Check count is continuous or not yet. */ + if (pATEInfo->TxCount == 0) + { + InterlockedExchange(&pAd->BulkOutRemained, 0); + } + else + { + InterlockedExchange(&pAd->BulkOutRemained, pATEInfo->TxCount); + } + + DBGPRINT(RT_DEBUG_TRACE, ("bulk out count = %d\n", atomic_read(&pAd->BulkOutRemained))); + ASSERT((atomic_read(&pAd->BulkOutRemained) >= 0)); + + if (atomic_read(&pAd->BulkOutRemained) == 0) + { + DBGPRINT(RT_DEBUG_TRACE, ("Send packet continuously\n")); + + /* NdisAcquireSpinLock() == spin_lock_bh() */ + /* NdisAcquireSpinLock only need one argument. */ + NdisAcquireSpinLock(&pAd->GenericLock); + pAd->ContinBulkOut = TRUE; + NdisReleaseSpinLock(&pAd->GenericLock); + + /* BULK_OUT_LOCK() == spin_lock_irqsave() */ + BULK_OUT_LOCK(&pAd->BulkOutLock[0], IrqFlags); + pAd->BulkOutPending[0] = FALSE; + BULK_OUT_UNLOCK(&pAd->BulkOutLock[0], IrqFlags); + } + else + { + DBGPRINT(RT_DEBUG_TRACE, ("Send packets depend on counter\n")); + + NdisAcquireSpinLock(&pAd->GenericLock); + pAd->ContinBulkOut = FALSE; + NdisReleaseSpinLock(&pAd->GenericLock); + + BULK_OUT_LOCK(&pAd->BulkOutLock[0], IrqFlags); + pAd->BulkOutPending[0] = FALSE; + BULK_OUT_UNLOCK(&pAd->BulkOutLock[0], IrqFlags); + } + + RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE); + + /* Kick bulk out */ + RTUSBKickBulkOut(pAd); +#endif /* RTMP_MAC_USB */ + +#ifdef RTMP_INTERNAL_TX_ALC +#if defined(RT3350) || defined(RT3352) + if (pATEInfo->bTSSICalbrEnableG == TRUE) + { + if ((IS_RT3350(pAd)) || (IS_RT3352(pAd))) + { + if ((pATEInfo->TxWI.MCS == 7) + && (pATEInfo->TxWI.BW == BW_20) && (pATEInfo->TxAntennaSel == 1)) + { + if (pATEInfo->Channel == 7) + { + /* step 1: get calibrated channel 7 TSSI reading as reference */ + RtmpOsMsDelay(500); + DBGPRINT(RT_DEBUG_TRACE, ("Channel %d, Calibrated Tx.Power0= 0x%04x\n", CurrentChannel, ChannelPower)); + + /* read BBP R49[4:0] and write to EEPROM 0x6E */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpData); + DBGPRINT(RT_DEBUG_TRACE, ("BBP R49 = 0x%02x\n", BbpData)); + BbpData &= 0x1f; + TssiRefPerChannel[CurrentChannel-1] = BbpData; + DBGPRINT(RT_DEBUG_TRACE, ("TSSI = 0x%02x\n", TssiRefPerChannel[CurrentChannel-1])); + } + + /* step 2: calibrate channel 1 and 13 TSSI delta values */ + else if (pATEInfo->Channel == 1) + { + /* Channel 1 */ + RtmpOsMsDelay(500); + DBGPRINT(RT_DEBUG_TRACE, ("Channel %d, Calibrated Tx.Power0= 0x%04x\n", CurrentChannel, ChannelPower)); + + /* read BBP R49[4:0] */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpData); + DBGPRINT(RT_DEBUG_TRACE, ("BBP R49 = 0x%02x\n", BbpData)); + BbpData &= 0x1f; + TssiRefPerChannel[CurrentChannel-1] = BbpData; + DBGPRINT(RT_DEBUG_TRACE, ("TSSI = 0x%02x\n", TssiRefPerChannel[CurrentChannel-1])); + } + else if (pATEInfo->Channel == 13) + { + /* Channel 13 */ + RtmpOsMsDelay(500); + DBGPRINT(RT_DEBUG_TRACE, ("Channel %d, Calibrated Tx.Power0= 0x%04x\n", CurrentChannel, ChannelPower)); + + /* read BBP R49[4:0] */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpData); + DBGPRINT(RT_DEBUG_TRACE, ("BBP R49 = 0x%02x\n", BbpData)); + BbpData &= 0x1f; + TssiRefPerChannel[CurrentChannel-1] = BbpData; + DBGPRINT(RT_DEBUG_TRACE, ("TSSI = 0x%02x\n", TssiRefPerChannel[CurrentChannel-1])); + } + else + { + DBGPRINT(RT_DEBUG_OFF, ("Channel %d, Calibrated Tx.Power0= 0x%04x\n", CurrentChannel, ChannelPower)); + } + } + } + } +#endif /* defined(RT3350) || defined(RT3352) */ +#endif /* RTMP_INTERNAL_TX_ALC */ + +#ifdef RTMP_TEMPERATURE_COMPENSATION +#endif /* RTMP_TEMPERATURE_COMPENSATION */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +static NDIS_STATUS RXFRAME( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; +#ifdef RTMP_MAC_USB + UINT32 ring_index=0; +#endif /* RTMP_MAC_USB */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + /* Disable Rx of MAC block */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + /* Default value in BBP R22 is 0x0. */ + ATE_BBP_RESET_TX_MODE(pAd, BBP_R22, &BbpData); + + + /* Clear bit4 to stop continuous Tx production test. */ + ATE_MAC_TX_CTS_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + pATEInfo->Mode |= ATE_RXFRAME; + +#ifdef RTMP_MAC_USB + /* Abort Tx, RX DMA. */ + RtmpDmaEnable(pAd, 0); +#endif /* RTMP_MAC_USB */ + + /* Disable Tx of MAC block. */ + ATE_MAC_TX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + +#ifdef RTMP_MAC_USB + /* Reset Rx RING */ + for (ring_index = 0; ring_index < (RX_RING_SIZE); ring_index++) + { + PRX_CONTEXT pRxContext = &(pAd->RxContext[ring_index]); + + pRxContext->InUse = FALSE; + pRxContext->IRPPending = FALSE; + pRxContext->Readable = FALSE; + + /* Get the URB from kernel(i.e., host control driver) back to driver. */ + RTUSB_UNLINK_URB(pRxContext->pUrb); + + /* Sleep 200 microsecs to give cancellation time to work. */ + RTMPusecDelay(200); + pAd->BulkInReq = 0; + + pAd->PendingRx = 0; + /* Next Rx Read index */ + pAd->NextRxBulkInReadIndex = 0; + /* Rx Bulk pointer */ + pAd->NextRxBulkInIndex = RX_RING_SIZE - 1; + pAd->NextRxBulkInPosition = 0; + } + + /* read to clear counters */ + RTUSBReadMACRegister(pAd, RX_STA_CNT0, &MacData); /* RX PHY & RX CRC count */ + RTUSBReadMACRegister(pAd, RX_STA_CNT1, &MacData); /* RX PLCP error count & CCA false alarm count */ + RTUSBReadMACRegister(pAd, RX_STA_CNT2, &MacData); /* RX FIFO overflow frame count & RX duplicated filtered frame count */ + + pAd->ContinBulkIn = TRUE; + + /* Enable Tx, RX DMA. */ + RtmpDmaEnable(pAd, 1); +#endif /* RTMP_MAC_USB */ + + /* Enable Rx of MAC block. */ + ATE_MAC_RX_ENABLE(pAd, MAC_SYS_CTRL, &MacData); + + +#ifdef RTMP_MAC_USB + /* Kick bulk in. */ + RTUSBBulkReceive(pAd); +#endif /* RTMP_MAC_USB */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +/* +========================================================================== + Description: + Set ATE operation mode to + 0. ATESTART = Start/Reset ATE Mode + 1. ATESTOP = Stop ATE Mode + 2. TXCARR = Transmit Carrier + 3. TXCONT = Continuous Transmit + 4. TXFRAME = Transmit Frames + 5. RXFRAME = Receive Frames +#ifdef RALINK_QA + 6. TXSTOP = Stop Any Type of Transmition + 7. RXSTOP = Stop Receiving Frames +#endif + + Return: + NDIS_STATUS_SUCCESS if all parameters are OK. +========================================================================== +*/ +static NDIS_STATUS ATECmdHandler( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + + DBGPRINT(RT_DEBUG_TRACE, ("===> %s\n", __FUNCTION__)); + +#ifdef CONFIG_RT2880_ATE_CMD_NEW + if (!strcmp(arg, "ATESTART")) + { + /* Enter/Reset ATE mode and set Tx/Rx Idle */ + Status = ATESTART(pAd); + } + else if (!strcmp(arg, "ATESTOP")) + { + /* Leave ATE mode */ + Status = ATESTOP(pAd); + } +#else + if (!strcmp(arg, "APSTOP")) + { + Status = ATESTART(pAd); + } + else if (!strcmp(arg, "APSTART")) + { + Status = ATESTOP(pAd); + } +#endif + else if (!strcmp(arg, "TXCARR")) + { + ATEAsicSwitchChannel(pAd); + /* AsicLockChannel() is empty function so far in fact */ + AsicLockChannel(pAd, pATEInfo->Channel); + RtmpOsMsDelay(5); + + Status = TXCARR(pAd); + } + else if (!strcmp(arg, "TXCARS")) + { + ATEAsicSwitchChannel(pAd); + /* AsicLockChannel() is empty function so far in fact */ + AsicLockChannel(pAd, pATEInfo->Channel); + RtmpOsMsDelay(5); + + Status = TXCARS(pAd); + } + else if (!strcmp(arg, "TXCONT")) + { + ATEAsicSwitchChannel(pAd); + /* AsicLockChannel() is empty function so far in fact */ + AsicLockChannel(pAd, pATEInfo->Channel); + RtmpOsMsDelay(5); + + Status = TXCONT(pAd); + } + else if (!strcmp(arg, "TXFRAME")) + { + + ATEAsicSwitchChannel(pAd); + /* AsicLockChannel() is empty function so far in fact */ + AsicLockChannel(pAd, pATEInfo->Channel); + RtmpOsMsDelay(5); + + Status = TXFRAME(pAd); + } + else if (!strcmp(arg, "RXFRAME")) + { + ATEAsicSwitchChannel(pAd); + /* AsicLockChannel() is empty function so far in fact */ + AsicLockChannel(pAd, pATEInfo->Channel); + RTMPusecDelay(5); + + Status = RXFRAME(pAd); + } +#ifdef RALINK_QA + /* Enter ATE mode and set Tx/Rx Idle */ + else if (!strcmp(arg, "TXSTOP")) + { + Status = TXSTOP(pAd); + } + else if (!strcmp(arg, "RXSTOP")) + { + Status = RXSTOP(pAd); + } +#endif /* RALINK_QA */ + else + { + DBGPRINT_ERR(("ATE : Invalid arg in %s!\n", __FUNCTION__)); + Status = NDIS_STATUS_INVALID_DATA; + } + RtmpOsMsDelay(5); + + DBGPRINT(RT_DEBUG_TRACE, ("<=== %s\n", __FUNCTION__)); + return Status; +} + + +INT Set_ATE_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + /* Handle ATEACTIVE and ATEPASSIVE commands as a special case */ + if (!strcmp(arg, "ATEACTIVE")) + { + pATEInfo->PassiveMode = FALSE; + return TRUE; + } + + if (!strcmp(arg, "ATEPASSIVE")) + { + pATEInfo->PassiveMode = TRUE; + return TRUE; + } + + /* Disallow all other ATE commands in passive mode */ + if (pATEInfo->PassiveMode) + return TRUE; + + if (ATECmdHandler(pAd, arg) == NDIS_STATUS_SUCCESS) + { + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + return TRUE; + } + else + { + DBGPRINT_ERR(("Set_ATE_Proc Failed\n")); + return FALSE; + } +} + + +/* +========================================================================== + Description: + Set ATE ADDR1=DA for TxFrame(AP : To DS = 0 ; From DS = 1) + or + Set ATE ADDR3=DA for TxFrame(STA : To DS = 1 ; From DS = 0) + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_DA_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + PSTRING value; + INT octet; + + /* Mac address acceptable format 01:02:03:04:05:06 length 17 */ + if (strlen(arg) != 17) + return FALSE; + + for (octet = 0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":")) + { + /* sanity check */ + if ((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1)))) + { + return FALSE; + } +#ifdef CONFIG_AP_SUPPORT + AtoH(value, &pATEInfo->Addr1[octet++], 1); +#endif /* CONFIG_AP_SUPPORT */ + + } + + /* sanity check */ + if (octet != MAC_ADDR_LEN) + { + return FALSE; + } +#ifdef CONFIG_AP_SUPPORT + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_DA_Proc (DA = %02x:%02x:%02x:%02x:%02x:%02x)\n", + pATEInfo->Addr1[0], pATEInfo->Addr1[1], pATEInfo->Addr1[2], pATEInfo->Addr1[3], + pATEInfo->Addr1[4], pATEInfo->Addr1[5])); + +#endif /* CONFIG_AP_SUPPORT */ + + + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_DA_Proc Success\n")); + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE ADDR3=SA for TxFrame(AP : To DS = 0 ; From DS = 1) + or + Set ATE ADDR2=SA for TxFrame(STA : To DS = 1 ; From DS = 0) + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_SA_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + PSTRING value; + INT octet; + + /* Mac address acceptable format 01:02:03:04:05:06 length 17 */ + if (strlen(arg) != 17) + return FALSE; + + for (octet=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":")) + { + /* sanity check */ + if ((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1)))) + { + return FALSE; + } +#ifdef CONFIG_AP_SUPPORT + AtoH(value, &pATEInfo->Addr3[octet++], 1); +#endif /* CONFIG_AP_SUPPORT */ + + } + + /* sanity check */ + if (octet != MAC_ADDR_LEN) + { + return FALSE; + } +#ifdef CONFIG_AP_SUPPORT + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_SA_Proc (SA = %02x:%02x:%02x:%02x:%02x:%02x)\n", + pATEInfo->Addr3[0], pATEInfo->Addr3[1], pATEInfo->Addr3[2], pATEInfo->Addr3[3], + pATEInfo->Addr3[4], pATEInfo->Addr3[5])); +#endif /* CONFIG_AP_SUPPORT */ + + + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_SA_Proc Success\n")); + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE ADDR2=BSSID for TxFrame(AP : To DS = 0 ; From DS = 1) + or + Set ATE ADDR1=BSSID for TxFrame(STA : To DS = 1 ; From DS = 0) + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_BSSID_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + PSTRING value; + INT octet; + + /* Mac address acceptable format 01:02:03:04:05:06 length 17 */ + if (strlen(arg) != 17) + return FALSE; + + for (octet=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":")) + { + /* sanity check */ + if ((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1)))) + { + return FALSE; + } +#ifdef CONFIG_AP_SUPPORT + AtoH(value, &pATEInfo->Addr2[octet++], 1); +#endif /* CONFIG_AP_SUPPORT */ + + } + + /* sanity check */ + if (octet != MAC_ADDR_LEN) + { + return FALSE; + } +#ifdef CONFIG_AP_SUPPORT + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_BSSID_Proc (BSSID = %02x:%02x:%02x:%02x:%02x:%02x)\n", + pATEInfo->Addr2[0], pATEInfo->Addr2[1], pATEInfo->Addr2[2], pATEInfo->Addr2[3], + pATEInfo->Addr2[4], pATEInfo->Addr2[5])); + +#endif /* CONFIG_AP_SUPPORT */ + + + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_BSSID_Proc Success\n")); + + return TRUE; +} + + + + +/* +========================================================================== + Description: + Set ATE Tx Channel + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_CHANNEL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR channel; + + + channel = simple_strtol(arg, 0, 10); + + /* to allow A band channel : ((channel < 1) || (channel > 14)) */ + if ((channel < 1) || (channel > 216)) + { + DBGPRINT_ERR(("Set_ATE_CHANNEL_Proc::Out of range, it should be in range of 1~14.\n")); + return FALSE; + } + + pATEInfo->Channel = channel; + + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_CHANNEL_Proc (ATE Channel = %d)\n", pATEInfo->Channel)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_CHANNEL_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Initialize the channel - set the power and switch to selected channel + 0 => use current value + else set channel to specified channel + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_INIT_CHAN_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + int index; + int value; + + /* Get channel parameter */ + value = simple_strtol(arg, 0, 10); + + if (value<0 || value>216) + { + DBGPRINT_ERR(("Set_ATE_INIT_CHAN_Proc::Channel out of range\n")); + return FALSE; + } + + if (value != 0) + pATEInfo->Channel = value; + + for (index=0; indexChannel == pAd->TxPower[index].Channel) + { + pATEInfo->TxPower0 = pAd->TxPower[index].Power; + pATEInfo->TxPower1 = pAd->TxPower[index].Power2; +#ifdef DOT11N_SS3_SUPPORT + if (IS_RT2883(pAd) || IS_RT3593(pAd) || IS_RT3883(pAd)) + pATEInfo->TxPower2 = pAd->TxPower[index].Power3; +#endif /* DOT11N_SS3_SUPPORT */ + break; + } + } + + if (index == MAX_NUM_OF_CHANNELS) + { + DBGPRINT_ERR(("Set_ATE_INIT_CHAN_Proc::Channel not found\n")); + return FALSE; + } + + /* Force non-QATool mode */ + pATEInfo->bQATxStart = pATEInfo->bQARxStart = FALSE; + + ATETxPwrHandler(pAd, 0); + ATETxPwrHandler(pAd, 1); +#ifdef DOT11N_SS3_SUPPORT + ATETxPwrHandler(pAd, 2); +#endif /* DOT11N_SS3_SUPPORT */ + + + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_INIT_CHAN_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Tx Power + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +static INT ATESetAntennaTxPower( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg, + IN INT Antenna) + +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR TxPower; + INT index, maximun_index; + + pATEInfo = &(pAd->ate); + TxPower = simple_strtol(arg, 0, 10); + index = Antenna; + maximun_index = pAd->Antenna.field.TxPath - 1; + + if ((index < 0) || (index > maximun_index)) + { + DBGPRINT_ERR(("No such antenna! The range is 0~%d.\n", maximun_index)); + return FALSE; + } + + if (pATEInfo->Channel <= 14) /* 2.4 GHz */ + { +#ifdef MT7601 + if (IS_MT7601(pAd)) + { + CHAR MaxPower; + UINT32 RegValue = 0; + + RTMP_IO_READ32(pAd, TX_ALC_CFG_0, &RegValue); + MaxPower = (RegValue & 0x003F0000) >> 16; + if (TxPower > MaxPower ) + { + DBGPRINT_ERR(("Set_ATE_TX_POWER%d_Proc::Out of range! (Value=%d)\n", index, TxPower)); + DBGPRINT_ERR(("TxPower range is 0~39 in G band.\n")); + return FALSE; + } + } + else +#endif /* MT7601 */ + if (!IS_RT3390(pAd)) + { + if ((TxPower > 31) || (TxPower < 0)) + { + DBGPRINT_ERR(("Set_ATE_TX_POWER%d_Proc::Out of range! (Value=%d)\n", index, TxPower)); + DBGPRINT_ERR(("TxPower range is 0~31 in G band.\n")); + return FALSE; + } + } + } + else /* 5.5 GHz */ + { + if ((TxPower > (pATEInfo->MaxTxPowerBandA)) || (TxPower < (pATEInfo->MinTxPowerBandA))) + { + DBGPRINT_ERR(("Set_ATE_TX_POWER%d_Proc::Out of range! (Value=%d)\n", index, TxPower)); + DBGPRINT_ERR(("TxPower range is %d~%d in A band.\n", pATEInfo->MinTxPowerBandA, pATEInfo->MaxTxPowerBandA)); + return FALSE; + } + } + + switch (index) + { + case 0: + pATEInfo->TxPower0 = TxPower; + break; + case 1: + pATEInfo->TxPower1 = TxPower; + break; +#ifdef DOT11N_SS3_SUPPORT + case 2: + pATEInfo->TxPower2 = TxPower; + break; +#endif /* DOT11N_SS3_SUPPORT */ + default: + return FALSE; + } + + ATETxPwrHandler(pAd, index); + + + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_POWER%d_Proc Success\n", index)); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Tx Power0 + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_POWER0_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + INT ret; + + ret = ATESetAntennaTxPower(pAd, arg, 0); + return ret; +} + + +/* +========================================================================== + Description: + Set ATE Tx Power1 + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_POWER1_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + INT ret; + + ret = ATESetAntennaTxPower(pAd, arg, 1); + return ret; +} + + +#ifdef DOT11N_SS3_SUPPORT +/* +========================================================================== + Description: + Set ATE Tx Power2 + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_POWER2_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + INT ret; + + ret = ATESetAntennaTxPower(pAd, arg, 2); + return ret; +} +#endif /* DOT11N_SS3_SUPPORT */ + + +/* +========================================================================== + Description: + Set ATE Tx Antenna + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_Antenna_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR value; + INT maximun_index = pAd->Antenna.field.TxPath; + + value = simple_strtol(arg, 0, 10); + + if ((value > maximun_index) || (value < 0)) + { + DBGPRINT_ERR(("Set_ATE_TX_Antenna_Proc::Out of range (Value=%d)\n", value)); + DBGPRINT_ERR(("Set_ATE_TX_Antenna_Proc::The range is 0~%d\n", maximun_index)); + + return FALSE; + } + + pATEInfo->TxAntennaSel = value; + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_Antenna_Proc (Antenna = %d)\n", pATEInfo->TxAntennaSel)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_Antenna_Proc Success\n")); + + /* calibration power unbalance issues */ + ATEAsicSwitchChannel(pAd); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Rx Antenna + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_RX_Antenna_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR value; + INT maximun_index = pAd->Antenna.field.RxPath; + + value = simple_strtol(arg, 0, 10); + + if ((value > maximun_index) || (value < 0)) + { + DBGPRINT_ERR(("Set_ATE_RX_Antenna_Proc::Out of range (Value=%d)\n", value)); + DBGPRINT_ERR(("Set_ATE_RX_Antenna_Proc::The range is 0~%d\n", maximun_index)); + + return FALSE; + } + + pATEInfo->RxAntennaSel = value; + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_Antenna_Proc (Antenna = %d)\n", pATEInfo->RxAntennaSel)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_Antenna_Proc Success\n")); + + /* calibration power unbalance issues */ + ATEAsicSwitchChannel(pAd); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +VOID DefaultATEAsicExtraPowerOverMAC( + IN PRTMP_ADAPTER pAd) +{ + ULONG ExtraPwrOverMAC = 0; + ULONG ExtraPwrOverTxPwrCfg7 = 0, ExtraPwrOverTxPwrCfg8 = 0, ExtraPwrOverTxPwrCfg9 = 0; + + /* For OFDM_54 and HT_MCS_7, extra fill the corresponding register value into MAC 0x13D4 */ + RTMP_IO_READ32(pAd, 0x1318, &ExtraPwrOverMAC); + ExtraPwrOverTxPwrCfg7 |= (ExtraPwrOverMAC & 0x0000FF00) >> 8; /* Get Tx power for OFDM 54 */ + RTMP_IO_READ32(pAd, 0x131C, &ExtraPwrOverMAC); + ExtraPwrOverTxPwrCfg7 |= (ExtraPwrOverMAC & 0x0000FF00) << 8; /* Get Tx power for HT MCS 7 */ + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_7, ExtraPwrOverTxPwrCfg7); + + /* For STBC_MCS_7, extra fill the corresponding register value into MAC 0x13DC */ + RTMP_IO_READ32(pAd, 0x1324, &ExtraPwrOverMAC); + ExtraPwrOverTxPwrCfg9 |= (ExtraPwrOverMAC & 0x0000FF00) >> 8; /* Get Tx power for STBC MCS 7 */ + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_9, ExtraPwrOverTxPwrCfg9); + + if (IS_RT5392(pAd)) + { + /* For HT_MCS_15, extra fill the corresponding register value into MAC 0x13DC */ + RTMP_IO_READ32(pAd, 0x1320, &ExtraPwrOverMAC); + ExtraPwrOverTxPwrCfg8 |= (ExtraPwrOverMAC & 0x0000FF00) >> 8; /* Get Tx power for HT MCS 15 */ + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_8, ExtraPwrOverTxPwrCfg8); + + DBGPRINT(RT_DEBUG_TRACE, ("Offset =0x13D8, TxPwr = 0x%08X, ", (UINT)ExtraPwrOverTxPwrCfg8)); + } + + DBGPRINT(RT_DEBUG_TRACE, ("Offset = 0x13D4, TxPwr = 0x%08X, Offset = 0x13DC, TxPwr = 0x%08X\n", + (UINT)ExtraPwrOverTxPwrCfg7, + (UINT)ExtraPwrOverTxPwrCfg9)); +} + + +VOID ATEAsicExtraPowerOverMAC( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->AsicExtraPowerOverMAC!= NULL) + pATEInfo->pChipStruct->AsicExtraPowerOverMAC(pAd); + + return; +} + + +VOID ATEAsicTemperCompensation( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->TemperCompensation!= NULL) + pATEInfo->pChipStruct->TemperCompensation(pAd); + + return; +} + + +#ifdef RT3350 +/* +========================================================================== + Description: + Set ATE PA bias to improve EVM + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_PA_Bias_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR PABias = 0; + UCHAR RFValue; + + PABias = simple_strtol(arg, 0, 10); + + if (PABias >= 16) + { + DBGPRINT_ERR(("Set_ATE_PA_Bias_Proc::Out of range, it should be in range of 0~15.\n")); + return FALSE; + } + + pATEInfo->PABias = PABias; + + ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R19, (PUCHAR)&RFValue); + RFValue = (((RFValue & 0x0F) | (pATEInfo->PABias << 4))); + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R19, (UCHAR)RFValue); + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_PA_Bias_Proc (PABias = %d)\n", pATEInfo->PABias)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_PA_Bias_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} +#endif /* RT3350 */ + + +/* +========================================================================== + Description: + Set ATE RF BW(default) + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Default_Set_ATE_TX_FREQ_OFFSET_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR RFFreqOffset = 0; + + + RFFreqOffset = simple_strtol(arg, 0, 10); + + if (RFFreqOffset >= 64) + { + DBGPRINT_ERR(("Set_ATE_TX_FREQ_OFFSET_Proc::Out of range(0 ~ 63).\n")); + return FALSE; + } + + pATEInfo->RFFreqOffset = RFFreqOffset; + + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_FREQOFFSET_Proc (RFFreqOffset = %d)\n", pATEInfo->RFFreqOffset)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_FREQOFFSET_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE RF frequence offset + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_FREQ_OFFSET_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + INT ret = FALSE; + + if (pATEInfo->pChipStruct->Set_FREQ_OFFSET_Proc != NULL) + { + ret = pATEInfo->pChipStruct->Set_FREQ_OFFSET_Proc(pAd, arg); + } + + if (ret == TRUE) + { + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_FREQ_OFFSET_Proc (RFFreqOffset = %d)\n", pATEInfo->RFFreqOffset)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_FREQ_OFFSET_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + } + + return ret; +} + + +/* +========================================================================== + Description: + Set ATE RF BW(default) + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Default_Set_ATE_TX_BW_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + INT powerIndex; + UCHAR value = 0; + UCHAR BBPCurrentBW; + + BBPCurrentBW = simple_strtol(arg, 0, 10); + + if ((BBPCurrentBW == 0) + ) + { + pATEInfo->TxWI.TxWIBW = BW_20; + } + else + { + pATEInfo->TxWI.TxWIBW = BW_40; + } + + if ((pATEInfo->TxWI.TxWIPHYMODE == MODE_CCK) && (pATEInfo->TxWI.TxWIBW == BW_40)) + { + DBGPRINT_ERR(("Set_ATE_TX_BW_Proc!! Warning!! CCK only supports 20MHZ!!\n")); + DBGPRINT_ERR(("Bandwidth switch to 20!!\n")); + pATEInfo->TxWI.TxWIBW = BW_20; + } + + if (pATEInfo->TxWI.TxWIBW == BW_20) + { + if (pATEInfo->Channel <= 14) + { + /* BW=20;G band */ + for (powerIndex=0; powerIndexTx20MPwrCfgGBand[powerIndex] == 0xffffffff) + continue; + + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgGBand[powerIndex]); + RtmpOsMsDelay(5); + } + } + else + { + /* BW=20;A band */ + for (powerIndex=0; powerIndexTx20MPwrCfgABand[powerIndex] == 0xffffffff) + continue; + + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgABand[powerIndex]); + RtmpOsMsDelay(5); + } + } + + /* set BW = 20 MHz */ + /* Set BBP R4 bit[4:3]=0:0 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value); + value &= (~0x18); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value); + + /* Set BBP R66=0x3C */ + value = 0x3C; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value); + + /* set BW = 20 MHz */ + { + pAd->LatchRfRegs.R4 &= ~0x00200000; + RtmpRfIoWrite(pAd); + } + + /* BW = 20 MHz */ + /* Set BBP R68=0x0B to improve Rx sensitivity. */ + value = 0x0B; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value); + /* Set BBP R69=0x16 */ + value = 0x16; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value); + /* Set BBP R70=0x08 */ + value = 0x08; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value); + /* Set BBP R73=0x11 */ + if ( IS_RT5390(pAd) || IS_RT5392(pAd)) + value = 0x13; + else + value = 0x11; + + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value); + + + if (pATEInfo->Channel == 14) + { + INT TxMode = pATEInfo->TxWI.TxWIPHYMODE; + + if (TxMode == MODE_CCK) + { + /* when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value); + value |= 0x20; /* set bit5=1 */ + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value); + } + } + } + /* If bandwidth = 40M, set RF Reg4 bit 21 = 0. */ + else if (pATEInfo->TxWI.TxWIBW == BW_40) + { + if (pATEInfo->Channel <= 14) + { + /* BW=40;G band */ + for (powerIndex=0; powerIndexTx40MPwrCfgGBand[powerIndex] == 0xffffffff) + continue; + + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgGBand[powerIndex]); + RtmpOsMsDelay(5); + } + } + else + { + /* BW=40;A band */ + for (powerIndex=0; powerIndexTx40MPwrCfgABand[powerIndex] == 0xffffffff) + continue; + + RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgABand[powerIndex]); + RtmpOsMsDelay(5); + } + + if ((pATEInfo->TxWI.TxWIPHYMODE >= 2) && (pATEInfo->TxWI.TxWIMCS == 7)) + { + value = 0x28; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R67, value); + } + } + + /* Set BBP R4 bit[4:3]=1:0 */ + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value); + value &= (~0x18); + value |= 0x10; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value); + + /* Set BBP R66=0x3C */ + value = 0x3C; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value); + + + /* Set BBP R68=0x0C to improve Rx sensitivity. */ + value = 0x0C; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value); + /* Set BBP R69=0x1A */ + value = 0x1A; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value); + /* Set BBP R70=0x0A */ + value = 0x0A; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value); + /* Set BBP R73=0x16 */ + if (IS_RT5390(pAd) || IS_RT5392(pAd)) + value = 0x13; + else + value = 0x16; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value); + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_BW_Proc (BBPCurrentBW = %d)\n", pATEInfo->TxWI.TxWIBW)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_BW_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE RF BW + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_BW_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->Set_BW_Proc != NULL) + pATEInfo->pChipStruct->Set_BW_Proc(pAd, arg); + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_BW_Proc (BBPCurrentBW = %d)\n", pATEInfo->TxWI.TxWIBW)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_BW_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Tx frame length + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_LENGTH_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + pATEInfo->TxLength = simple_strtol(arg, 0, 10); + + if ((pATEInfo->TxLength < 24) || (pATEInfo->TxLength > (MAX_FRAME_SIZE - 34/* == 2312 */))) + { + pATEInfo->TxLength = (MAX_FRAME_SIZE - 34/* == 2312 */); + DBGPRINT_ERR(("Set_ATE_TX_LENGTH_Proc::Out of range, it should be in range of 24~%d.\n", (MAX_FRAME_SIZE - 34/* == 2312 */))); + return FALSE; + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_LENGTH_Proc (TxLength = %d)\n", pATEInfo->TxLength)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_LENGTH_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Tx frame count + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_COUNT_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + pATEInfo->TxCount = simple_strtol(arg, 0, 10); + + if (pATEInfo->TxCount == 0) + { + pATEInfo->TxCount = 0xFFFFFFFF; + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_COUNT_Proc (TxCount = %d)\n", pATEInfo->TxCount)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_COUNT_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Tx frame MCS + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_MCS_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR MCS; + INT result; + + MCS = simple_strtol(arg, 0, 10); + result = CheckMCSValid(pAd, pATEInfo->TxWI.TxWIPHYMODE, MCS); + + if (result != -1) + { + pATEInfo->TxWI.TxWIMCS = (UCHAR)MCS; + } + else + { + DBGPRINT_ERR(("Set_ATE_TX_MCS_Proc::Out of range, refer to rate table.\n")); + return FALSE; + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MCS_Proc (MCS = %d)\n", pATEInfo->TxWI.TxWIMCS)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MCS_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Tx frame Mode + 0: MODE_CCK + 1: MODE_OFDM + 2: MODE_HTMIX + 3: MODE_HTGREENFIELD + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_MODE_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR BbpData = 0; + + pATEInfo->TxWI.TxWIPHYMODE = simple_strtol(arg, 0, 10); + + if (pATEInfo->TxWI.TxWIPHYMODE > 3) + { + pATEInfo->TxWI.TxWIPHYMODE = 0; + DBGPRINT_ERR(("Set_ATE_TX_MODE_Proc::Out of range.\nIt should be in range of 0~3\n")); + DBGPRINT(RT_DEBUG_OFF, ("0: CCK, 1: OFDM, 2: HT_MIX, 3: HT_GREEN_FIELD.\n")); + return FALSE; + } + +#if defined(RT5592) || defined(MT7601) + /* Turn on BBP 20MHz mode by request here. */ + if (IS_RT5592(pAd) || IS_MT7601(pAd)) + { + if (pATEInfo->TxWI.TxWIBW == BW_20) + { + BbpData = 0x40; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData); + } + else /* BW == 40MHz */ + { + BbpData = 0x50; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData); + } + } + //else +#endif /* defined(RT5592) || defined(MT7601) */ + /* Turn on BBP 20MHz mode by request here. */ + if (pATEInfo->TxWI.TxWIPHYMODE == MODE_CCK) + { + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BbpData); + BbpData &= (~0x18); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData); + pATEInfo->TxWI.TxWIBW = BW_20; + DBGPRINT(RT_DEBUG_OFF, ("Set_ATE_TX_MODE_Proc::CCK Only support 20MHZ. Switch to 20MHZ.\n")); + } + +#ifdef RT3350 + if (IS_RT3350(pAd)) + { + if (pATEInfo->TxWI.TxWIPHYMODE == MODE_CCK) + { + USHORT value; + UCHAR rf_offset; + UCHAR rf_value; + + RT28xx_EEPROM_READ16(pAd, 0x126, value); + rf_value = value & 0x00FF; + rf_offset = (value & 0xFF00) >> 8; + + if(rf_offset == 0xff) + rf_offset = RF_R21; + if(rf_value == 0xff) + rf_value = 0x4F; + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, rf_offset, (UCHAR)rf_value); + + RT28xx_EEPROM_READ16(pAd, 0x12a, value); + rf_value = value & 0x00FF; + rf_offset = (value & 0xFF00) >> 8; + + if(rf_offset == 0xff) + rf_offset = RF_R29; + if(rf_value == 0xff) + rf_value = 0x07; + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, rf_offset, (UCHAR)rf_value); + + + /* set RF_R24 */ + if (pATEInfo->TxWI.BW == BW_40) + { + value = 0x3F; + } + else + { + value = 0x1F; + } + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR)value); + } + else + { + USHORT value; + UCHAR rf_offset; + UCHAR rf_value; + + RT28xx_EEPROM_READ16(pAd, 0x124, value); + rf_value = value & 0x00FF; + rf_offset = (value & 0xFF00) >> 8; + + if(rf_offset == 0xff) + rf_offset = RF_R21; + if(rf_value == 0xff) + rf_value = 0x6F; + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, rf_offset, (UCHAR)rf_value); + + RT28xx_EEPROM_READ16(pAd, 0x128, value); + rf_value = value & 0x00FF; + rf_offset = (value & 0xFF00) >> 8; + + if(rf_offset == 0xff) + rf_offset = RF_R29; + if(rf_value == 0xff) + rf_value = 0x07; + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, rf_offset, (UCHAR)rf_value); + + /* set RF_R24 */ + if (pATEInfo->TxWI.BW == BW_40) + { + value = 0x28; + } + else + { + value = 0x18; + } + ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR)value); + } + } +#endif /* RT3350 */ + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MODE_Proc (TxMode = %d)\n", pATEInfo->TxWI.TxWIPHYMODE)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MODE_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE Tx frame GI + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TX_GI_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + pATEInfo->TxWI.TxWIShortGI = simple_strtol(arg, 0, 10); + + if (pATEInfo->TxWI.TxWIShortGI > 1) + { + pATEInfo->TxWI.TxWIShortGI = 0; + DBGPRINT_ERR(("Set_ATE_TX_GI_Proc::Out of range\n")); + return FALSE; + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_GI_Proc (GI = %d)\n", pATEInfo->TxWI.TxWIShortGI)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_GI_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +INT Set_ATE_RX_FER_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + pATEInfo->bRxFER = simple_strtol(arg, 0, 10); + + if (pATEInfo->bRxFER == 1) + { + pATEInfo->RxCntPerSec = 0; + pATEInfo->RxTotalCnt = 0; + } + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_FER_Proc (bRxFER = %d)\n", pATEInfo->bRxFER)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_FER_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +INT Set_ATE_Read_RF_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + { + DBGPRINT(RT_DEBUG_OFF, ("R1 = %x\n", pAd->LatchRfRegs.R1)); + DBGPRINT(RT_DEBUG_OFF, ("R2 = %x\n", pAd->LatchRfRegs.R2)); + DBGPRINT(RT_DEBUG_OFF, ("R3 = %x\n", pAd->LatchRfRegs.R3)); + DBGPRINT(RT_DEBUG_OFF, ("R4 = %x\n", pAd->LatchRfRegs.R4)); + } + return TRUE; +} + + +INT Set_ATE_Write_RF1_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UINT32 value = (UINT32) simple_strtol(arg, 0, 16); + + pAd->LatchRfRegs.R1 = value; + RtmpRfIoWrite(pAd); + + return TRUE; +} + + +INT Set_ATE_Write_RF2_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UINT32 value = (UINT32) simple_strtol(arg, 0, 16); + + pAd->LatchRfRegs.R2 = value; + RtmpRfIoWrite(pAd); + + return TRUE; +} + + +INT Set_ATE_Write_RF3_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UINT32 value = (UINT32) simple_strtol(arg, 0, 16); + + pAd->LatchRfRegs.R3 = value; + RtmpRfIoWrite(pAd); + + return TRUE; +} + + +INT Set_ATE_Write_RF4_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UINT32 value = (UINT32) simple_strtol(arg, 0, 16); + + pAd->LatchRfRegs.R4 = value; + RtmpRfIoWrite(pAd); + + return TRUE; +} + + +/* +========================================================================== + Description: + Load and Write EEPROM from a binary file prepared in advance. + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_Load_E2P_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + BOOLEAN ret = FALSE; + PSTRING src = EEPROM_BIN_FILE_NAME; + RTMP_OS_FD srcf; + INT32 retval; + USHORT WriteEEPROM[(EEPROM_SIZE >> 1)]; + INT FileLength = 0; + UINT32 value = (UINT32) simple_strtol(arg, 0, 10); + RTMP_OS_FS_INFO osFSInfo; + + DBGPRINT(RT_DEBUG_OFF, ("===> %s (value=%d)\n\n", __FUNCTION__, value)); + + if (value > 0) + { + /* zero the e2p buffer */ + NdisZeroMemory((PUCHAR)WriteEEPROM, EEPROM_SIZE); + + RtmpOSFSInfoChange(&osFSInfo, TRUE); + + do + { + /* open the bin file */ + srcf = RtmpOSFileOpen(src, O_RDONLY, 0); + + if (IS_FILE_OPEN_ERR(srcf)) + { + DBGPRINT_ERR(("%s - Error opening file %s\n", __FUNCTION__, src)); + break; + } + + /* read the firmware from the file *.bin */ + FileLength = RtmpOSFileRead(srcf, (PSTRING)WriteEEPROM, EEPROM_SIZE); + + if (FileLength != EEPROM_SIZE) + { + DBGPRINT_ERR(("%s : error file length (=%d) in e2p.bin\n", + __FUNCTION__, FileLength)); + break; + } + else + { + /* write the content of .bin file to EEPROM */ + rt_ee_write_all(pAd, WriteEEPROM); + ret = TRUE; + } + break; + } while(TRUE); + + /* close firmware file */ + if (IS_FILE_OPEN_ERR(srcf)) + { + ; + } + else + { + retval = RtmpOSFileClose(srcf); + + if (retval) + { + DBGPRINT_ERR(("--> Error %d closing %s\n", -retval, src)); + + } + } + + /* restore */ + RtmpOSFSInfoChange(&osFSInfo, FALSE); + } + + DBGPRINT(RT_DEBUG_OFF, ("<=== %s (ret=%d)\n", __FUNCTION__, ret)); + + return ret; +} + + +#ifdef RTMP_EFUSE_SUPPORT +/* +========================================================================== + Description: + Load and Write E-Fuse from pAd->EEPROMImage. + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_Load_E2P_From_Buf_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + BOOLEAN ret = FALSE; + UINT32 value = (UINT32) simple_strtol(arg, 0, 10); + + DBGPRINT(RT_DEBUG_OFF, ("===> %s (value=%d)\n\n", __FUNCTION__, value)); + + if (value > 0) + { + + rt_ee_write_all(pAd, pAd->EEPROMImage); + ret = TRUE; + + } + + DBGPRINT(RT_DEBUG_OFF, ("<=== %s (ret=%d)\n", __FUNCTION__, ret)); + + return ret; +} + + +INT Set_ATE_Cal_Free_Info_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + BOOLEAN ret = FALSE; + + if ( pAd->bCalFreeIC ) + DBGPRINT(RT_DEBUG_OFF, ("%s (bCalFreeIC=TRUE)\n\n", __FUNCTION__)); + else + DBGPRINT(RT_DEBUG_OFF, ("%s (bCalFreeIC=FALSE)\n\n", __FUNCTION__)); + + return TRUE; +} + +#endif /* RTMP_EFUSE_SUPPORT */ + + +INT Set_ATE_Read_E2P_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + USHORT buffer[EEPROM_SIZE >> 1]; + USHORT *p; + int i; + + rt_ee_read_all(pAd, (USHORT *)buffer); + p = buffer; + for (i = 0; i < (EEPROM_SIZE >> 1); i++) + { + DBGPRINT(RT_DEBUG_OFF, ("%4.4x ", *p)); + if (((i+1) % 16) == 0) + DBGPRINT(RT_DEBUG_OFF, ("\n")); + p++; + } + return TRUE; +} + + +#ifdef LED_CONTROL_SUPPORT +#endif /* LED_CONTROL_SUPPORT */ + + +/* +========================================================================== + Description: + Enable ATE auto Tx alc (Tx auto level control). + According to the chip temperature, auto adjust the transmit power. + + 0: disable + 1: enable + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_AUTO_ALC_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 value = simple_strtol(arg, 0, 10); + + if (value > 0) + { + pATEInfo->bAutoTxAlc = TRUE; + DBGPRINT(RT_DEBUG_TRACE, ("ATEAUTOALC = TRUE , auto alc enabled!\n")); + } + else + { + pATEInfo->bAutoTxAlc = FALSE; + DBGPRINT(RT_DEBUG_TRACE, ("ATEAUTOALC = FALSE , auto alc disabled!\n")); + } + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +#ifdef TXBF_SUPPORT +/* +========================================================================== + Description: + Set ATE Tx Beamforming mode + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TXBF_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR value; + + value = simple_strtol(arg, 0, 10); + + switch (value) + { + case 0: + /* no BF */ + pATEInfo->TxWI.iTxBF = pATEInfo->TxWI.eTxBF = 0; + break; + case 1: + /* ETxBF */ + pATEInfo->TxWI.eTxBF = 1; + break; + case 2: + /* ITxBF */ + pATEInfo->TxWI.iTxBF = 1; + break; + case 3: + /* Enable TXBF support */ + pATEInfo->bTxBF = TRUE; + break; + case 4: + /* Disable TXBF support */ + pATEInfo->bTxBF = FALSE; + break; + default: + DBGPRINT_ERR(("Set_ATE_TXBF_Proc: Invalid parameter %d\n", value)); + break; + } + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; + } + + +/* +========================================================================== + Description: + Set ATE Sounding type + 0 => no sounding + 1 => Data sounding + 2 => 2 stream NDP sounding + 3 => 3 stream NDP Sounding + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TXSOUNDING_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + CHAR value; + + value = simple_strtol(arg, 0, 10); + + if (value<0 || value>3) + { + DBGPRINT_ERR(("Set_ATE_TXSOUNDING_Proc: Invalid parameter %d\n", value)); + return FALSE; + } + + pATEInfo->txSoundingMode = value; + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Do a Divider Calibration on calibration channels and save in EEPROM + 0 => do G and A band + 1 => G band only + 2 => A band only + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TXBF_DIVCAL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + int value; + ITXBF_DIV_PARAMS divParams; + CHAR initChanArg[] = "0"; + + value = simple_strtol(arg, 0, 10); + + if (value<0 || value>2) + return FALSE; + + /* G band */ + if (value==0 || value==1) + { + pATEInfo->Channel = 1; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFDividerCalibration(pAd, 1, 0, NULL); + + pATEInfo->Channel = 14; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFDividerCalibration(pAd, 1, 0, NULL); + + /* Display delta phase information */ + ITxBFGetEEPROM(pAd, NULL, NULL, &divParams); + + DBGPRINT(RT_DEBUG_WARN, ("Divider Cal Done:\n" + "ch1-ch14 = [%2d, %2d] degrees\n" + "ant0-ant2 = [%2d, %2d] degrees\n", + (UCHAR)(divParams.gBeg[0]-divParams.gEnd[0])*360/256, + (UCHAR)(divParams.gBeg[1]-divParams.gEnd[1])*360/256, + (UCHAR)(divParams.gBeg[0]-divParams.gBeg[1])*360/256, + (UCHAR)(divParams.gEnd[0]-divParams.gEnd[1])*360/256) ); + } + + /* A Band */ + if (value==0 || value==2) + { + pATEInfo->Channel = 36; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFDividerCalibration(pAd, 1, 0, NULL); + + pATEInfo->Channel = 120; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFDividerCalibration(pAd, 1, 0, NULL); + + pATEInfo->Channel = 165; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFDividerCalibration(pAd, 1, 0, NULL); + } + + return TRUE; +} + + +/* +========================================================================== + Description: + Do a LNA Calibration on calibration channels and save in EEPROM + 0 => do G and A band + 1 => G band only + 2 => A band only + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_TXBF_LNACAL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + int value; + int i; + CHAR initChanArg[] = "0"; + + value = simple_strtol(arg, 0, 10); + + if (value<0 || value>2) + return FALSE; + + /* G Band */ + if (value==0 || value==1) + { + pATEInfo->Channel = 1; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFLNACalibration(pAd, 1, 0, TRUE); + + pATEInfo->Channel = 14; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFLNACalibration(pAd, 1, 0, TRUE); + } + + /* A Band */ + if (value==0 || value==2) + { + static UCHAR channels[6] = {36, 64, 100, 128, 132, 165}; + for (i=0; i<6; i++) + { + pATEInfo->Channel = channels[i]; + Set_ATE_INIT_CHAN_Proc(pAd, initChanArg); + ITxBFLNACalibration(pAd, 1, 0, FALSE); + } + } + + return TRUE; +} + + +/* +========================================================================== + Description: + Sanity check for the channel of Implicit TxBF calibration. + + Return: + TRUE if all parameters are OK, FALSE otherwise + + Note: + 1. This sanity check function only work for Implicit TxBF calibration. + 2. Currently supported channels are: + 1, 14, 36, 64, 128, 132, 165 +========================================================================== +*/ +static BOOLEAN rtmp_ate_txbf_cal_valid_ch( + IN RTMP_ADAPTER *pAd, + IN UCHAR channel) +{ + BOOLEAN bValidCh; + + /* TODO: shall we check the capability of the chipset here ?? */ + switch (channel) + { + case 1: + case 14: +#ifdef A_BAND_SUPPORT + case 36: + case 64: + case 100: + case 128: + case 132: + case 165: +#endif /* A_BAND_SUPPORT */ + bValidCh = TRUE; + break; + default: + bValidCh = FALSE; + break; + } + + return bValidCh; +} + + +/* +========================================================================== + Description: + Set to start the initialization procedures of iTxBf calibration in DUT side + 0 => do nothing + 1 => do following initializations + + Return: + TRUE if all parameters are OK, FALSE otherwise + + Note: + This cmd shall only used in DUT side for calibration +========================================================================== +*/ +INT Set_ATE_TXBF_INIT_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + int val; + USHORT eepromVal; + UCHAR cmdStr[32]; + + val = simple_strtol(arg, 0, 10); + if (val != 1) + return FALSE; + + /* Do ATESTART */ +#ifdef CONFIG_RT2880_ATE_CMD_NEW + Set_ATE_Proc(pAd, "ATESTART"); +#else + Set_ATE_Proc(pAd, "APSTOP"); +#endif /* CONFIG_RT2880_ATE_CMD_NEW */ + + /* set ATETXBF=3 */ + Set_ATE_TXBF_Proc(pAd, "3"); + + + /* Set self mac address as 22:22:22:22:22:22 */ + RTMP_IO_WRITE32(pAd, 0x1008, 0x22222222); + RTMP_IO_WRITE32(pAd, 0x100c, 0x00002222); + + /* set ATEDA=11:11:11:11:11:11 */ + /* set ATESA=22:22:22:22:22:22 */ + /* set ATEBSSID=22:22:22:22:22:22 */ + for (val = 0; val < MAC_ADDR_LEN; val++) + { + pATEInfo->Addr1[val] = 0x11; /* the RA */ + pATEInfo->Addr2[val] = 0x22; /* the TA */ + pATEInfo->Addr3[val] = 0x22; /* the BSSID */ + } + + /* set ATETXMODE=2 */ + Set_ATE_TX_MODE_Proc(pAd, "2"); + + /* set ATETXMCS=16 */ + Set_ATE_TX_MCS_Proc(pAd, "16"); + + /* set ATETXBW=0 */ + Set_ATE_TX_BW_Proc(pAd, "0"); + + /* set ATETXGI=0 */ + Set_ATE_TX_GI_Proc(pAd, "0"); + + /* set ATETXANT=0 */ + Set_ATE_TX_Antenna_Proc(pAd, "0"); + + /* set ATERXANT=0 */ + Set_ATE_RX_Antenna_Proc(pAd, "0"); + + /* set ATETXFREQOFFSET=eeprom */ + /* read EEPROM Frequency offset from EEPROM and set it to BBP */ + RT28xx_EEPROM_READ16(pAd, 0x44, eepromVal); + snprintf(cmdStr, sizeof(cmdStr), "%d\n", (eepromVal & 0xff)); + Set_ATE_TX_FREQ_OFFSET_Proc(pAd, cmdStr); + + /* bbp 65=29 */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R65, 0x29); + + /* bbp 163=bd */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R163, 0xbd); + + /* bbp 173=28 */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R173, 0x28); + + return TRUE; +} + + +/* +========================================================================== + Description: + Set to do iTxBF calibration procedures for specific channel, following show us the supported channels. + 1, 14, 36, 64, 128, 132, 165 + + Return: + TRUE if all parameters are OK, FALSE otherwise + + Note: + This cmd shall only used in DUT side for calibration +========================================================================== +*/ +INT Set_ATE_TXBF_CAL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR ch; + UCHAR cmdStr[32]; + + ch = simple_strtol(arg, 0, 10); + if (rtmp_ate_txbf_cal_valid_ch(pAd, ch) == FALSE) + return FALSE; + + /* iwpriv ra0 set ATECHANNEL=Channel */ + snprintf(cmdStr, sizeof(cmdStr), "%d\n", ch); + if (Set_ATE_CHANNEL_Proc(pAd, cmdStr) == FALSE) + return FALSE; + + /* iwpriv ra0 set ATEINITCHAN =0 */ + if (Set_ATE_INIT_CHAN_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXSOUNDING=3 */ + if (Set_ATE_TXSOUNDING_Proc(pAd, "3") == FALSE) + return FALSE; + + /* iwpriv ra0 set ETxBfNoncompress=0 */ + if (Set_ETxBfNoncompress_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXMCS=0 */ + if (Set_ATE_TX_MCS_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXCNT=1 */ + if (Set_ATE_TX_COUNT_Proc(pAd, "1") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXLEN=258 */ + if (Set_ATE_TX_LENGTH_Proc(pAd, "258") == FALSE) + return FALSE; + + /* iwpriv ra0 set InvTxBfTag=0 */ + if (Set_InvTxBfTag_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATE=TXFRAME */ + if (Set_ATE_Proc(pAd, "TXFRAME") == FALSE) + return FALSE; + + /* iwpriv ra0 set ITxBfCal=1 */ + return Set_ITxBfCal_Proc(pAd, "1"); + +} + + +/* +========================================================================== + Description: + Set to start the initialization procedures of iTxBf calibration in Golden side at specified channel + arg => valid values are "1, 14, 36, 64, 128, 132, 165" + + Return: + TRUE if all parameters are OK, FALSE otherwise + + Note: + This cmd shall only used in GOLDEN side for calibration feedback +========================================================================== +*/ +INT Set_ATE_TXBF_GOLDEN_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR ch; + UCHAR cmdStr[32]; + USHORT eepromVal; + + ch = simple_strtol(arg, 0, 10); + if (rtmp_ate_txbf_cal_valid_ch(pAd, ch) == FALSE) + return FALSE; + + /* iwpriv ra0 set ATE=ATESTART */ +#ifdef CONFIG_RT2880_ATE_CMD_NEW + Set_ATE_Proc(pAd, "ATESTART"); +#else + Set_ATE_Proc(pAd, "APSTOP"); +#endif // CONFIG_RT2880_ATE_CMD_NEW // + + /* set the ate channel and read txpower from EEPROM and set to bbp */ + /* iwpriv ra0 set ATECHANNEL=Channel */ + /* iwpriv ra0 set ATETXPOWER=0 */ + snprintf(cmdStr, sizeof(cmdStr), "%d\n", ch); + Set_ATE_INIT_CHAN_Proc(pAd, cmdStr); + + + /* Set self mac address as 11:11:11:11:11:11 */ + /* iwpriv ra0 set ATESA=11:11:11:11:11:11 */ + RTMP_IO_WRITE32(pAd, 0x1008, 0x11111111); + RTMP_IO_WRITE32(pAd, 0x100c, 0x00001111); + + /* iwpriv ra0 set ATETXMODE=2 */ + Set_ATE_TX_MODE_Proc(pAd, "2"); + + /* iwpriv ra0 set ATETXBW=0 */ + Set_ATE_TX_BW_Proc(pAd, "0"); + + /* iwpriv ra0 set ATETXGI=0 */ + Set_ATE_TX_GI_Proc(pAd, "0"); + + /* iwpriv ra0 set ATETXANT=1 */ + Set_ATE_TX_Antenna_Proc(pAd, "1"); + + /* iwpriv ra0 set ATERXANT=1 */ + Set_ATE_RX_Antenna_Proc(pAd, "1"); + + /* iwpriv ra0 set ATETXFREQOFFSET=ValueOfEEPROM */ + RT28xx_EEPROM_READ16(pAd, 0x44, eepromVal); + snprintf(cmdStr, sizeof(cmdStr), "%d\n", (eepromVal & 0xff)); + Set_ATE_TX_FREQ_OFFSET_Proc(pAd, cmdStr); + + /* iwpriv ra0 bbp 65=29 */ + /* iwpriv ra0 bbp 163=9d */ + /* iwpriv ra0 bbp 173=00 */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R65, 0x29); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R163, 0x9d); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R173, 0x00); + + /* iwpriv ra0 set ATE=RXFRAME */ + Set_ATE_Proc(pAd, "RXFRAME"); + + /* reset the BBP_R173 as 0 to eliminate the compensation */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R173, 0x00); + + return TRUE; + +} + + +/* +========================================================================== + Description: + Set to do iTxBF calibration verification procedures at sepcified channel, following show us the supported channels. + args=> valid values are "1, 14, 36, 64, 128, 132, 165" + + Return: + TRUE if all parameters are OK, FALSE otherwise + + Note: + This cmd shall only used in GOLDEN side for calibration verification +========================================================================== +*/ +INT Set_ATE_TXBF_VERIFY_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR ch; + UCHAR cmdStr[32]; + + ch = simple_strtol(arg, 0, 10); + if (rtmp_ate_txbf_cal_valid_ch(pAd, ch) == FALSE) + return FALSE; + + /* iwpriv ra0 set ATECHANNEL=Channel */ + snprintf(cmdStr, sizeof(cmdStr), "%d\n", ch); + if (Set_ATE_CHANNEL_Proc(pAd, cmdStr) == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXSOUNDING=3 */ + if (Set_ATE_TXSOUNDING_Proc(pAd, "3") == FALSE) + return FALSE; + + /* iwpriv ra0 set ETxBfNoncompress=0 */ + if (Set_ETxBfNoncompress_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXMCS=0 */ + if (Set_ATE_TX_MCS_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXCNT=1 */ + if (Set_ATE_TX_COUNT_Proc(pAd, "1") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXLEN=258 */ + if (Set_ATE_TX_LENGTH_Proc(pAd, "258") == FALSE) + return FALSE; + + /* iwpriv ra0 set InvTxBfTag=0 */ + if (Set_InvTxBfTag_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATE=TXFRAME */ + if (Set_ATE_Proc(pAd, "TXFRAME") == FALSE) + return FALSE; + + /* iwpriv ra0 set ITxBfCal=0 */ + return Set_ITxBfCal_Proc(pAd, "0"); +} + + +INT Set_ATE_ForceBBP_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR bbpReg; + + bbpReg = simple_strtol(arg, 0, 10); + + /* + 0: no any restriction for BBP writing + 1~255: force to not allow to change this specific BBP register. + + Note: + BBP_R0 is not write-able, so use 0 as the rest operation shall be safe enough + */ + pATEInfo->forceBBPReg = bbpReg; + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_ForceBBP_Proc:(forceBBPReg value=%d)\n", pATEInfo->forceBBPReg)); + + return TRUE; +} + + +/* +========================================================================== + Description: + Set to do iTxBF calibration verification without R173 compensation procedures at sepcified channel, following show us the supported channels. + args=> valid values are "1, 14, 36, 64, 128, 132, 165" + + Return: + TRUE if all parameters are OK, FALSE otherwise + + Note: + This cmd shall only used in GOLDEN side for calibration verification +========================================================================== +*/ +INT Set_ATE_TXBF_VERIFY_NoComp_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR ch; + UCHAR cmdStr[32]; + UCHAR bbpR173 = 0; + int retval; + + ch = simple_strtol(arg, 0, 10); + if (rtmp_ate_txbf_cal_valid_ch(pAd, ch) == FALSE) + return FALSE; + + /* iwpriv ra0 set ATECHANNEL=Channel */ + snprintf(cmdStr, sizeof(cmdStr), "%d\n", ch); + if (Set_ATE_CHANNEL_Proc(pAd, cmdStr) == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXSOUNDING=3 */ + if (Set_ATE_TXSOUNDING_Proc(pAd, "3") == FALSE) + return FALSE; + + /* iwpriv ra0 set ETxBfNoncompress=0 */ + if (Set_ETxBfNoncompress_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXMCS=0 */ + if (Set_ATE_TX_MCS_Proc(pAd, "0") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXCNT=1 */ + if (Set_ATE_TX_COUNT_Proc(pAd, "1") == FALSE) + return FALSE; + + /* iwpriv ra0 set ATETXLEN=258 */ + if (Set_ATE_TX_LENGTH_Proc(pAd, "258") == FALSE) + return FALSE; + + /* iwpriv ra0 set InvTxBfTag=0 */ + if (Set_InvTxBfTag_Proc(pAd, "0") == FALSE) + return FALSE; + + /* save current BBP_R173 value and reset it as 0 */ + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R173, &bbpR173); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R173, 0); + + /* force BBP_R173 value when do following procedures. */ + Set_ATE_ForceBBP_Proc(pAd, "173"); + + /* iwpriv ra0 set ATE=TXFRAME */ + if (Set_ATE_Proc(pAd, "TXFRAME") == FALSE) + { + Set_ATE_ForceBBP_Proc(pAd, "0"); + return FALSE; + } + + /* enable the update of BBP_R173 */ + Set_ATE_ForceBBP_Proc(pAd, "0"); + + /* iwpriv ra0 set ITxBfCal=0 */ + retval = Set_ITxBfCal_Proc(pAd, "0"); + + /* recovery the BBP_173 to original value */ + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R173, bbpR173); + + /* done and return */ + return retval; + +} +#endif /* TXBF_SUPPORT */ + + +/* +========================================================================== + Description: + Set ATE Tx frame IPG + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_IPG_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 data, value; + + pATEInfo->IPG = simple_strtol(arg, 0, 10); + value = pATEInfo->IPG; + + RTMP_IO_READ32(pAd, XIFS_TIME_CFG, &data); + + if (value <= 0) + { + DBGPRINT(RT_DEBUG_OFF, ("Set_ATE_IPG_Proc::IPG is disabled(IPG == 0).\n")); + return TRUE; + } + + ASSERT(value > 0); + + if ((value > 0) && (value < 256)) + { + RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &data); + data &= 0x0; + RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, data); + + RTMP_IO_READ32(pAd, EDCA_AC1_CFG, &data); + data &= 0x0; + RTMP_IO_WRITE32(pAd, EDCA_AC1_CFG, data); + + RTMP_IO_READ32(pAd, EDCA_AC2_CFG, &data); + data &= 0x0; + RTMP_IO_WRITE32(pAd, EDCA_AC2_CFG, data); + + RTMP_IO_READ32(pAd, EDCA_AC3_CFG, &data); + data &= 0x0; + RTMP_IO_WRITE32(pAd, EDCA_AC3_CFG, data); + } + else + { + UINT32 aifsn, slottime; + + RTMP_IO_READ32(pAd, BKOFF_SLOT_CFG, &slottime); + slottime &= 0x000000FF; + + aifsn = value / slottime; + value = value % slottime; + + RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &data); + data &= 0x0; + data |= (aifsn << 8); + RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, data); + + RTMP_IO_READ32(pAd, EDCA_AC1_CFG, &data); + data &= 0x0; + data |= (aifsn << 8); + RTMP_IO_WRITE32(pAd, EDCA_AC1_CFG, data); + + RTMP_IO_READ32(pAd, EDCA_AC2_CFG, &data); + data &= 0x0; + data |= (aifsn << 8); + RTMP_IO_WRITE32(pAd, EDCA_AC2_CFG, data); + + RTMP_IO_READ32(pAd, EDCA_AC3_CFG, &data); + data &= 0x0; + data |= (aifsn << 8); + RTMP_IO_WRITE32(pAd, EDCA_AC3_CFG, data); + } + + data = (value & 0xFFFF0000) | value | (value << 8); + RTMP_IO_WRITE32(pAd, XIFS_TIME_CFG, data); + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_IPG_Proc (IPG = %u)\n", pATEInfo->IPG)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_IPG_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + +/* +========================================================================== + Description: + Set ATE payload pattern for TxFrame + + Return: + TRUE if all parameters are OK, FALSE otherwise +========================================================================== +*/ +INT Set_ATE_Payload_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + PSTRING value; + + value = arg; + + /* only one octet acceptable */ + if (strlen(value) != 2) + return FALSE; + + AtoH(value, &(pATEInfo->Payload), 1); + + DBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_Payload_Proc (repeated pattern = 0x%2x)\n", pATEInfo->Payload)); + DBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_Payload_Proc Success\n")); + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; +} + + + + +INT Set_ATE_Show_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + PSTRING Mode_String = NULL; + PSTRING TxMode_String = NULL; + + switch (pATEInfo->Mode) + { +#ifdef CONFIG_RT2880_ATE_CMD_NEW + case (fATE_IDLE): + Mode_String = "ATESTART"; + break; + case (fATE_EXIT): + Mode_String = "ATESTOP"; + break; +#else + case (fATE_IDLE): + Mode_String = "APSTOP"; + break; + case (fATE_EXIT): + Mode_String = "APSTART"; + break; +#endif /* CONFIG_RT2880_ATE_CMD_NEW */ + case ((fATE_TX_ENABLE)|(fATE_TXCONT_ENABLE)): + Mode_String = "TXCONT"; + break; + case ((fATE_TX_ENABLE)|(fATE_TXCARR_ENABLE)): + Mode_String = "TXCARR"; + break; + case ((fATE_TX_ENABLE)|(fATE_TXCARRSUPP_ENABLE)): + Mode_String = "TXCARS"; + break; + case (fATE_TX_ENABLE): + Mode_String = "TXFRAME"; + break; + case (fATE_RX_ENABLE): + Mode_String = "RXFRAME"; + break; + default: + { + Mode_String = "Unknown ATE mode"; + DBGPRINT(RT_DEBUG_OFF, ("ERROR! Unknown ATE mode!\n")); + break; + } + } + DBGPRINT(RT_DEBUG_OFF, ("ATE Mode=%s\n", Mode_String)); +#ifdef RT3350 + if (IS_RT3350(pAd)) + DBGPRINT(RT_DEBUG_OFF, ("PABias=%u\n", pATEInfo->PABias)); +#endif /* RT3350 */ + DBGPRINT(RT_DEBUG_OFF, ("TxPower0=%d\n", pATEInfo->TxPower0)); + DBGPRINT(RT_DEBUG_OFF, ("TxPower1=%d\n", pATEInfo->TxPower1)); +#ifdef DOT11N_SS3_SUPPORT + DBGPRINT(RT_DEBUG_OFF, ("TxPower2=%d\n", pATEInfo->TxPower2)); +#endif /* DOT11N_SS3_SUPPORT */ + DBGPRINT(RT_DEBUG_OFF, ("TxAntennaSel=%d\n", pATEInfo->TxAntennaSel)); + DBGPRINT(RT_DEBUG_OFF, ("RxAntennaSel=%d\n", pATEInfo->RxAntennaSel)); + DBGPRINT(RT_DEBUG_OFF, ("BBPCurrentBW=%u\n", pATEInfo->TxWI.TxWIBW)); + DBGPRINT(RT_DEBUG_OFF, ("GI=%u\n", pATEInfo->TxWI.TxWIShortGI)); + DBGPRINT(RT_DEBUG_OFF, ("MCS=%u\n", pATEInfo->TxWI.TxWIMCS)); + + switch (pATEInfo->TxWI.TxWIPHYMODE) + { + case 0: + TxMode_String = "CCK"; + break; + case 1: + TxMode_String = "OFDM"; + break; + case 2: + TxMode_String = "HT-Mix"; + break; + case 3: + TxMode_String = "GreenField"; + break; + default: + { + TxMode_String = "Unknown TxMode"; + DBGPRINT(RT_DEBUG_OFF, ("ERROR! Unknown TxMode!\n")); + break; + } + } + + DBGPRINT(RT_DEBUG_OFF, ("TxMode=%s\n", TxMode_String)); + DBGPRINT(RT_DEBUG_OFF, ("Addr1=%02x:%02x:%02x:%02x:%02x:%02x\n", + pATEInfo->Addr1[0], pATEInfo->Addr1[1], pATEInfo->Addr1[2], pATEInfo->Addr1[3], pATEInfo->Addr1[4], pATEInfo->Addr1[5])); + DBGPRINT(RT_DEBUG_OFF, ("Addr2=%02x:%02x:%02x:%02x:%02x:%02x\n", + pATEInfo->Addr2[0], pATEInfo->Addr2[1], pATEInfo->Addr2[2], pATEInfo->Addr2[3], pATEInfo->Addr2[4], pATEInfo->Addr2[5])); + DBGPRINT(RT_DEBUG_OFF, ("Addr3=%02x:%02x:%02x:%02x:%02x:%02x\n", + pATEInfo->Addr3[0], pATEInfo->Addr3[1], pATEInfo->Addr3[2], pATEInfo->Addr3[3], pATEInfo->Addr3[4], pATEInfo->Addr3[5])); + DBGPRINT(RT_DEBUG_OFF, ("Channel=%u\n", pATEInfo->Channel)); + DBGPRINT(RT_DEBUG_OFF, ("TxLength=%u\n", pATEInfo->TxLength)); + DBGPRINT(RT_DEBUG_OFF, ("TxCount=%u\n", pATEInfo->TxCount)); + DBGPRINT(RT_DEBUG_OFF, ("RFFreqOffset=%u\n", pATEInfo->RFFreqOffset)); + DBGPRINT(RT_DEBUG_OFF, ("bAutoTxAlc=%d\n", pATEInfo->bAutoTxAlc)); + DBGPRINT(RT_DEBUG_OFF, ("IPG=%u\n", pATEInfo->IPG)); + DBGPRINT(RT_DEBUG_OFF, ("Payload=0x%02x\n", pATEInfo->Payload)); +#ifdef TXBF_SUPPORT + DBGPRINT(RT_DEBUG_OFF, ("bTxBF=%d\n", pATEInfo->bTxBF)); + DBGPRINT(RT_DEBUG_OFF, ("txSoundingMode=%d\n", pATEInfo->txSoundingMode)); +#endif /* TXBF_SUPPORT */ + DBGPRINT(RT_DEBUG_OFF, ("Set_ATE_Show_Proc Success\n")); +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + return TRUE; +} + + +INT Set_ATE_Help_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ +#ifdef CONFIG_RT2880_ATE_CMD_NEW + DBGPRINT(RT_DEBUG_OFF, ("ATE=ATESTART, ATESTOP, TXCONT, TXCARR, TXCARS, TXFRAME, RXFRAME\n")); +#else + DBGPRINT(RT_DEBUG_OFF, ("ATE=APSTOP, APSTART, TXCONT, TXCARR, TXCARS, TXFRAME, RXFRAME\n")); +#endif /* CONFIG_RT2880_ATE_CMD_NEW */ + DBGPRINT(RT_DEBUG_OFF, ("ATEDA\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATESA\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEBSSID\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATECHANNEL, range:0~14(unless A band !)\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXPOW0, set power level of antenna 1.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXPOW1, set power level of antenna 2.\n")); +#ifdef DOT11N_SS3_SUPPORT + DBGPRINT(RT_DEBUG_OFF, ("ATETXPOW2, set power level of antenna 3.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXANT, set TX antenna. 0:all, 1:antenna one, 2:antenna two, 3:antenna three.\n")); +#else + DBGPRINT(RT_DEBUG_OFF, ("ATETXANT, set TX antenna. 0:all, 1:antenna one, 2:antenna two.\n")); +#endif /* DOT11N_SS3_SUPPORT */ + DBGPRINT(RT_DEBUG_OFF, ("ATERXANT, set RX antenna.0:all, 1:antenna one, 2:antenna two, 3:antenna three.\n")); +#ifdef RT3350 + if (IS_RT3350(pAd)) + DBGPRINT(RT_DEBUG_OFF, ("ATEPABIAS, set power amplifier bias for EVM, range 0~15\n")); +#endif /* RT3350 */ + DBGPRINT(RT_DEBUG_OFF, ("ATETXFREQOFFSET, set frequency offset, range 0~63\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXBW, set BandWidth, 0:20MHz, 1:40MHz.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXLEN, set Frame length, range 24~%d\n", (MAX_FRAME_SIZE - 34/* == 2312 */))); + DBGPRINT(RT_DEBUG_OFF, ("ATETXCNT, set how many frame going to transmit.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXMCS, set MCS, reference to rate table.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXMODE, set Mode 0:CCK, 1:OFDM, 2:HT-Mix, 3:GreenField, reference to rate table.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXGI, set GI interval, 0:Long, 1:Short\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATERXFER, 0:disable Rx Frame error rate. 1:enable Rx Frame error rate.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATERRF, show all RF registers.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEWRF1, set RF1 register.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEWRF2, set RF2 register.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEWRF3, set RF3 register.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEWRF4, set RF4 register.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATELDE2P, load EEPROM from .bin file.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATERE2P, display all EEPROM content.\n")); +#ifdef LED_CONTROL_SUPPORT +#endif /* LED_CONTROL_SUPPORT */ + DBGPRINT(RT_DEBUG_OFF, ("ATEAUTOALC, enable ATE auto Tx alc (Tx auto level control).\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEIPG, set ATE Tx frame IPG.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEPAYLOAD, set ATE payload pattern for TxFrame.\n")); +#ifdef TXBF_SUPPORT + DBGPRINT(RT_DEBUG_OFF, ("ATETXBF, enable ATE Tx beam forming.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETXSOUNDING, Sounding mode 0:none, 1:Data sounding, 2:2 stream NDP, 3:3 stream NDP.\n")); +#endif /* TXBF_SUPPORT */ +#ifdef RTMP_INTERNAL_TX_ALC + DBGPRINT(RT_DEBUG_OFF, ("ATETSSICBA, start internal TSSI calibration.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATETSSICBAEX, start extended internal TSSI calibration.\n")); +#endif /* RTMP_INTERNAL_TX_ALC */ +#ifdef RTMP_TEMPERATURE_COMPENSATION + DBGPRINT(RT_DEBUG_OFF, ("ATEREADEXTSSI, start advanced temperature TSSI calibration.\n")); +#endif /* RTMP_TEMPERATURE_COMPENSATION */ + DBGPRINT(RT_DEBUG_OFF, ("ATESHOW, display all parameters of ATE.\n")); + DBGPRINT(RT_DEBUG_OFF, ("ATEHELP, online help.\n")); + + return TRUE; +} + + +#ifdef RTMP_INTERNAL_TX_ALC + + +INT Set_ATE_TSSI_CALIBRATION_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->TssiCalibration != NULL) +{ + pATEInfo->pChipStruct->TssiCalibration(pAd, arg); + } + else + { + RTMP_CHIP_ATE_TSSI_CALIBRATION(pAd, arg); + } + + return TRUE; +} + + +INT Set_ATE_TSSI_CALIBRATION_EX_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + if (pATEInfo->pChipStruct->ExtendedTssiCalibration != NULL) + { + pATEInfo->pChipStruct->ExtendedTssiCalibration(pAd, arg); + } + else + { + RTMP_CHIP_ATE_TSSI_CALIBRATION_EXTEND(pAd, arg); + } + + return TRUE; +} + + +#if defined(RT3350) || defined(RT3352) +INT RT335x2_Set_ATE_TSSI_CALIBRATION_ENABLE_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) + { + BOOLEAN bTSSICalbrEnableG = FALSE; + + if (pAd->TxPowerCtrl.bInternalTxALC == FALSE) + { + DBGPRINT_ERR(("Please set e2p 0x36 as 0x2024!!!\n")); + return FALSE; + } + + if ((!IS_RT3350(pAd)) && (!IS_RT3352(pAd))) + { + DBGPRINT_ERR(("Not support TSSI calibration since not 3350/3352 chip!!!\n")); + return FALSE; + } + + if (strcmp(arg, "0") == 0) + { + bTSSICalbrEnableG = FALSE; + DBGPRINT(RT_DEBUG_TRACE, ("TSSI calibration disabled!\n")); + } + else if (strcmp(arg, "1") == 0) + { + bTSSICalbrEnableG = TRUE; + DBGPRINT(RT_DEBUG_TRACE, ("TSSI calibration enabled!\n")); + } + else + { + return FALSE; + } + + pAd->ate.bTSSICalbrEnableG = bTSSICalbrEnableG; + +#ifdef CONFIG_AP_SUPPORT +#endif /* CONFIG_AP_SUPPORT */ + + return TRUE; + } + + +CHAR InsertTssi(UCHAR InChannel, UCHAR Channel0, UCHAR Channel1,CHAR Tssi0, CHAR Tssi1) +{ + CHAR InTssi; + CHAR ChannelDelta, InChannelDelta; + CHAR TssiDelta; + + ChannelDelta = Channel1 - Channel0; + InChannelDelta = InChannel - Channel0; + TssiDelta = Tssi1 - Tssi0; + + InTssi = Tssi0 + ((InChannelDelta * TssiDelta) / ChannelDelta); + + return InTssi; +} + + +INT RT335xATETssiCalibrationExtend( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + CHAR TssiRefPerChannel[CFG80211_NUM_OF_CHAN_2GHZ], TssiDeltaPerChannel[CFG80211_NUM_OF_CHAN_2GHZ]; + UCHAR CurrentChannel; + UCHAR BbpData = 0; + USHORT EEPData; + + if (pAd->ate.bTSSICalbrEnableG == FALSE) + { + DBGPRINT_ERR(("No TSSI readings obtained !!!\n")); + DBGPRINT_ERR(("TSSI calibration failed !!!\n")); + + return FALSE; + } + else + { + pAd->ate.bTSSICalbrEnableG = FALSE; + } + + NdisCopyMemory(TssiRefPerChannel, pAd->ate.TssiRefPerChannel, CFG80211_NUM_OF_CHAN_2GHZ); + NdisCopyMemory(TssiDeltaPerChannel, pAd->ate.TssiDeltaPerChannel, CFG80211_NUM_OF_CHAN_2GHZ); + + /* step 1: write TSSI_ref to EEPROM 0x6E */ + CurrentChannel = 7; + BbpData = TssiRefPerChannel[CurrentChannel-1]; + DBGPRINT(RT_DEBUG_TRACE, ("TSSI_ref = 0x%02x\n", TssiRefPerChannel[CurrentChannel-1])); + RT28xx_EEPROM_READ16(pAd, EEPROM_TSSI_OVER_OFDM_54, EEPData); + EEPData &= 0xff00; + EEPData |= BbpData; + DBGPRINT(RT_DEBUG_TRACE, ("Write E2P 0x6e: 0x%04x\n", EEPData)); +#ifdef RTMP_EFUSE_SUPPORT + if(pAd->bUseEfuse) + { + if(pAd->bFroceEEPROMBuffer) + NdisMoveMemory(&(pAd->EEPROMImage[EEPROM_TSSI_OVER_OFDM_54]), (PUCHAR) (&EEPData) ,2); + else + eFuseWrite(pAd, EEPROM_TSSI_OVER_OFDM_54, (PUCHAR) (&EEPData), 2); + } + else +#endif /* RTMP_EFUSE_SUPPORT */ + { + RT28xx_EEPROM_WRITE16(pAd, EEPROM_TSSI_OVER_OFDM_54, EEPData); + RTMPusecDelay(10); + } + + /* step 2: insert the TSSI table */ + /* insert channel 2 to 6 TSSI values */ + for (CurrentChannel = 2; CurrentChannel < 7; CurrentChannel++) + TssiRefPerChannel[CurrentChannel-1] = InsertTssi(CurrentChannel, 1, 7, TssiRefPerChannel[0], TssiRefPerChannel[6]); + + /* insert channel 8 to 12 TSSI values */ + for (CurrentChannel = 8; CurrentChannel < 13; CurrentChannel++) + TssiRefPerChannel[CurrentChannel-1] = InsertTssi(CurrentChannel, 7, 13, TssiRefPerChannel[6], TssiRefPerChannel[12]); + + /* channel 14 TSSI equals channel 13 TSSI */ + TssiRefPerChannel[13] = TssiRefPerChannel[12]; + + for (CurrentChannel = 1; CurrentChannel <= 14; CurrentChannel++) + { + TssiDeltaPerChannel[CurrentChannel-1] = TssiRefPerChannel[CurrentChannel-1] - TssiRefPerChannel[6]; + + /* boundary check */ + if(TssiDeltaPerChannel[CurrentChannel-1] > 7 ) + TssiDeltaPerChannel[CurrentChannel-1] = 7; + if(TssiDeltaPerChannel[CurrentChannel-1] < -8 ) + TssiDeltaPerChannel[CurrentChannel-1] = -8; + + /* eeprom only use 4 bit for TSSI delta */ + TssiDeltaPerChannel[CurrentChannel-1] &= 0x0f; + DBGPRINT(RT_DEBUG_TRACE, ("Channel %d, TSSI= 0x%x, TssiDelta=0x%x\n", + CurrentChannel, TssiRefPerChannel[CurrentChannel-1], TssiDeltaPerChannel[CurrentChannel-1])); + } + + /* step 3: store TSSI delta values to EEPROM */ + RT28xx_EEPROM_READ16(pAd, EEPROM_TX_POWER_OFFSET_OVER_CH_1-1, EEPData); + EEPData &= 0x00ff; + EEPData |= (TssiDeltaPerChannel[0] << 8) | (TssiDeltaPerChannel[1] << 12); + +#ifdef RTMP_EFUSE_SUPPORT + if (pAd->bUseEfuse) + { + if (pAd->bFroceEEPROMBuffer) + NdisMoveMemory(&(pAd->EEPROMImage[EEPROM_TX_POWER_OFFSET_OVER_CH_1-1]), (PUCHAR)(&EEPData), 2); + else + eFuseWrite(pAd, EEPROM_TX_POWER_OFFSET_OVER_CH_1-1, (PUCHAR) (&EEPData), 2); + } + else +#endif /* RTMP_EFUSE_SUPPORT */ + { + RT28xx_EEPROM_WRITE16(pAd, EEPROM_TX_POWER_OFFSET_OVER_CH_1-1, EEPData); + RTMPusecDelay(10); + } + + for (CurrentChannel = 3; CurrentChannel <= 14; CurrentChannel += 4) + { + EEPData = (TssiDeltaPerChannel[CurrentChannel+2] << 12) |(TssiDeltaPerChannel[CurrentChannel+1] << 8) + | (TssiDeltaPerChannel[CurrentChannel] << 4) | TssiDeltaPerChannel[CurrentChannel-1]; +#ifdef RTMP_EFUSE_SUPPORT + if (pAd->bUseEfuse) + { + if (pAd->bFroceEEPROMBuffer) + NdisMoveMemory(&(pAd->EEPROMImage[(EEPROM_TX_POWER_OFFSET_OVER_CH_3 +((CurrentChannel-3)/2))]), (PUCHAR)(&EEPData), 2); + else + eFuseWrite(pAd, (EEPROM_TX_POWER_OFFSET_OVER_CH_3 +((CurrentChannel-3)/2)), (PUCHAR) (&EEPData), 2); + } + else +#endif /* RTMP_EFUSE_SUPPORT */ + { + RT28xx_EEPROM_WRITE16(pAd, (EEPROM_TX_POWER_OFFSET_OVER_CH_3 +((CurrentChannel-3)/2)), EEPData); + RTMPusecDelay(10); + } + } + + /* step 4: disable legacy ALC and set TSSI enabled and TSSI extend mode to EEPROM */ + RT28xx_EEPROM_READ16(pAd, EEPROM_TSSI_ENABLE, EEPData); + /* disable legacy ALC */ + EEPData &= ~(1 << 1); + /* enable TSSI */ + EEPData |= (1 << 13); +#ifdef RTMP_EFUSE_SUPPORT + if (pAd->bUseEfuse) + { + if (pAd->bFroceEEPROMBuffer) + NdisMoveMemory(&(pAd->EEPROMImage[EEPROM_TSSI_ENABLE]), (PUCHAR)(&EEPData), 2); + else + eFuseWrite(pAd, EEPROM_TSSI_ENABLE, (PUCHAR)(&EEPData), 2); + } + else +#endif /* RTMP_EFUSE_SUPPORT */ + { + RT28xx_EEPROM_WRITE16(pAd, EEPROM_TSSI_ENABLE, EEPData); + RTMPusecDelay(10); + } + + RT28xx_EEPROM_READ16(pAd, EEPROM_TSSI_MODE_EXTEND, EEPData); + /* set extended TSSI mode */ + EEPData |= (1 << 15); +#ifdef RTMP_EFUSE_SUPPORT + if (pAd->bUseEfuse) + { + if (pAd->bFroceEEPROMBuffer) + NdisMoveMemory(&(pAd->EEPROMImage[EEPROM_TSSI_MODE_EXTEND]), (PUCHAR)(&EEPData), 2); + else + eFuseWrite(pAd, EEPROM_TSSI_MODE_EXTEND, (PUCHAR)(&EEPData), 2); + } + else +#endif /* RTMP_EFUSE_SUPPORT */ + { + RT28xx_EEPROM_WRITE16(pAd, EEPROM_TSSI_MODE_EXTEND, EEPData); + RTMPusecDelay(10); + } + + /* step 5: synchronize ATE private data structure with the values written to EEPROM */ + NdisCopyMemory(pAd->ate.TssiRefPerChannel, TssiRefPerChannel, CFG80211_NUM_OF_CHAN_2GHZ); + NdisCopyMemory(pAd->ate.TssiDeltaPerChannel, TssiDeltaPerChannel, CFG80211_NUM_OF_CHAN_2GHZ); + + return TRUE; +} + +#endif /* defined(RT3350) || defined(RT3352) */ +#endif /* RTMP_INTERNAL_TX_ALC */ + + +#ifdef RTMP_TEMPERATURE_COMPENSATION + + +INT Set_ATE_READ_EXTERNAL_TSSI_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + + RTMP_CHIP_ATE_READ_EXTERNAL_TSSI(pAd, arg); + return TRUE; +} +#endif /* RTMP_TEMPERATURE_COMPENSATION */ + + + + +#ifdef MT7601 +INT Set_ATE_Read_Temperature_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + CHAR Temperature; + + DBGPRINT(RT_DEBUG_TRACE,("Set_MT7601ATE_Read_Temperature_Proc\n")); + + MT7601_Read_Temperature(pAd, &Temperature); + + DBGPRINT(RT_DEBUG_TRACE,("Temperature = %d (0x%X)\n", Temperature, Temperature)); + + return TRUE; +} + + +INT Set_ATE_Read_TSSI_DC_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR BbpReg; + + DBGPRINT(RT_DEBUG_TRACE,("Set_ATE_Read_TSSI_DC_Proc\n")); + + RTMP_IO_WRITE32(pAd, 0x50C, 0x30); + RTMP_IO_WRITE32(pAd, 0x504, 0xC0030); + /* Set VGA gain */ + rlt_rf_write(pAd, RF_BANK5, RF_R03, 0x8); + /* Mixer disable */ + rlt_rf_write(pAd, RF_BANK4, RF_R39, 0x0); + + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4 , 0x0); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R58 , 0x0); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21 , 0x1); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21 , 0x0); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47 , 0x50); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22 , 0x40); + RtmpOsMsDelay(10); + + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R47, &BbpReg); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, 0x40); + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpReg); + DBGPRINT(RT_DEBUG_TRACE,("TSSI DC = %d (0x%X)\n", BbpReg, BbpReg)); + RtmpOsMsDelay(1); + + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22 , 0x0); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21 , 0x1); + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21 , 0x0); + RTMP_IO_WRITE32(pAd, 0x504, 0x0); + RTMP_IO_WRITE32(pAd, 0x50C, 0x0); + rlt_rf_write(pAd, RF_BANK4, RF_R39, 0xB3); + + return TRUE; +} +#endif /* MT7601 */ + + +struct _ATE_CHIP_STRUCT RALINKDefault = +{ + /* functions */ + .ChannelSwitch = DefaultATEAsicSwitchChannel, + .TxPwrHandler = DefaultATETxPwrHandler, + .TssiCalibration = NULL, + .ExtendedTssiCalibration = NULL, + .RxVGAInit = NULL, + .AsicSetTxRxPath = DefaultATEAsicSetTxRxPath, + .AdjustTxPower = DefaultATEAsicAdjustTxPower, + .AsicExtraPowerOverMAC = NULL, + + /* command handlers */ + .Set_BW_Proc = Default_Set_ATE_TX_BW_Proc, + .Set_FREQ_OFFSET_Proc = Default_Set_ATE_TX_FREQ_OFFSET_Proc, + + /* variables */ + .maxTxPwrCnt = 5, + .bBBPStoreTXCARR = TRUE, + .bBBPStoreTXCARRSUPP = TRUE, + .bBBPStoreTXCONT = FALSE, + .bBBPLoadATESTOP = TRUE, +}; + +#ifdef RT28xx +#ifdef RTMP_MAC_USB +extern ATE_CHIP_STRUCT RALINK2870; +#endif /* RTMP_MAC_USB */ +#endif /* RT28xx */ + + + + + + + + + + + + +#ifdef MT7601 +extern ATE_CHIP_STRUCT MT7601ATE; +#endif + +/* +========================================================================== + Description: + Assign chip structure when initialization. + This routine is specific for ATE. + +========================================================================== +*/ +NDIS_STATUS ChipStructAssign( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + pATEInfo->pChipStruct = &RALINKDefault; + +#ifdef RT28xx +#ifdef A_BAND_SUPPORT + if (IS_PCI_ONLY_INF(pAd) || IS_USB_INF(pAd) || IS_RBUS_INF(pAd)) + + { + + + + if (pATEInfo->pChipStruct == &RALINKDefault) + { + /* Not RT2860/RT2870/RT2880 ! */ + DBGPRINT_ERR(("Error - Unknown chipset !!!\n")); + DBGPRINT_ERR(("The interface type is %d\n", pAd->infType)); + + return NDIS_STATUS_FAILURE; + } + } +#endif /* A_BAND_SUPPORT */ +#endif /* RT28xx */ + + + + + + + + + + + +#ifdef MT7601 + if ( IS_MT7601(pAd) ) + { + pATEInfo->pChipStruct = &MT7601ATE; + } +#endif /* MT7601 */ + + return NDIS_STATUS_SUCCESS; +} + + +/* +========================================================================== + Description: + Initialize ATE_INFO structure. + This routine is specific for ATE. + +========================================================================== +*/ +NDIS_STATUS ATEInit( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + NdisZeroMemory(pATEInfo, sizeof(ATE_INFO)); + + if (ChipStructAssign(pAd) != NDIS_STATUS_SUCCESS) + { + DBGPRINT_ERR(("%s failed !\n", __FUNCTION__)); + return NDIS_STATUS_FAILURE; + } + + pATEInfo->Mode = ATE_STOP; +#ifdef RT3350 + pATEInfo->PABias = 0; +#endif /* RT3350 */ + pATEInfo->TxCount = 1000;/* to sync with QA and to exceed TX_RING_SIZE ... */ + pATEInfo->TxDoneCount = 0; + pATEInfo->RFFreqOffset = 0; + pATEInfo->Payload = 0xA5;/* to be backward compatible */ + pATEInfo->IPG = 200;/* 200 : sync with QA */ + pATEInfo->TxLength = 1024; + pATEInfo->TxWI.TxWIShortGI = 0;/* LONG GI : 800 ns*/ + pATEInfo->TxWI.TxWIPHYMODE = MODE_CCK; + pATEInfo->TxWI.TxWIMCS = 3; + pATEInfo->TxWI.TxWIBW = BW_20; + /* please do not change this default channel value */ + pATEInfo->Channel = 1; + + + pATEInfo->QID = QID_AC_BE; + +#ifdef DOT11N_SS3_SUPPORT + /* For 3T/3R ++ */ + /* use broadcast address as default value */ + pATEInfo->Addr1[0] = 0xFF; + pATEInfo->Addr1[1] = 0xFF; + pATEInfo->Addr1[2] = 0xFF; + pATEInfo->Addr1[3] = 0xFF; + pATEInfo->Addr1[4] = 0xFF; + pATEInfo->Addr1[5] = 0xFF; + + pATEInfo->Addr2[0] = 0x00; + pATEInfo->Addr2[1] = 0x11; + pATEInfo->Addr2[2] = 0x22; + pATEInfo->Addr2[3] = 0xAA; + pATEInfo->Addr2[4] = 0xBB; + pATEInfo->Addr2[5] = 0xCC; + + NdisMoveMemory(pATEInfo->Addr3, pATEInfo->Addr2, ETH_LENGTH_OF_ADDRESS); + + { + UINT32 data; + + data = 0xFFFFFFFF; + RTMP_IO_WRITE32(pAd, 0x1044, data); + RTMP_IO_READ32(pAd, 0x1048, &data); + + data = data | 0x0000FFFF; + RTMP_IO_WRITE32(pAd, 0x1048, data); + } + /* For stream mode in 3T/3R -- */ +#else + pATEInfo->Addr1[0] = 0x00; + pATEInfo->Addr1[1] = 0x11; + pATEInfo->Addr1[2] = 0x22; + pATEInfo->Addr1[3] = 0xAA; + pATEInfo->Addr1[4] = 0xBB; + pATEInfo->Addr1[5] = 0xCC; + + NdisMoveMemory(pATEInfo->Addr2, pATEInfo->Addr1, ETH_LENGTH_OF_ADDRESS); + NdisMoveMemory(pATEInfo->Addr3, pATEInfo->Addr1, ETH_LENGTH_OF_ADDRESS); +#endif /* DOT11N_SS3_SUPPORT */ + + pATEInfo->bRxFER = 0; + pATEInfo->bQAEnabled = FALSE; + pATEInfo->bQATxStart = FALSE; + pATEInfo->bQARxStart = FALSE; + pATEInfo->bAutoTxAlc = FALSE; +#ifdef RTMP_INTERNAL_TX_ALC +#if defined(RT3350) || defined(RT3352) + pATEInfo->bTSSICalbrEnableG = FALSE; + NdisZeroMemory((PUCHAR)&(pATEInfo->TssiRefPerChannel), CFG80211_NUM_OF_CHAN_2GHZ); + NdisZeroMemory((PUCHAR)&(pATEInfo->TssiDeltaPerChannel), CFG80211_NUM_OF_CHAN_2GHZ); +#endif /* defined(RT3350) || defined(RT3352) */ +#endif /* RTMP_INTERNAL_TX_ALC */ + /* Default TXCONT/TXCARR/TXCARS mechanism is TX_METHOD_1 */ + pATEInfo->TxMethod = TX_METHOD_1; + if ((IS_RT2070(pAd) || IS_RT2860(pAd) || IS_RT2872(pAd) || IS_RT2883(pAd))) + { + /* Early chipsets must be applied original TXCONT/TXCARR/TXCARS mechanism. */ + pATEInfo->TxMethod = TX_METHOD_0; + } + + /* Power range is 0~31 in A band. */ + pATEInfo->MinTxPowerBandA = 0; + pATEInfo->MaxTxPowerBandA = 31; + if ((IS_RT2860(pAd)) || (IS_RT2872(pAd)) || (IS_RT2883(pAd))) + { + /* Power range of early chipsets is -7~15 in A band. */ + pATEInfo->MinTxPowerBandA = -7; + pATEInfo->MaxTxPowerBandA = 15; + } + +#ifdef TXBF_SUPPORT + pATEInfo->bTxBF = FALSE; +#endif /* TXBF_SUPPORT */ + + +#ifdef RTMP_MAC_USB +#endif /* RTMP_MAC_USB */ + +#ifdef RALINK_QA + pATEInfo->TxStatus = 0; + RtmpOsTaskPidInit(&(pATEInfo->AtePid)); +/* pATEInfo->AtePid = THREAD_PID_INIT_VALUE; */ +#endif /* RALINK_QA */ + pATEInfo->OneSecPeriodicRound = 0; + + return NDIS_STATUS_SUCCESS; +} + + +#ifdef RALINK_QA +/* +========================================================================== + Description: + This routine is specific for ATE. + When we start tx from QA GUI, it will modify BBP registers without + notify ATE driver what the tx subtype is. + + Return: + VOID +========================================================================== +*/ +VOID ReadQATxTypeFromBBP( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR Bbp22Value = 0, Bbp24Value = 0; + + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &Bbp22Value); + + switch (Bbp22Value) + { + case BBP22_TXFRAME: + { + DBGPRINT(RT_DEBUG_TRACE,("START TXFRAME\n")); + pATEInfo->bQATxStart = TRUE; + Set_ATE_Proc(pAd, "TXFRAME"); + } + break; + + case BBP22_TXCONT_OR_CARRSUPP: + { + DBGPRINT(RT_DEBUG_TRACE,("BBP22_TXCONT_OR_CARRSUPP\n")); + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R24, &Bbp24Value); + + switch (Bbp24Value) + { + case BBP24_TXCONT: + { + DBGPRINT(RT_DEBUG_TRACE,("START TXCONT\n")); + pATEInfo->bQATxStart = TRUE; + + if (pATEInfo->TxMethod == TX_METHOD_0) + { + Set_ATE_Proc(pAd, "TXCONT"); + } + } + break; + + case BBP24_CARRSUPP: + { + DBGPRINT(RT_DEBUG_TRACE,("START TXCARRSUPP\n")); + pATEInfo->bQATxStart = TRUE; + + if (pATEInfo->TxMethod == TX_METHOD_0) + { + Set_ATE_Proc(pAd, "TXCARS"); + } + } + break; + + default: + { + DBGPRINT_ERR(("Unknown TX subtype !\n")); + } + break; + } + } + break; + + case BBP22_TXCARR: + { + DBGPRINT(RT_DEBUG_TRACE,("START TXCARR\n")); + pATEInfo->bQATxStart = TRUE; + + if (pATEInfo->TxMethod == TX_METHOD_0) + { + Set_ATE_Proc(pAd, "TXCARR"); + } + } + break; + + default: + { + DBGPRINT_ERR(("Unknown Start TX subtype !\n")); + } + break; + } + + return; +} +#endif /* RALINK_QA */ + + +NDIS_STATUS ATEBBPWriteWithRxChain( + IN RTMP_ADAPTER *pAd, + IN UCHAR bbpId, + IN CHAR bbpVal, + IN RX_CHAIN_IDX rx_ch_idx) +{ + UCHAR idx = 0, val = 0; + + if (((pAd->MACVersion & 0xffff0000) < 0x28830000) || + (pAd->Antenna.field.RxPath == 1)) + { + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, bbpId, bbpVal); + return NDIS_STATUS_SUCCESS; + } + + while (rx_ch_idx != 0) + { + if (idx >= pAd->Antenna.field.RxPath) + break; + + if (rx_ch_idx & 0x01) + { + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R27, &val); + val = (val & (~0x60)/* clear bit5 and bit6 */) | (idx << 5); +#ifdef RTMP_MAC_USB + if (IS_USB_INF(pAd)) + { + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, val); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, bbpId, bbpVal); + } +#endif /* RTMP_MAC_USB */ + + + DBGPRINT(RT_DEBUG_INFO, + ("%s(Idx):Write(R%d,val:0x%x) to Chain(0x%x, idx:%d)\n", + __FUNCTION__, bbpId, bbpVal, rx_ch_idx, idx)); + } + rx_ch_idx >>= 1; + idx++; + } + + return NDIS_STATUS_SUCCESS; +} + + +#define SMM_BASEADDR 0x4000 +#define PKT_BASEADDR 0x8000 + + +#ifdef RLT_MAC +INT Set_ADCDump_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + + DBGPRINT_ERR(("%s::Not supported!!!\n", __FUNCTION__)); + return TRUE; +} + +#else +INT Set_ADCDump_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR BBP_R21_Ori=0,BBP_R60_Ori=0,BBP_R142_ORI=0,BBP_R143_ORI=0; + UINT32 MACValue=0,PBF_SYS_CTRL_ORI=0,PBF_CAP_CTRL_ORI=0; + UINT32 CaptureModeOffset=0,CaptureStartAddr=0; + UINT32 SMM_Addr; + UINT32 PKT_Addr; + int i = 0; + PSTRING src = "ADCDump.txt"; + RTMP_OS_FD srcf; + RTMP_OS_FS_INFO osFSInfo; + UCHAR msg[128]; + UCHAR msg1[128]; + CAPTURE_MODE_SHARE_MEMORY SMMValued; + CAPTURE_MODE_PACKET_BUFFER PKTValue1d; + CAPTURE_MODE_PACKET_BUFFER PKTValue2d; + UCHAR retval=0; + UCHAR DataSourceADC6=simple_strtol(arg, 0, 10); + + pAd->ate.Mode = ATE_START; + + /* Disable Tx/Rx */ + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x00); + BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BBP_R21_Ori); + + /* Disable BBP power saving */ + + /* disable all Tx/Rx Queue */ + RTMP_IO_WRITE32(pAd, PBF_CFG, 0x00000000); + + /* capture mode */ + RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MACValue); + PBF_SYS_CTRL_ORI=MACValue; + MACValue |= 0x00004000; /* bit[14]=1 */ + RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, MACValue); + + /* capture setting */ + if (DataSourceADC6 == 1) + { + BBP_IO_READ8_BY_REG_ID(pAd, BBP_R60, &BBP_R60_Ori); + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R60, 0x80); + BBP_IO_READ8_BY_REG_ID(pAd, BBP_R142, &BBP_R142_ORI); + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R142, 0x10); + BBP_IO_READ8_BY_REG_ID(pAd, BBP_R143, &BBP_R143_ORI); + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R143, 0x05); + + RTMP_IO_READ32(pAd, PBF_CAP_CTRL, &MACValue); + PBF_CAP_CTRL_ORI=MACValue; + MACValue |= 0x00008000; /* set bit[15]=1 for ADC 6 */ + MACValue &= ~0x80000000; /* set bit[31]=0 */ + RTMP_IO_WRITE32(pAd, PBF_CAP_CTRL, MACValue); + } + else + { + RTMP_IO_READ32(pAd, PBF_CAP_CTRL, &MACValue); + PBF_CAP_CTRL_ORI=MACValue; + MACValue &= ~0x80008000; /* set bit[31]=0, bit[15]=0 for ADC 8 */ + RTMP_IO_WRITE32(pAd, PBF_CAP_CTRL, MACValue); + } + + /* trigger offset */ + RTMP_IO_READ32(pAd, PBF_CAP_CTRL, &MACValue); + MACValue &= ~(0x1FFF0000); + RTMP_IO_WRITE32(pAd, PBF_CAP_CTRL, MACValue); + + if ((CaptureModeOffset > 0) && (CaptureModeOffset <= 0x1FFF)) + { + RTMP_IO_READ32(pAd, PBF_CAP_CTRL, &MACValue); + MACValue |= CaptureModeOffset << 16; + RTMP_IO_WRITE32(pAd, PBF_CAP_CTRL, MACValue); + } + + /* start capture */ + RTMP_IO_READ32(pAd, PBF_CAP_CTRL, &MACValue); + MACValue = MACValue | 0x40000000; /* set bit[30]=1 */ + RTMP_IO_WRITE32(pAd, PBF_CAP_CTRL, MACValue); + + if (0) + { + /* start TX */ + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x4); + } + else + { + /* start RX */ + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x8); + } + + /* Wait until [0x440] bit30=0 */ + do + { + i++; + RTMPusecDelay(10); + RTMP_IO_READ32(pAd, PBF_CAP_CTRL, &MACValue); + MACValue = MACValue & 0x40000000; /* bit[30] */ + + if (MACValue == 0) + { + break; + } + + if (i == 1000) /* 3 sec */ + { + printk("Error, over 3s\n"); + break; + } + } while (MACValue != 0); + + if (DataSourceADC6 == 1) + { + /* restore BBP R60 */ + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R60, BBP_R60_Ori); + } + + /* Stop TX/RX */ + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0); + + /* Read [0x440] bit[12:0] */ + RTMP_IO_READ32(pAd, PBF_CAP_CTRL, &CaptureStartAddr); + CaptureStartAddr = CaptureStartAddr & 0x00001FFF; + + /* Dump data from MAC memory */ + RtmpOSFSInfoChange(&osFSInfo, TRUE); + + SMM_Addr=SMM_BASEADDR+CaptureStartAddr*2; + PKT_Addr=PKT_BASEADDR+CaptureStartAddr*4; + + /* SMM Address must be four byte alignment*/ + SMM_Addr=(SMM_Addr/4)*4; + + /* open file */ + if (src && *src) + { + srcf = RtmpOSFileOpen(src, O_WRONLY|O_CREAT, 0); + + if (IS_FILE_OPEN_ERR(srcf)) + { + DBGPRINT(RT_DEBUG_ERROR, ("--> Error opening %s\n", src)); + return FALSE; + } + else + { + memset(msg, 0x00, 128); + memset(msg1, 0x00, 128); + + for (i=0;i<0x1000;i++) + { + RTMP_IO_READ32(pAd,SMM_Addr, &SMMValued.Value); + SMM_Addr += 4; + + if(SMM_Addr >= 0x8000) + SMM_Addr = SMM_Addr - SMM_BASEADDR; + + RTMP_IO_READ32(pAd,PKT_Addr, &PKTValue1d.Value); + PKT_Addr += 4; + + if(PKT_Addr >= 0x10000) + PKT_Addr = PKT_Addr - PKT_BASEADDR; + + RTMP_IO_READ32(pAd,PKT_Addr, &PKTValue2d.Value); + PKT_Addr += 4; + + if(PKT_Addr >= 0x10000) + PKT_Addr = PKT_Addr - PKT_BASEADDR; + + sprintf(msg, "%d %d %d %d %d %d\n",SMMValued.field.LOW_BYTE1,SMMValued.field.LOW_BYTE0 + ,PKTValue1d.field.BYTE3,PKTValue1d.field.BYTE2 + ,PKTValue1d.field.BYTE1,PKTValue1d.field.BYTE0); + sprintf(msg1, "%d %d %d %d %d %d\n",SMMValued.field.LOW_BYTE1,SMMValued.field.LOW_BYTE0 + ,PKTValue2d.field.BYTE3,PKTValue2d.field.BYTE2 + ,PKTValue2d.field.BYTE1,PKTValue2d.field.BYTE0); + + retval=RtmpOSFileWrite(srcf, (PSTRING)msg, strlen(msg)); + retval=RtmpOSFileWrite(srcf, (PSTRING)msg1, strlen(msg1)); + } + } + } + else + { + DBGPRINT(RT_DEBUG_ERROR, ("--> Error src or srcf is null\n")); + return FALSE; + } + + retval=RtmpOSFileClose(srcf); + + if (retval) + { + DBGPRINT(RT_DEBUG_TRACE, ("--> Error %d closing %s\n", -retval, src)); + } + + RtmpOSFSInfoChange(&osFSInfo, FALSE); + + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BBP_R21_Ori); + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R60, BBP_R60_Ori); + + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R142, BBP_R142_ORI); + BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R142, BBP_R142_ORI); + RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, PBF_SYS_CTRL_ORI); + RTMP_IO_WRITE32(pAd, PBF_CAP_CTRL, PBF_CAP_CTRL_ORI); + + /* Finish */ + /* normal mode */ + RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MACValue); + MACValue &= ~0x00004000; + RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, MACValue); + + /* reset packet buffer */ + RTMP_IO_WRITE32(pAd, PBF_CTRL,0x00000020 ); + + /* enable Tx/Rx Queue */ + RTMP_IO_WRITE32(pAd, PBF_CFG, 0x00F40016); + RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0C); + pAd->ate.Mode = ATE_STOP; + + return TRUE; +} +#endif /* RLT_MAC */ + + +/* one-second periodic execution */ +VOID ATEPeriodicExec( + IN PVOID SystemSpecific1, + IN PVOID FunctionContext, + IN PVOID SystemSpecific2, + IN PVOID SystemSpecific3) +{ + PRTMP_ADAPTER pAd = (RTMP_ADAPTER *)FunctionContext; + PATE_INFO pATEInfo = &(pAd->ate); + + if (ATE_ON(pAd)) + { + pATEInfo->OneSecPeriodicRound++; + + /* for performace enchanement */ + NdisZeroMemory(&pAd->RalinkCounters, + (UINT32)&pAd->RalinkCounters.OneSecEnd - + (UINT32)&pAd->RalinkCounters.OneSecStart); + NICUpdateRawCounters(pAd); + + if (pATEInfo->bRxFER == 1) + { + pATEInfo->RxTotalCnt += pATEInfo->RxCntPerSec; + ate_print(KERN_EMERG "ATEPeriodicExec: Rx packet cnt = %d/%d\n", + pATEInfo->RxCntPerSec, pATEInfo->RxTotalCnt); + pATEInfo->RxCntPerSec = 0; + + if (pATEInfo->RxAntennaSel == 0) + ate_print(KERN_EMERG "ATEPeriodicExec: Rx AvgRssi0=%d, AvgRssi1=%d, AvgRssi2=%d\n\n", + pATEInfo->AvgRssi0, pATEInfo->AvgRssi1, pATEInfo->AvgRssi2); + else + ate_print(KERN_EMERG "ATEPeriodicExec: Rx AvgRssi=%d\n\n", pATEInfo->AvgRssi0); + } + + MlmeResetRalinkCounters(pAd); + + /* In QA Mode, QA will handle all registers. */ + if (pATEInfo->bQAEnabled == TRUE) + { + return; + } + + if ((pATEInfo->bAutoTxAlc == TRUE) + && ((pATEInfo->Mode == ATE_TXFRAME) || (pATEInfo->Mode == ATE_TXCONT))) + { + ATEAsicAdjustTxPower(pAd); + } + + ATEAsicExtraPowerOverMAC(pAd); + + //ATEAsicTemperCompensation(pAd); + + } + else + { + DBGPRINT_ERR(("%s is NOT called in ATE mode.\n", __FUNCTION__)); + } + + return; +} + diff --git a/cleopatre/devkit/mt7601udrv/ate/common/rt_qa.c b/cleopatre/devkit/mt7601udrv/ate/common/rt_qa.c new file mode 100644 index 0000000000..0f5dde5e9c --- /dev/null +++ b/cleopatre/devkit/mt7601udrv/ate/common/rt_qa.c @@ -0,0 +1,2497 @@ +/* + *************************************************************************** + * Ralink Tech Inc. + * 4F, No. 2 Technology 5th Rd. + * Science-based Industrial Park + * Hsin-chu, Taiwan, R.O.C. + * + * (c) Copyright 2002-2010, Ralink Technology, Inc. + * + * All rights reserved. Ralink's source code is an unpublished work and the + * use of a copyright notice does not imply otherwise. This source code + * contains confidential trade secret material of Ralink Tech. Any attemp + * or participation in deciphering, decoding, reverse engineering or in any + * way altering the source code is stricitly prohibited, unless the prior + * written consent of Ralink Technology, Inc. is obtained. + *************************************************************************** + + Module Name: + rt_qa.c + + Abstract: + + Revision History: + Who When What + -------- ---------- ---------------------------------------------- + Name Date Modification logs +*/ +#include "rt_config.h" + +#ifdef RALINK_QA +NDIS_STATUS TXSTOP( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0, atemode=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + UCHAR BbpData = 0; + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + atemode = pATEInfo->Mode; + pATEInfo->Mode &= ATE_TXSTOP; + pATEInfo->bQATxStart = FALSE; + + if (atemode == ATE_TXCARR) + { + if (pATEInfo->TxMethod == TX_METHOD_0) + { + /* No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0 */ + ATE_BBP_RESET_TX_MODE(pAd, BBP_R22, &BbpData); + } + } + else if (atemode == ATE_TXCARRSUPP) + { + if (pATEInfo->TxMethod == TX_METHOD_0) + { + /* No Cont. TX set BBP R22 bit7=0 */ + /* QA will do this in new TXCARRSUPP proposal */ + ATE_BBP_STOP_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + + /* No Carrier Suppression set BBP R24 bit0=0 */ + ATE_BBP_CTS_TX_SIN_WAVE_DISABLE(pAd, BBP_R24, &BbpData); + } + } + + /* + We should free some resource which was allocated + when ATE_TXFRAME, ATE_STOP, and ATE_TXCONT. + */ + else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP)) + { + if (atemode == ATE_TXCONT) + { + if (pATEInfo->TxMethod == TX_METHOD_0) + { + /* No Cont. TX set BBP R22 bit7=0 */ + /* QA will do this in new TXCONT proposal */ + ATE_BBP_STOP_CTS_TX_MODE(pAd, BBP_R22, &BbpData); + } + } + + +#ifdef RTMP_MAC_USB + RTUSBRejectPendingPackets(pAd); + RTUSBCleanUpDataBulkOutQueue(pAd); + RTUSBCleanUpMLMEBulkOutQueue(pAd); + + /* Abort Tx, RX DMA. */ + RtmpDmaEnable(pAd, 0); + while (pAd->PendingRx > 0) + { + ATE_RTUSBCancelPendingBulkInIRP(pAd); + RtmpOsMsDelay(500); + } + + while (((pAd->BulkOutPending[0] == TRUE) || + (pAd->BulkOutPending[1] == TRUE) || + (pAd->BulkOutPending[2] == TRUE) || + (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) + /* pAd->BulkFlags != 0 : wait bulk out finish */ + { + do + { + RTUSBCancelPendingBulkOutIRP(pAd); + } while (FALSE); + + RtmpOsMsDelay(500); + } + + ASSERT(pAd->PendingRx == 0); + + /* Enable Tx, Rx DMA. */ + RtmpDmaEnable(pAd, 1); +#endif /* RTMP_MAC_USB */ + } + + /* task Tx status : 0 --> task is idle, 1 --> task is running */ + pATEInfo->TxStatus = 0; + + if (pATEInfo->TxMethod == TX_METHOD_0) + { + BbpSoftReset(pAd);/* Soft reset BBP. */ + } + + /* Disable Tx */ + ATE_MAC_TX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + +#ifdef RTMP_MAC_USB + /* Clear ATE bulk in/out counter and continue setup */ + InterlockedExchange(&pAd->BulkOutRemained, 0); + pAd->ContinBulkOut = FALSE; +#endif /* RTMP_MAC_USB */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +NDIS_STATUS RXSTOP( + IN PRTMP_ADAPTER pAd) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 MacData=0; + NDIS_STATUS Status = NDIS_STATUS_SUCCESS; + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : ===> %s\n", __FUNCTION__)); + + /* Disable Rx */ + ATE_MAC_RX_DISABLE(pAd, MAC_SYS_CTRL, &MacData); + + pATEInfo->Mode &= ATE_RXSTOP; + pATEInfo->bQARxStart = FALSE; + +#ifdef RTMP_MAC_USB + RTUSBRejectPendingPackets(pAd); + RTUSBCleanUpDataBulkOutQueue(pAd); + + RTUSBCleanUpMLMEBulkOutQueue(pAd); + + /* Abort Tx, RX DMA. */ + RtmpDmaEnable(pAd, 0); + + while (pAd->PendingRx > 0) + { + ATE_RTUSBCancelPendingBulkInIRP(pAd); + RtmpOsMsDelay(500); + } + + while (((pAd->BulkOutPending[0] == TRUE) || + (pAd->BulkOutPending[1] == TRUE) || + (pAd->BulkOutPending[2] == TRUE) || + (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) + /* pAd->BulkFlags != 0 : wait bulk out finish */ + { + do + { + RTUSBCancelPendingBulkOutIRP(pAd); + } while (FALSE); + + RtmpOsMsDelay(500); + } + + ASSERT(pAd->PendingRx == 0); + pAd->ContinBulkIn = FALSE; +#endif /* RTMP_MAC_USB */ + + if ((!IS_RT3883(pAd)) && (!IS_RT3352(pAd)) && (!IS_RT5350(pAd))) + BbpSoftReset(pAd);/* Soft reset BBP. */ + + DBGPRINT(RT_DEBUG_TRACE, ("ATE : <=== %s\n", __FUNCTION__)); + return Status; +} + + +static VOID memcpy_exl(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len) +{ + UINT32 i, Value = 0; + UCHAR *pDst = NULL, *pSrc = NULL; + + for (i = 0 ; i < (len >> 2); i++) + { + pDst = (dst + i*4); + pSrc = (src + i*4); + /* For alignment issue, we need a variable "Value". */ + memmove(&Value, pSrc, 4); + Value = OS_HTONL(Value); + memmove(pDst, &Value, 4); + pDst += 4; + pSrc += 4; + } + + if ((len % 4) != 0) + { + /* wish that it will never reach here */ + memmove(&Value, pSrc, (len % 4)); + Value = OS_HTONL(Value); + memmove(pDst, &Value, (len % 4)); + } +} + + +static VOID memcpy_exs(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len) +{ + ULONG i; + { + USHORT *pDst, *pSrc; + + pDst = (USHORT *) dst; + pSrc = (USHORT *) src; + + for (i =0; i < (len >> 1); i++) + { + *pDst = OS_NTOHS(*pSrc); + pDst++; + pSrc++; + } + + if ((len % 2) != 0) + { + memcpy(pDst, pSrc, (len % 2)); + *pDst = OS_NTOHS(*pDst); + } + } + return; +} + + +static VOID RTMP_IO_READ_BULK(PRTMP_ADAPTER pAd, UCHAR *dst, UINT32 offset, UINT32 len) +{ + UINT32 i, Value = 0; + UCHAR *pDst; + + for (i = 0 ; i < (len >> 2); i++) + { + pDst = (dst + (i << 2)); + RTMP_IO_READ32(pAd, offset, &Value); + Value = OS_HTONL(Value); + memmove(pDst, &Value, 4); + offset += 4; + } + return; +} + + +VOID BubbleSort(INT32 size, INT32 array[]) +{ + INT32 outer, inner, temp; + + for (outer = size-1; outer>0; outer--) + { + for (inner = 0; inner array[inner+1]) + { + temp = array[inner]; + array[inner]=array[inner+1]; + array[inner+1]=temp; + } + } + } + return; +} + + +VOID CalNoiseLevel(PRTMP_ADAPTER pAd, UCHAR channel, INT32 RSSI[3][10]) +{ + PATE_INFO pATEInfo = &(pAd->ate); + INT32 RSSI0, RSSI1, RSSI2; + CHAR Rssi0Offset, Rssi1Offset, Rssi2Offset; + UCHAR BbpR50Rssi0 = 0, BbpR51Rssi1 = 0, BbpR52Rssi2 = 0; + UCHAR Org_BBP66value = 0, Org_BBP69value = 0, Org_BBP70value = 0, data = 0; + USHORT LNA_Gain = 0; + INT32 column = 0; + UCHAR Org_Channel = pATEInfo->Channel; + USHORT GainValue = 0, OffsetValue = 0; + + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &Org_BBP66value); + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R69, &Org_BBP69value); + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R70, &Org_BBP70value); + + /************************************************************************/ + /* Read the value of LNA gain and RSSI offset */ + /************************************************************************/ + RT28xx_EEPROM_READ16(pAd, EEPROM_LNA_OFFSET, GainValue); + + /* for Noise Level */ + if (channel <= 14) + { + LNA_Gain = GainValue & 0x00FF; + + RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET, OffsetValue); + Rssi0Offset = OffsetValue & 0x00FF; + Rssi1Offset = (OffsetValue & 0xFF00) >> 8; + + RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_BG_OFFSET + 2)/* 0x48 */, OffsetValue); + Rssi2Offset = OffsetValue & 0x00FF; + } + else + { + LNA_Gain = (GainValue & 0xFF00) >> 8; + + RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_A_OFFSET, OffsetValue); + Rssi0Offset = OffsetValue & 0x00FF; + Rssi1Offset = (OffsetValue & 0xFF00) >> 8; + + RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_A_OFFSET + 2)/* 0x4C */, OffsetValue); + Rssi2Offset = OffsetValue & 0x00FF; + } + /***********************************************************************/ + { + pATEInfo->Channel = channel; + ATEAsicSwitchChannel(pAd); + RtmpOsMsDelay(5); + + data = 0x10; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, data); + data = 0x40; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, data); + data = 0x40; + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, data); + RtmpOsMsDelay(5); + + /* start Rx */ + pATEInfo->bQARxStart = TRUE; + Set_ATE_Proc(pAd, "RXFRAME"); + + RtmpOsMsDelay(5); + + for (column = 0; column < 10; column++) + { + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R50, &BbpR50Rssi0); + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R51, &BbpR51Rssi1); + ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R52, &BbpR52Rssi2); + + RtmpOsMsDelay(10); + + /* calculate RSSI 0 */ + if (BbpR50Rssi0 == 0) + { + RSSI0 = -100; + } + else + { + RSSI0 = (INT32)(-12 - BbpR50Rssi0 - LNA_Gain - Rssi0Offset); + } + RSSI[0][column] = RSSI0; + + if ( pAd->Antenna.field.RxPath >= 2 ) /* 2R */ + { + /* calculate RSSI 1 */ + if (BbpR51Rssi1 == 0) + { + RSSI1 = -100; + } + else + { + RSSI1 = (INT32)(-12 - BbpR51Rssi1 - LNA_Gain - Rssi1Offset); + } + RSSI[1][column] = RSSI1; + } + + if ( pAd->Antenna.field.RxPath >= 3 ) /* 3R */ + { + /* calculate RSSI 2 */ + if (BbpR52Rssi2 == 0) + RSSI2 = -100; + else + RSSI2 = (INT32)(-12 - BbpR52Rssi2 - LNA_Gain - Rssi2Offset); + + RSSI[2][column] = RSSI2; + } + } + + /* stop Rx */ + Set_ATE_Proc(pAd, "RXSTOP"); + + RtmpOsMsDelay(5); + + BubbleSort(10, RSSI[0]); /* 1R */ + + if ( pAd->Antenna.field.RxPath >= 2 ) /* 2R */ + { + BubbleSort(10, RSSI[1]); + } + + if ( pAd->Antenna.field.RxPath >= 3 ) /* 3R */ + { + BubbleSort(10, RSSI[2]); + } + } + + pATEInfo->Channel = Org_Channel; + ATEAsicSwitchChannel(pAd); + + /* restore original value */ + + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, Org_BBP69value); + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, Org_BBP70value); + + return; +} + + +static VOID ATE_BBPRead( + IN PRTMP_ADAPTER pAd, + IN UCHAR offset, + IN UCHAR *pValue) +{ + if (ATE_ON(pAd)) + { + ATE_BBP_IO_READ8_BY_REG_ID(pAd, offset, pValue); + } + else + { + RTMP_BBP_IO_READ8_BY_REG_ID(pAd, offset, pValue); + } +} + + +static VOID ATE_BBPWrite( + IN PRTMP_ADAPTER pAd, + IN UCHAR offset, + IN UCHAR value) +{ + if (ATE_ON(pAd)) + { + ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, offset, value); + } + else + { + RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, offset, value); + } +} + + +BOOLEAN SyncTxRxConfig(PRTMP_ADAPTER pAd, USHORT offset, UCHAR value) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UCHAR tmp = 0, bbp_data = 0; + + ATE_BBPRead(pAd, offset, &bbp_data); + + /* confirm again */ + ASSERT(bbp_data == value); + + switch (offset) + { + case BBP_R1: + /* Need to synchronize tx configuration with legacy ATE. */ + tmp = (bbp_data & ((1 << 4) | (1 << 3))/* 0x18 */) >> 3; + switch (tmp) + { + /* The BBP R1 bit[4:3] = 2 :: Both DACs will be used by QA. */ + case 2: + /* All */ + pATEInfo->TxAntennaSel = 0; + break; + /* The BBP R1 bit[4:3] = 0 :: DAC 0 will be used by QA. */ + case 0: + /* Antenna one */ + pATEInfo->TxAntennaSel = 1; + break; + /* The BBP R1 bit[4:3] = 1 :: DAC 1 will be used by QA. */ + case 1: + /* Antenna two */ + pATEInfo->TxAntennaSel = 2; + break; + default: + DBGPRINT_ERR(("%s -- Sth. wrong! : return FALSE; \n", __FUNCTION__)); + return FALSE; + } + break;/* case BBP_R1 */ + + case BBP_R3: + /* Need to synchronize rx configuration with legacy ATE. */ + tmp = (bbp_data & ((1 << 1) | (1 << 0))/* 0x03 */); + switch(tmp) + { + /* The BBP R3 bit[1:0] = 3 :: All ADCs will be used by QA. */ + case 3: + /* All */ + pATEInfo->RxAntennaSel = 0; + break; + /* + The BBP R3 bit[1:0] = 0 :: ADC 0 will be used by QA, + unless the BBP R3 bit[4:3] = 2 + */ + case 0: + /* Antenna one */ + pATEInfo->RxAntennaSel = 1; + tmp = ((bbp_data & ((1 << 4) | (1 << 3))/* 0x03 */) >> 3); + if (tmp == 2) /* 3R */ + { + /* Default : All ADCs will be used by QA */ + pATEInfo->RxAntennaSel = 0; + } + break; + /* The BBP R3 bit[1:0] = 1 :: ADC 1 will be used by QA. */ + case 1: + /* Antenna two */ + pATEInfo->RxAntennaSel = 2; + break; + /* The BBP R3 bit[1:0] = 2 :: ADC 2 will be used by QA. */ + case 2: + /* Antenna three */ + pATEInfo->RxAntennaSel = 3; + break; + default: + DBGPRINT_ERR(("%s -- Impossible! : return FALSE; \n", __FUNCTION__)); + return FALSE; + } + break;/* case BBP_R3 */ + + default: + DBGPRINT_ERR(("%s -- Sth. wrong! : return FALSE; \n", __FUNCTION__)); + return FALSE; + + } + return TRUE; +} + + +static INT ResponseToGUI( + IN struct ate_racfghdr *pRaCfg, + IN RTMP_IOCTL_INPUT_STRUCT *pwrq, + IN INT Length, + IN INT Status) +{ + (pRaCfg)->length = OS_HTONS((Length)); + (pRaCfg)->status = OS_HTONS((Status)); + (pwrq)->u.data.length = sizeof((pRaCfg)->magic_no) + sizeof((pRaCfg)->command_type) + + sizeof((pRaCfg)->command_id) + sizeof((pRaCfg)->length) + + sizeof((pRaCfg)->sequence) + OS_NTOHS((pRaCfg)->length); + DBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", (pwrq)->u.data.length)); + + if (copy_to_user((pwrq)->u.data.pointer, (UCHAR *)(pRaCfg), (pwrq)->u.data.length)) + { + + DBGPRINT_ERR(("copy_to_user() fail in %s\n", __FUNCTION__)); + return (-EFAULT); + } + else + { + DBGPRINT(RT_DEBUG_TRACE, ("RACFG command(0x%04x)[magic number(0x%08x)] is done\n", + OS_NTOHS(pRaCfg->command_id), OS_NTOHL(pRaCfg->magic_no))); + } + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_START( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START\n")); + + pATEInfo->bQAEnabled = TRUE; + DBGPRINT(RT_DEBUG_TRACE,("pATEInfo->bQAEnabled = %s\n", (pATEInfo->bQAEnabled)? "TRUE":"FALSE")); + + /* Prepare feedback as soon as we can to avoid QA timeout. */ + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + +#ifdef CONFIG_RT2880_ATE_CMD_NEW + Set_ATE_Proc(pAd, "ATESTART"); +#else + Set_ATE_Proc(pAd, "APSTOP"); +#endif /* CONFIG_RT2880_ATE_CMD_NEW */ + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_STOP( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + INT32 ret; + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_STOP\n")); + + pATEInfo->bQAEnabled = FALSE; + DBGPRINT(RT_DEBUG_TRACE,("pATEInfo->bQAEnabled = %s\n", (pATEInfo->bQAEnabled)? "TRUE":"FALSE")); + + /* + Distinguish this command came from QA(via ate agent) + or ate agent according to the existence of pid in payload. + + No need to prepare feedback if this cmd came directly from ate agent, + not from QA. + */ + pRaCfg->length = OS_NTOHS(pRaCfg->length); + + if (pRaCfg->length == sizeof(pATEInfo->AtePid)) + { + /* + This command came from QA. + Get the pid of ATE agent. + */ + memcpy((UCHAR *)&pATEInfo->AtePid, + (&pRaCfg->data[0]) - 2/* == sizeof(pRaCfg->status) */, + sizeof(pATEInfo->AtePid)); + + /* Prepare feedback as soon as we can to avoid QA timeout. */ + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + /* Kill ATE agent when leaving ATE mode. */ +#ifdef LINUX + ret = RTMP_THREAD_PID_KILL(pATEInfo->AtePid); + if (ret) + DBGPRINT_ERR(("%s : unable to kill ate thread\n", RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev))); +#endif /* LINUX */ + } + + + /* AP/STA may be already in ATE_STOP mode due to cmd from QA. */ + if (ATE_ON(pAd)) + { + /* Someone has killed ate agent while QA GUI is still open. */ + +#ifdef CONFIG_RT2880_ATE_CMD_NEW + Set_ATE_Proc(pAd, "ATESTOP"); +#else + Set_ATE_Proc(pAd, "APSTART"); +#endif + DBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_AP_START is done !\n")); + } + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_RF_WRITE_ALL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + UINT32 R1, R2, R3, R4; + USHORT channel; + + memcpy(&R1, pRaCfg->data-2, 4); + memcpy(&R2, pRaCfg->data+2, 4); + memcpy(&R3, pRaCfg->data+6, 4); + memcpy(&R4, pRaCfg->data+10, 4); + memcpy(&channel, pRaCfg->data+14, 2); + + pAd->LatchRfRegs.R1 = OS_NTOHL(R1); + pAd->LatchRfRegs.R2 = OS_NTOHL(R2); + pAd->LatchRfRegs.R3 = OS_NTOHL(R3); + pAd->LatchRfRegs.R4 = OS_NTOHL(R4); + pAd->LatchRfRegs.Channel = OS_NTOHS(channel); + + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R3); + RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_E2PROM_READ16( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + UINT16 offset=0, value=0; + USHORT tmp=0; + + offset = OS_NTOHS(pRaCfg->status); + RT28xx_EEPROM_READ16(pAd, offset, tmp); + value = tmp; + value = OS_HTONS(value); + + DBGPRINT(RT_DEBUG_TRACE,("EEPROM Read offset = 0x%04x, value = 0x%04x\n", offset, value)); + memcpy(pRaCfg->data, &value, 2); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+2, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_E2PROM_WRITE16( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT offset, value; + + offset = OS_NTOHS(pRaCfg->status); + memcpy(&value, pRaCfg->data, 2); + value = OS_NTOHS(value); + RT28xx_EEPROM_WRITE16(pAd, offset, value); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_E2PROM_READ_ALL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT buffer[EEPROM_SIZE >> 1]; + + rt_ee_read_all(pAd,(USHORT *)buffer); + memcpy_exs(pAd, pRaCfg->data, (UCHAR *)buffer, EEPROM_SIZE); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+EEPROM_SIZE, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_E2PROM_WRITE_ALL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT buffer[EEPROM_SIZE >> 1]; + + NdisZeroMemory((UCHAR *)buffer, EEPROM_SIZE); + memcpy_exs(pAd, (UCHAR *)buffer, (UCHAR *)&pRaCfg->status, EEPROM_SIZE); + rt_ee_write_all(pAd,(USHORT *)buffer); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_IO_READ( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + UINT32 offset; + UINT32 value; + + memcpy(&offset, &pRaCfg->status, 4); + offset = OS_NTOHL(offset); + + { + /* + We do not need the base address. + So just extract the offset out. + */ + offset &= 0x0000FFFF; + RTMP_IO_READ32(pAd, offset, &value); + } + value = OS_HTONL(value); + memcpy(pRaCfg->data, &value, 4); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+4, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_IO_WRITE( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + UINT32 offset, value; + + memcpy(&offset, pRaCfg->data-2, 4); + memcpy(&value, pRaCfg->data+2, 4); + + offset = OS_NTOHL(offset); + + /* + We do not need the base address. + So just extract the offset out. + */ + offset &= 0x0000FFFF; + value = OS_NTOHL(value); + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_IO_WRITE: offset = %x, value = %x\n", offset, value)); + RTMP_IO_WRITE32(pAd, offset, value); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_IO_READ_BULK( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + UINT32 offset; + USHORT len; + + memcpy(&offset, &pRaCfg->status, 4); + offset = OS_NTOHL(offset); + + offset &= 0x0000FFFF; + memcpy(&len, pRaCfg->data+2, 2); + len = OS_NTOHS(len); + + if (len > 371) + { + DBGPRINT_ERR(("%s : length requested is too large, make it smaller\n", __FUNCTION__)); + pRaCfg->length = OS_HTONS(2); + pRaCfg->status = OS_HTONS(1); + + return -EFAULT; + } + + RTMP_IO_READ_BULK(pAd, pRaCfg->data, offset, (len << 2));/* unit in four bytes*/ + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+(len << 2), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_BBP_READ8( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT offset; + UCHAR value; + + value = 0; + offset = OS_NTOHS(pRaCfg->status); + + ATE_BBPRead(pAd, offset, &value); + + pRaCfg->data[0] = value; + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+1, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_BBP_WRITE8( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT offset; + UCHAR value; + + offset = OS_NTOHS(pRaCfg->status); + memcpy(&value, pRaCfg->data, 1); + ATE_BBPWrite(pAd, offset, value); + + if ((offset == BBP_R1) || (offset == BBP_R3)) + { + SyncTxRxConfig(pAd, offset, value); + } + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_BBP_READ_ALL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT bbp_reg_index; + + for (bbp_reg_index = 0; bbp_reg_index < pAd->chipCap.MaxNumOfBbpId+1; bbp_reg_index++) + { + pRaCfg->data[bbp_reg_index] = 0; + ATE_BBPRead(pAd, bbp_reg_index, &pRaCfg->data[bbp_reg_index]); + } + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+ pAd->chipCap.MaxNumOfBbpId+1, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_GET_NOISE_LEVEL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + UCHAR channel; + INT32 buffer[3][10];/* 3 : RxPath ; 10 : no. of per rssi samples */ + + channel = (OS_NTOHS(pRaCfg->status) & 0x00FF); + CalNoiseLevel(pAd, channel, buffer); + memcpy_exl(pAd, (UCHAR *)pRaCfg->data, (UCHAR *)&(buffer[0][0]), (sizeof(INT32)*3*10)); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+(sizeof(INT32)*3*10), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + + + +static INT DO_RACFG_CMD_GET_COUNTER( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + memcpy_exl(pAd, &pRaCfg->data[0], (UCHAR *)&pATEInfo->U2M, 4); + memcpy_exl(pAd, &pRaCfg->data[4], (UCHAR *)&pATEInfo->OtherData, 4); + memcpy_exl(pAd, &pRaCfg->data[8], (UCHAR *)&pATEInfo->Beacon, 4); + memcpy_exl(pAd, &pRaCfg->data[12], (UCHAR *)&pATEInfo->OtherCount, 4); + memcpy_exl(pAd, &pRaCfg->data[16], (UCHAR *)&pATEInfo->TxAc0, 4); + memcpy_exl(pAd, &pRaCfg->data[20], (UCHAR *)&pATEInfo->TxAc1, 4); + memcpy_exl(pAd, &pRaCfg->data[24], (UCHAR *)&pATEInfo->TxAc2, 4); + memcpy_exl(pAd, &pRaCfg->data[28], (UCHAR *)&pATEInfo->TxAc3, 4); + memcpy_exl(pAd, &pRaCfg->data[32], (UCHAR *)&pATEInfo->TxHCCA, 4); + memcpy_exl(pAd, &pRaCfg->data[36], (UCHAR *)&pATEInfo->TxMgmt, 4); + memcpy_exl(pAd, &pRaCfg->data[40], (UCHAR *)&pATEInfo->RSSI0, 4); + memcpy_exl(pAd, &pRaCfg->data[44], (UCHAR *)&pATEInfo->RSSI1, 4); + memcpy_exl(pAd, &pRaCfg->data[48], (UCHAR *)&pATEInfo->RSSI2, 4); + memcpy_exl(pAd, &pRaCfg->data[52], (UCHAR *)&pATEInfo->SNR0, 4); + memcpy_exl(pAd, &pRaCfg->data[56], (UCHAR *)&pATEInfo->SNR1, 4); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+60, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_CLEAR_COUNTER( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + pATEInfo->U2M = 0; + pATEInfo->OtherData = 0; + pATEInfo->Beacon = 0; + pATEInfo->OtherCount = 0; + pATEInfo->TxAc0 = 0; + pATEInfo->TxAc1 = 0; + pATEInfo->TxAc2 = 0; + pATEInfo->TxAc3 = 0; + pATEInfo->TxHCCA = 0; + pATEInfo->TxMgmt = 0; + pATEInfo->TxDoneCount = 0; + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_TX_START( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + USHORT *p; + USHORT err = 1; + UINT8 TXWISize = pAd->chipCap.TXWISize; + UINT8 TxInfoSize = 4; + + if ((pATEInfo->TxStatus != 0) && (pATEInfo->Mode & ATE_TXFRAME)) + { + DBGPRINT_ERR(("%s : Ate Tx is already running," + "to run next Tx, you must stop it first\n", __FUNCTION__)); + err = 2; + goto tx_start_error; + } + else if ((pATEInfo->TxStatus != 0) && !(pATEInfo->Mode & ATE_TXFRAME)) + { + int slot = 0; + + while ((slot++ < 10) && (pATEInfo->TxStatus != 0)) + { + RtmpOsMsDelay(5); + } + + /* force it to stop */ + pATEInfo->TxStatus = 0; + pATEInfo->TxDoneCount = 0; + pATEInfo->bQATxStart = FALSE; + } + + /* + Reset ATE mode and set Tx/Rx idle + for new proposed TXCONT/TXCARR/TXCARRSUPP solution. + */ + if ((pATEInfo->Mode & ATE_TXFRAME) && (pATEInfo->TxMethod == TX_METHOD_1)) + { + TXSTOP(pAd); + } + + /* + If pRaCfg->length == 0, this "RACFG_CMD_TX_START" + is for Carrier test or Carrier Suppression test. + */ + if (OS_NTOHS(pRaCfg->length) != 0) + { + /* get frame info */ +#ifdef RTMP_MAC_USB + NdisMoveMemory(&pATEInfo->TxInfo, pRaCfg->data - 2, TxInfoSize); +#ifdef RT_BIG_ENDIAN + RTMPDescriptorEndianChange((PUCHAR) &pATEInfo->TxInfo, TYPE_TXINFO); +#endif /* RT_BIG_ENDIAN */ +#endif /* RTMP_MAC_USB */ + + NdisMoveMemory(&pATEInfo->TxWI, pRaCfg->data + 2, TXWISize); +#ifdef RT_BIG_ENDIAN + RTMPWIEndianChange(pAd, (PUCHAR)&pATEInfo->TxWI, TYPE_TXWI); +#endif /* RT_BIG_ENDIAN */ + + NdisMoveMemory(&pATEInfo->TxCount, pRaCfg->data + TXWISize + 2, 4); + pATEInfo->TxCount = OS_NTOHL(pATEInfo->TxCount); + +/* p = (USHORT *)(&pRaCfg->data[TXWISize + TxInfoSize + 2]); */ + + /* always use QID_AC_BE */ + pATEInfo->QID = 0; + + p = (USHORT *)(&pRaCfg->data[TXWISize + TxInfoSize + 2*2]); + pATEInfo->HLen = OS_NTOHS(*p); + + if (pATEInfo->HLen > 32) + { + DBGPRINT_ERR(("%s : pATEInfo->HLen > 32\n", __FUNCTION__)); + DBGPRINT_ERR(("pATEInfo->HLen = %d\n", pATEInfo->HLen)); + err = 3; + goto tx_start_error; + } + + NdisMoveMemory(&pATEInfo->Header, pRaCfg->data + (TXWISize + TxInfoSize + 2*3), pATEInfo->HLen); + + pATEInfo->PLen = OS_NTOHS(pRaCfg->length) - (pATEInfo->HLen + (TXWISize + TxInfoSize + 2*4)); + + if (pATEInfo->PLen > 32) + { + DBGPRINT_ERR(("%s : pATEInfo->PLen > 32\n", __FUNCTION__)); + err = 4; + goto tx_start_error; + } + + NdisMoveMemory(&pATEInfo->Pattern, pRaCfg->data + (TXWISize + TxInfoSize + 2*3) + pATEInfo->HLen, pATEInfo->PLen); + pATEInfo->DLen = pATEInfo->TxWI.TxWIMPDUByteCnt - pATEInfo->HLen; + + + } + + ReadQATxTypeFromBBP(pAd); + + if (pATEInfo->bQATxStart == TRUE) + { + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + return NDIS_STATUS_SUCCESS; + } + +tx_start_error: + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), err); + + return err; +} + + +static INT DO_RACFG_CMD_GET_TX_STATUS( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + UINT32 count=0; + + count = OS_HTONL(pATEInfo->TxDoneCount); + NdisMoveMemory(pRaCfg->data, &count, 4); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+4, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_TX_STOP( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_TX_STOP\n")); + + Set_ATE_Proc(pAd, "TXSTOP"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_RX_START( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n")); + + pATEInfo->bQARxStart = TRUE; + Set_ATE_Proc(pAd, "RXFRAME"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_RX_STOP( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_STOP\n")); + + Set_ATE_Proc(pAd, "RXSTOP"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_START_TX_CARRIER( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CARRIER\n")); + + Set_ATE_Proc(pAd, "TXCARR"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_START_TX_CONT( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CONT\n")); + + Set_ATE_Proc(pAd, "TXCONT"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_START_TX_FRAME( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_FRAME\n")); + + Set_ATE_Proc(pAd, "TXFRAME"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_BW( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_BW\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + + Set_ATE_TX_BW_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_TX_POWER0( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER0\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_POWER0_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_TX_POWER1( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER1\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_POWER1_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +#ifdef DOT11N_SS3_SUPPORT +static INT DO_RACFG_CMD_ATE_SET_TX_POWER2( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER2\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_POWER2_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} +#endif /* DOT11N_SS3_SUPPORT */ + + +static INT DO_RACFG_CMD_ATE_SET_FREQ_OFFSET( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_FREQ_OFFSET\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_FREQ_OFFSET_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_GET_STATISTICS( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_GET_STATISTICS\n")); + + memcpy_exl(pAd, &pRaCfg->data[0], (UCHAR *)&pATEInfo->TxDoneCount, 4); + memcpy_exl(pAd, &pRaCfg->data[4], (UCHAR *)&pAd->WlanCounters.RetryCount.u.LowPart, 4); + memcpy_exl(pAd, &pRaCfg->data[8], (UCHAR *)&pAd->WlanCounters.FailedCount.u.LowPart, 4); + memcpy_exl(pAd, &pRaCfg->data[12], (UCHAR *)&pAd->WlanCounters.RTSSuccessCount.u.LowPart, 4); + memcpy_exl(pAd, &pRaCfg->data[16], (UCHAR *)&pAd->WlanCounters.RTSFailureCount.u.LowPart, 4); + memcpy_exl(pAd, &pRaCfg->data[20], (UCHAR *)&pAd->WlanCounters.ReceivedFragmentCount.QuadPart, 4); + memcpy_exl(pAd, &pRaCfg->data[24], (UCHAR *)&pAd->WlanCounters.FCSErrorCount.u.LowPart, 4); + memcpy_exl(pAd, &pRaCfg->data[28], (UCHAR *)&pAd->Counters8023.RxNoBuffer, 4); + memcpy_exl(pAd, &pRaCfg->data[32], (UCHAR *)&pAd->WlanCounters.FrameDuplicateCount.u.LowPart, 4); + memcpy_exl(pAd, &pRaCfg->data[36], (UCHAR *)&pAd->RalinkCounters.OneSecFalseCCACnt, 4); + + if (pATEInfo->RxAntennaSel == 0) + { + INT32 RSSI0 = 0; + INT32 RSSI1 = 0; + INT32 RSSI2 = 0; + + RSSI0 = (INT32)(pATEInfo->LastRssi0 - pAd->BbpRssiToDbmDelta); + RSSI1 = (INT32)(pATEInfo->LastRssi1 - pAd->BbpRssiToDbmDelta); + RSSI2 = (INT32)(pATEInfo->LastRssi2 - pAd->BbpRssiToDbmDelta); + memcpy_exl(pAd, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4); + memcpy_exl(pAd, &pRaCfg->data[44], (UCHAR *)&RSSI1, 4); + memcpy_exl(pAd, &pRaCfg->data[48], (UCHAR *)&RSSI2, 4); + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+52, NDIS_STATUS_SUCCESS); + } + else + { + INT32 RSSI0 = 0; + + RSSI0 = (INT32)(pATEInfo->LastRssi0 - pAd->BbpRssiToDbmDelta); + memcpy_exl(pAd, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4); + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+44, NDIS_STATUS_SUCCESS); + } + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_RESET_COUNTER( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + SHORT value = 1; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_RESET_COUNTER\n")); + + snprintf((char *)str, sizeof(str), "%d", value); + Set_ResetStatCounter_Proc(pAd, str); + + pATEInfo->TxDoneCount = 0; + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SEL_TX_ANTENNA( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_TX_ANTENNA\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_Antenna_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SEL_RX_ANTENNA( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_RX_ANTENNA\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_RX_Antenna_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_PREAMBLE( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_PREAMBLE\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_MODE_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_CHANNEL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_CHANNEL\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_CHANNEL_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_ADDR1( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR1\n")); + memcpy(pATEInfo->Addr1, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_ADDR2( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR2\n")); + memcpy(pATEInfo->Addr2, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_ADDR3( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR3\n")); + memcpy(pATEInfo->Addr3, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_RATE( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_RATE\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_MCS_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_TX_FRAME_LEN( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_LEN\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_LENGTH_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_SET_TX_FRAME_COUNT( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_COUNT\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + + { + snprintf((char *)str, sizeof(str), "%d", value); + Set_ATE_TX_COUNT_Proc(pAd, str); + } + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_START_RX_FRAME( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + DBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n")); + + Set_ATE_Proc(pAd, "RXFRAME"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_E2PROM_READ_BULK( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT offset; + USHORT len; + USHORT buffer[EEPROM_SIZE >> 1]; + + offset = OS_NTOHS(pRaCfg->status); + memcpy(&len, pRaCfg->data, 2); + len = OS_NTOHS(len); + + rt_ee_read_all(pAd, (USHORT *)buffer); + + if (offset + len <= EEPROM_SIZE) + memcpy_exs(pAd, pRaCfg->data, (UCHAR *)buffer+offset, len); + else + DBGPRINT_ERR(("%s : exceed EEPROM size\n", __FUNCTION__)); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+len, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_E2PROM_WRITE_BULK( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT offset; + USHORT len; + USHORT buffer[EEPROM_SIZE >> 1]; + + offset = OS_NTOHS(pRaCfg->status); + memcpy(&len, pRaCfg->data, 2); + len = OS_NTOHS(len); + + memcpy_exs(pAd, (UCHAR *)buffer + offset, (UCHAR *)pRaCfg->data + 2, len); + + if ((offset + len) <= EEPROM_SIZE) + { + rt_ee_write_bulk(pAd,(USHORT *)(((UCHAR *)buffer) + offset), offset, len); + } + else + { + DBGPRINT_ERR(("%s : exceed EEPROM size(%d)\n", __FUNCTION__, EEPROM_SIZE)); + DBGPRINT_ERR(("offset=%d\n", offset)); + DBGPRINT_ERR(("length=%d\n", len)); + DBGPRINT_ERR(("offset+length=%d\n", (offset+len))); + } + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_IO_WRITE_BULK( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + UINT32 offset, pos, value; + USHORT len; + + memcpy(&offset, &pRaCfg->status, 4); + offset = OS_NTOHL(offset); + memcpy(&len, pRaCfg->data+2, 2); + len = OS_NTOHS(len); + + for (pos = 0; pos < len; pos += 4) + { + memcpy_exl(pAd, (UCHAR *)&value, pRaCfg->data+4+pos, 4); + DBGPRINT(RT_DEBUG_TRACE,("Write %x %x\n", offset + pos, value)); + RTMP_IO_WRITE32(pAd, ((offset+pos) & (0xffff)), value); + } + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_BBP_READ_BULK( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT offset; + USHORT len; + USHORT pos; + + offset = OS_NTOHS(pRaCfg->status); + memcpy(&len, pRaCfg->data, 2); + len = OS_NTOHS(len); + + for (pos = offset; pos < (offset+len); pos++) + { + pRaCfg->data[pos - offset] = 0; + + ATE_BBPRead(pAd, pos, &pRaCfg->data[pos - offset]); + } + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status)+len, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_BBP_WRITE_BULK( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT offset; + USHORT len; + USHORT pos; + UCHAR *value; + + offset = OS_NTOHS(pRaCfg->status); + memcpy(&len, pRaCfg->data, 2); + len = OS_NTOHS(len); + + for (pos = offset; pos < (offset+len); pos++) + { + value = pRaCfg->data + 2 + (pos - offset); + ATE_BBPWrite(pAd, pos, *value); + } + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + + + + + + + +#ifdef TXBF_SUPPORT +static INT DO_RACFG_CMD_ATE_TXBF_DUT_INIT( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + DBGPRINT(RT_DEBUG_TRACE,("DO_RACFG_CMD_ATE_TXBF_DUT_INIT\n")); + + Set_ATE_TXBF_INIT_Proc(pAd, "1"); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_TXBF_LNA_CAL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT band; + CHAR bandStr[32] = {0}; + + DBGPRINT(RT_DEBUG_TRACE,("DO_RACFG_CMD_ATE_TXBF_LNA_CAL\n")); + + band = OS_NTOHS(pRaCfg->status); + DBGPRINT(RT_DEBUG_TRACE, ("%s : band=0x%x(0x%x)\n", + __FUNCTION__, band, pRaCfg->status)); + snprintf(bandStr, sizeof(bandStr), "%d\n", band); + Set_ATE_TXBF_LNACAL_Proc(pAd, &bandStr[0]); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_TXBF_DIV_CAL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + USHORT band; + CHAR bandStr[32] = {0}; + + DBGPRINT(RT_DEBUG_TRACE,("DO_RACFG_CMD_ATE_TXBF_DIV_CAL\n")); + + band = OS_NTOHS(pRaCfg->status); + DBGPRINT(RT_DEBUG_TRACE, ("%s : band=0x%x(0x%x)\n", + __FUNCTION__, band, pRaCfg->status)); + snprintf(bandStr, sizeof(bandStr), "%d\n", band); + Set_ATE_TXBF_DIVCAL_Proc(pAd, &bandStr[0]); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_TXBF_PHASE_CAL( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + BOOLEAN result = FALSE; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("DO_RACFG_CMD_ATE_TXBF_PHASE_CAL\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + + result = (BOOLEAN)Set_ATE_TXBF_CAL_Proc(pAd, str); + pRaCfg->data[0] = result; + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status) + 1, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_TXBF_GOLDEN_INIT( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + SHORT value = 0; + STRING str[LEN_OF_ARG]; + + NdisZeroMemory(str, LEN_OF_ARG); + + DBGPRINT(RT_DEBUG_TRACE,("DO_RACFG_CMD_ATE_TXBF_GOLDEN_INIT\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + + Set_ATE_TXBF_GOLDEN_Proc(pAd, str); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_TXBF_VERIFY( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + SHORT value = 0; + STRING str[LEN_OF_ARG]; + BOOLEAN result; + + DBGPRINT(RT_DEBUG_TRACE,("DO_RACFG_CMD_ATE_TXBF_VERIFY\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + + result = (BOOLEAN)Set_ATE_TXBF_VERIFY_Proc(pAd, str); + + pRaCfg->data[0] = result; + pRaCfg->data[1] = pATEInfo->calParams[0]; + pRaCfg->data[2] = pATEInfo->calParams[1]; + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status) + 3, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} + + +static INT DO_RACFG_CMD_ATE_TXBF_VERIFY_NOCOMP( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + SHORT value = 0; + STRING str[LEN_OF_ARG]; + BOOLEAN result; + + DBGPRINT(RT_DEBUG_TRACE,("DO_RACFG_CMD_ATE_TXBF_VERIFY_NOCOMP\n")); + + memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2); + value = OS_NTOHS(value); + snprintf((char *)str, sizeof(str), "%d", value); + + result = (BOOLEAN)Set_ATE_TXBF_VERIFY_NoComp_Proc(pAd, str); + + pRaCfg->data[0] = result; + pRaCfg->data[1] = pATEInfo->calParams[0]; + pRaCfg->data[2] = pATEInfo->calParams[1]; + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status) + 3, NDIS_STATUS_SUCCESS); + + return NDIS_STATUS_SUCCESS; +} +#endif /* TXBF_SUPPORT */ + + +static INT32 DO_RACFG_CMD_ATE_SHOW_PARAM( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + INT32 Status = NDIS_STATUS_SUCCESS; + UINT32 Len; + ATE_EX_PARAM ATEExParam; + + ATEExParam.mode = pATEInfo->Mode; + ATEExParam.TxPower0 = pATEInfo->TxPower0; + ATEExParam.TxPower1 = pATEInfo->TxPower1; + +#ifdef DOT11N_SS3_SUPPORT + ATEExParam.TxPower2 = pATEInfo->TxPower2; +#endif /* DOT11N_SS3_SUPPORT */ + + ATEExParam.TxAntennaSel = pATEInfo->TxAntennaSel; + ATEExParam.RxAntennaSel = pATEInfo->RxAntennaSel; + +#ifdef CONFIG_AP_SUPPORT + NdisMoveMemory(ATEExParam.DA, pATEInfo->Addr1, MAC_ADDR_LEN); + NdisMoveMemory(ATEExParam.SA, pATEInfo->Addr3, MAC_ADDR_LEN); + NdisMoveMemory(ATEExParam.BSSID, pATEInfo->Addr2, MAC_ADDR_LEN); +#endif /* CONFIG_AP_SUPPORT */ + + + ATEExParam.MCS = pATEInfo->TxWI.TxWIMCS; + ATEExParam.PhyMode = pATEInfo->TxWI.TxWIPHYMODE; + ATEExParam.ShortGI = pATEInfo->TxWI.TxWIShortGI; + ATEExParam.BW = pATEInfo->TxWI.TxWIBW; + ATEExParam.Channel = OS_HTONL(pATEInfo->Channel); + ATEExParam.TxLength = OS_HTONL(pATEInfo->TxLength); + ATEExParam.TxCount = OS_HTONL(pATEInfo->TxCount); + ATEExParam.RFFreqOffset = OS_HTONL(pATEInfo->RFFreqOffset); + ATEExParam.IPG = OS_HTONL(pATEInfo->IPG); + ATEExParam.RxTotalCnt = OS_HTONL(pATEInfo->RxTotalCnt); + ATEExParam.RxCntPerSec = OS_HTONL(pATEInfo->RxCntPerSec); + ATEExParam.LastSNR0 = pATEInfo->LastSNR0; + ATEExParam.LastSNR1 = pATEInfo->LastSNR1; +#ifdef DOT11N_SS3_SUPPORT + ATEExParam.LastSNR2 = pATEInfo->LastSNR2; +#endif /* DOT11N_SS3_SUPPORT */ + ATEExParam.LastRssi0 = pATEInfo->LastRssi0; + ATEExParam.LastRssi1 = pATEInfo->LastRssi1; + ATEExParam.LastRssi2 = pATEInfo->LastRssi2; + ATEExParam.AvgRssi0 = pATEInfo->AvgRssi0; + ATEExParam.AvgRssi1 = pATEInfo->AvgRssi1; + ATEExParam.AvgRssi2 = pATEInfo->AvgRssi2; + ATEExParam.AvgRssi0X8 = OS_HTONS(pATEInfo->AvgRssi0X8); + ATEExParam.AvgRssi1X8 = OS_HTONS(pATEInfo->AvgRssi1X8); + ATEExParam.AvgRssi2X8 = OS_HTONS(pATEInfo->AvgRssi2X8); + + Len = sizeof(ATEExParam); + NdisMoveMemory(pRaCfg->data, &ATEExParam, Len); + + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status) + Len, NDIS_STATUS_SUCCESS); + + return Status; +} + + +typedef INT (*RACFG_CMD_HANDLER)( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN struct ate_racfghdr *pRaCfg); + + +static RACFG_CMD_HANDLER RACFG_CMD_SET1[] = +{ + /* cmd id start from 0x0 */ + DO_RACFG_CMD_RF_WRITE_ALL,/* 0x0000 */ + DO_RACFG_CMD_E2PROM_READ16,/* 0x0001 */ + DO_RACFG_CMD_E2PROM_WRITE16,/* 0x0002 */ + DO_RACFG_CMD_E2PROM_READ_ALL,/* 0x0003 */ + DO_RACFG_CMD_E2PROM_WRITE_ALL,/* 0x0004 */ + DO_RACFG_CMD_IO_READ,/* 0x0005 */ + DO_RACFG_CMD_IO_WRITE,/* 0x0006 */ + DO_RACFG_CMD_IO_READ_BULK,/* 0x0007 */ + DO_RACFG_CMD_BBP_READ8,/* 0x0008 */ + DO_RACFG_CMD_BBP_WRITE8,/* 0x0009 */ + DO_RACFG_CMD_BBP_READ_ALL,/* 0x000a */ + DO_RACFG_CMD_GET_COUNTER,/* 0x000b */ + DO_RACFG_CMD_CLEAR_COUNTER,/* 0x000c */ + NULL /* RACFG_CMD_RSV1 */,/* 0x000d */ + NULL /* RACFG_CMD_RSV2 */,/* 0x000e */ + NULL /* RACFG_CMD_RSV3 */,/* 0x000f */ + DO_RACFG_CMD_TX_START,/* 0x0010 */ + DO_RACFG_CMD_GET_TX_STATUS,/* 0x0011 */ + DO_RACFG_CMD_TX_STOP,/* 0x0012 */ + DO_RACFG_CMD_RX_START,/* 0x0013 */ + DO_RACFG_CMD_RX_STOP,/* 0x0014 */ + DO_RACFG_CMD_GET_NOISE_LEVEL,/* 0x0015 */ + NULL + /* cmd id end with 0x20 */ +}; + + +static RACFG_CMD_HANDLER RACFG_CMD_SET2[] = +{ + /* cmd id start from 0x80 */ + DO_RACFG_CMD_ATE_START,/* 0x0080 */ + DO_RACFG_CMD_ATE_STOP/* 0x0081 */ + /* cmd id end with 0x81 */ +}; + + +static RACFG_CMD_HANDLER RACFG_CMD_SET3[] = +{ + /* cmd id start from 0x100 */ + DO_RACFG_CMD_ATE_START_TX_CARRIER,/* 0x0100 */ + DO_RACFG_CMD_ATE_START_TX_CONT,/* 0x0101 */ + DO_RACFG_CMD_ATE_START_TX_FRAME,/* 0x0102 */ + DO_RACFG_CMD_ATE_SET_BW,/* 0x0103 */ + DO_RACFG_CMD_ATE_SET_TX_POWER0,/* 0x0104 */ + DO_RACFG_CMD_ATE_SET_TX_POWER1,/* 0x0105 */ + DO_RACFG_CMD_ATE_SET_FREQ_OFFSET,/* 0x0106 */ + DO_RACFG_CMD_ATE_GET_STATISTICS,/* 0x0107 */ + DO_RACFG_CMD_ATE_RESET_COUNTER,/* 0x0108 */ + DO_RACFG_CMD_ATE_SEL_TX_ANTENNA,/* 0x0109 */ + DO_RACFG_CMD_ATE_SEL_RX_ANTENNA,/* 0x010a */ + DO_RACFG_CMD_ATE_SET_PREAMBLE,/* 0x010b */ + DO_RACFG_CMD_ATE_SET_CHANNEL,/* 0x010c */ + DO_RACFG_CMD_ATE_SET_ADDR1,/* 0x010d */ + DO_RACFG_CMD_ATE_SET_ADDR2,/* 0x010e */ + DO_RACFG_CMD_ATE_SET_ADDR3,/* 0x010f */ + DO_RACFG_CMD_ATE_SET_RATE,/* 0x0110 */ + DO_RACFG_CMD_ATE_SET_TX_FRAME_LEN,/* 0x0111 */ + DO_RACFG_CMD_ATE_SET_TX_FRAME_COUNT,/* 0x0112 */ + DO_RACFG_CMD_ATE_START_RX_FRAME,/* 0x0113 */ + DO_RACFG_CMD_ATE_E2PROM_READ_BULK,/* 0x0114 */ + DO_RACFG_CMD_ATE_E2PROM_WRITE_BULK,/* 0x0115 */ + DO_RACFG_CMD_ATE_IO_WRITE_BULK,/* 0x0116 */ + DO_RACFG_CMD_ATE_BBP_READ_BULK,/* 0x0117 */ + DO_RACFG_CMD_ATE_BBP_WRITE_BULK,/* 0x0118 */ + NULL,/* 0x0119 */ + NULL,/* 0x011a */ +#ifdef DOT11N_SS3_SUPPORT + DO_RACFG_CMD_ATE_SET_TX_POWER2,/* 0x011b */ +#else + NULL,/* 0x011b */ +#endif /* DOT11N_SS3_SUPPORT */ +#ifdef TXBF_SUPPORT + DO_RACFG_CMD_ATE_TXBF_DUT_INIT,/* 0x011c */ + DO_RACFG_CMD_ATE_TXBF_LNA_CAL,/* 0x011d */ + DO_RACFG_CMD_ATE_TXBF_DIV_CAL,/* 0x011e */ + DO_RACFG_CMD_ATE_TXBF_PHASE_CAL,/* 0x011f */ + DO_RACFG_CMD_ATE_TXBF_GOLDEN_INIT,/* 0x0120 */ + DO_RACFG_CMD_ATE_TXBF_VERIFY,/* 0x0121 */ + DO_RACFG_CMD_ATE_TXBF_VERIFY_NOCOMP/* 0x0122 */ +#else + NULL,/* 0x011c */ + NULL,/* 0x011d */ + NULL,/* 0x011e */ + NULL,/* 0x011f */ + NULL,/* 0x0120 */ + NULL,/* 0x0121 */ + NULL/* 0x0122 */ +#endif /* TXBF_SUPPORT */ + /* cmd id end with 0x122 */ +}; + + +static RACFG_CMD_HANDLER RACFG_CMD_SET4[] = +{ + /* cmd id start from 0x200 */ + NULL,/* 0x0200 */ + NULL,/* 0x0201 */ + NULL/* 0x0202 */ + /* cmd id end with 0x202 */ +}; + + +static RACFG_CMD_HANDLER RACFG_CMD_SET5[] = +{ + DO_RACFG_CMD_ATE_SHOW_PARAM +}; + + +typedef struct RACFG_CMD_TABLE_{ + RACFG_CMD_HANDLER *cmdSet; + int cmdSetSize; + int cmdOffset; +}RACFG_CMD_TABLE; + + +RACFG_CMD_TABLE RACFG_CMD_TABLES[]={ + { + RACFG_CMD_SET1, + sizeof(RACFG_CMD_SET1) / sizeof(RACFG_CMD_HANDLER), + 0x0, + }, + { + RACFG_CMD_SET2, + sizeof(RACFG_CMD_SET2) / sizeof(RACFG_CMD_HANDLER), + 0x80, + }, + { + RACFG_CMD_SET3, + sizeof(RACFG_CMD_SET3) / sizeof(RACFG_CMD_HANDLER), + 0x100, + }, + { + RACFG_CMD_SET4, + sizeof(RACFG_CMD_SET4) / sizeof(RACFG_CMD_HANDLER), + 0x200, + }, + { + RACFG_CMD_SET5, + sizeof(RACFG_CMD_SET5) / sizeof(RACFG_CMD_HANDLER), + 0xff00, + } + +}; + + +static INT32 RACfgCMDHandler( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN pRACFGHDR pRaCfg) +{ + PATE_INFO pATEInfo = &(pAd->ate); + INT32 Status = NDIS_STATUS_SUCCESS; + USHORT Command_Id; + UINT32 TableIndex = 0; + + Command_Id = OS_NTOHS(pRaCfg->command_id); + DBGPRINT(RT_DEBUG_TRACE,("\n%s: Command_Id = 0x%04x !\n", __FUNCTION__, Command_Id)); + + while (TableIndex < (sizeof(RACFG_CMD_TABLES) / sizeof(RACFG_CMD_TABLE))) + { + int cmd_index = 0; + cmd_index = Command_Id - RACFG_CMD_TABLES[TableIndex].cmdOffset; + if ((cmd_index >= 0) && (cmd_index < RACFG_CMD_TABLES[TableIndex].cmdSetSize)) + { + RACFG_CMD_HANDLER *pCmdSet; + + pCmdSet = RACFG_CMD_TABLES[TableIndex].cmdSet; + + if (pCmdSet[cmd_index] != NULL) + Status = (*pCmdSet[cmd_index])(pAd, wrq, pRaCfg); + break; + } + TableIndex++; + } + + /* In passive mode, only commands that read registers are allowed. */ + if (pATEInfo->PassiveMode) + { + int entry, allowCmd = FALSE; + static int allowedCmds[] = { + RACFG_CMD_E2PROM_READ16, RACFG_CMD_E2PROM_READ_ALL, + RACFG_CMD_IO_READ, RACFG_CMD_IO_READ_BULK, + RACFG_CMD_BBP_READ8, RACFG_CMD_BBP_READ_ALL, + RACFG_CMD_ATE_E2PROM_READ_BULK, + RACFG_CMD_ATE_BBP_READ_BULK, + RACFG_CMD_ATE_RF_READ_BULK, + }; + + for (entry=0; entrystatus); + if (offset==BBP_R27 || (offset>=BBP_R174 && offset<=BBP_R182)) + allowCmd = TRUE; + } + + /* If not allowed, then ignore the command. */ + if (!allowCmd) + { + ResponseToGUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS); + Status = NDIS_STATUS_FAILURE; + } + } + + return Status; +} + + +INT RtmpDoAte( + IN PRTMP_ADAPTER pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN PSTRING wrq_name) +{ + INT32 Status = NDIS_STATUS_SUCCESS; + struct ate_racfghdr *pRaCfg; + UINT32 ATEMagicNum; + + os_alloc_mem_suspend(pAd, (UCHAR **)&pRaCfg, sizeof(struct ate_racfghdr)); + + if (!pRaCfg) + { + Status = -ENOMEM; + goto ERROR0; + } + + NdisZeroMemory(pRaCfg, sizeof(struct ate_racfghdr)); + Status = copy_from_user((PUCHAR)pRaCfg, wrq->u.data.pointer, wrq->u.data.length); + + if (Status) + { + Status = -EFAULT; + goto ERROR1; + } + + ATEMagicNum = OS_NTOHL(pRaCfg->magic_no); + + switch(ATEMagicNum) + { + case RACFG_MAGIC_NO: + Status = RACfgCMDHandler(pAd, wrq, pRaCfg); + break; + + default: + Status = NDIS_STATUS_FAILURE; + DBGPRINT_ERR(("Unknown magic number of RACFG command = %x\n", ATEMagicNum)); + break; + } + + ERROR1: + os_free_mem(NULL, pRaCfg); + ERROR0: + return Status; +} + + +VOID ATE_QA_Statistics( + IN RTMP_ADAPTER *pAd, + IN RXWI_STRUC *pRxWI, + IN RXINFO_STRUC *pRxInfo, + IN PHEADER_802_11 pHeader) +{ + PATE_INFO pATEInfo = &(pAd->ate); + + /* update counter first */ + if (pHeader != NULL) + { + if (pHeader->FC.Type == BTYPE_DATA) + { + if (pRxInfo->U2M) + { + pATEInfo->U2M++; + } + else + pATEInfo->OtherData++; + } + else if (pHeader->FC.Type == BTYPE_MGMT) + { + if (pHeader->FC.SubType == SUBTYPE_BEACON) + pATEInfo->Beacon++; + else + pATEInfo->OtherCount++; + } + else if (pHeader->FC.Type == BTYPE_CNTL) + { + pATEInfo->OtherCount++; + } + } + pATEInfo->RSSI0 = pRxWI->RxWIRSSI0; + pATEInfo->RSSI1 = pRxWI->RxWIRSSI1; + pATEInfo->RSSI2 = pRxWI->RxWIRSSI2; + pATEInfo->SNR0 = pRxWI->RxWISNR0; + pATEInfo->SNR1 = pRxWI->RxWISNR1; + + +} + + +INT Set_TxStop_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + DBGPRINT(RT_DEBUG_TRACE,("Set_TxStop_Proc\n")); + + if (Set_ATE_Proc(pAd, "TXSTOP")) + { + return TRUE; + } + else + { + return FALSE; + } +} + + +INT Set_RxStop_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + DBGPRINT(RT_DEBUG_TRACE,("Set_RxStop_Proc\n")); + + if (Set_ATE_Proc(pAd, "RXSTOP")) + { + return TRUE; + } + else + { + return FALSE; + } +} + + +#ifdef DBG +INT Set_EERead_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + USHORT buffer[EEPROM_SIZE >> 1]; + USHORT *p; + INT offset; + + rt_ee_read_all(pAd, (USHORT *)buffer); + p = buffer; + + for (offset = 0; offset < (EEPROM_SIZE >> 1); offset++) + { + DBGPRINT(RT_DEBUG_OFF, ("%4.4x ", *p)); + if (((offset+1) % 16) == 0) + DBGPRINT(RT_DEBUG_OFF, ("\n")); + p++; + } + + return TRUE; +} + + +INT Set_EEWrite_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + USHORT offset = 0, value; + PSTRING p2 = arg; + + while ((*p2 != ':') && (*p2 != '\0')) + { + p2++; + } + + if (*p2 == ':') + { + A2Hex(offset, arg); + A2Hex(value, p2 + 1); + } + else + { + A2Hex(value, arg); + } + + if (offset >= EEPROM_SIZE) + { + DBGPRINT_ERR(("Offset can not exceed EEPROM_SIZE( == 0x%04x)\n", EEPROM_SIZE)); + return FALSE; + } + + RT28xx_EEPROM_WRITE16(pAd, offset, value); + + return TRUE; +} + + +INT Set_BBPRead_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + UCHAR value = 0, offset; + + A2Hex(offset, arg); + + ATE_BBPRead(pAd, offset, &value); + + DBGPRINT(RT_DEBUG_OFF, ("%x\n", value)); + + return TRUE; +} + + +INT Set_BBPWrite_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + USHORT offset = 0; + PSTRING p2 = arg; + UCHAR value; + + while ((*p2 != ':') && (*p2 != '\0')) + { + p2++; + } + + if (*p2 == ':') + { + A2Hex(offset, arg); + A2Hex(value, p2 + 1); + } + else + { + A2Hex(value, arg); + } + + ATE_BBPWrite(pAd, offset, value); + + return TRUE; +} + + +INT Set_RFWrite_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg) +{ + PSTRING p2, p3, p4; + UINT32 R1, R2, R3, R4; + + p2 = arg; + + while ((*p2 != ':') && (*p2 != '\0')) + { + p2++; + } + + if (*p2 != ':') + return FALSE; + + p3 = p2 + 1; + + while((*p3 != ':') && (*p3 != '\0')) + { + p3++; + } + + if (*p3 != ':') + return FALSE; + + p4 = p3 + 1; + + while ((*p4 != ':') && (*p4 != '\0')) + { + p4++; + } + + if (*p4 != ':') + return FALSE; + + + A2Hex(R1, arg); + A2Hex(R2, p2 + 1); + A2Hex(R3, p3 + 1); + A2Hex(R4, p4 + 1); + + RTMP_RF_IO_WRITE32(pAd, R1); + RTMP_RF_IO_WRITE32(pAd, R2); + RTMP_RF_IO_WRITE32(pAd, R3); + RTMP_RF_IO_WRITE32(pAd, R4); + + return TRUE; +} +#endif /* DBG */ +#endif /* RALINK_QA */ + diff --git a/cleopatre/devkit/mt7601udrv/ate/include/rt_ate.h b/cleopatre/devkit/mt7601udrv/ate/include/rt_ate.h new file mode 100644 index 0000000000..06e87392bf --- /dev/null +++ b/cleopatre/devkit/mt7601udrv/ate/include/rt_ate.h @@ -0,0 +1,808 @@ +/* + *************************************************************************** + * Ralink Tech Inc. + * 4F, No. 2 Technology 5th Rd. + * Science-based Industrial Park + * Hsin-chu, Taiwan, R.O.C. + * + * (c) Copyright 2002-2010, Ralink Technology, Inc. + * + * All rights reserved. Ralink's source code is an unpublished work and the + * use of a copyright notice does not imply otherwise. This source code + * contains confidential trade secret material of Ralink Tech. Any attemp + * or participation in deciphering, decoding, reverse engineering or in any + * way altering the source code is stricitly prohibited, unless the prior + * written consent of Ralink Technology, Inc. is obtained. + *************************************************************************** + + Module Name: + rt_ate.h + + Abstract: + + Revision History: + Who When What + -------- ---------- ---------------------------------------------- + Name Date Modification logs +*/ + +#ifndef __RT_ATE_H__ +#define __RT_ATE_H__ + +typedef struct _ATE_CHIP_STRUCT { + /* functions */ + VOID (*ChannelSwitch)(PRTMP_ADAPTER pAd); + INT (*TxPwrHandler)(PRTMP_ADAPTER pAd, char index); + INT (*TssiCalibration)(PRTMP_ADAPTER pAd, PSTRING arg); + INT (*ExtendedTssiCalibration)(PRTMP_ADAPTER pAd, PSTRING arg); + VOID (*RxVGAInit)(PRTMP_ADAPTER pAd); + VOID (*AsicSetTxRxPath)(PRTMP_ADAPTER pAd); + VOID (*AdjustTxPower)(PRTMP_ADAPTER pAd); + VOID (*AsicExtraPowerOverMAC)(PRTMP_ADAPTER pAd); + VOID (*TemperCompensation)(PRTMP_ADAPTER *pAd); + + /* command handlers */ + INT (*Set_BW_Proc)(PRTMP_ADAPTER pAd, PSTRING arg); + INT (*Set_FREQ_OFFSET_Proc)(PRTMP_ADAPTER pAd, PSTRING arg); + + /* variables */ + INT maxTxPwrCnt; + BOOLEAN bBBPStoreTXCARR; + BOOLEAN bBBPStoreTXCARRSUPP; + BOOLEAN bBBPStoreTXCONT; + BOOLEAN bBBPLoadATESTOP; + +}ATE_CHIP_STRUCT, *PATE_CHIP_STRUCT; + +typedef union _CAPTURE_MODE_SHARE_MEMORY { + struct + { + UINT32 LOW_BYTE0:8; + UINT32 LOW_BYTE1:8; + UINT32 HIGH_BYTE0:8; + UINT32 HIGH_BYTE1:8; + } field; + UINT32 Value; +}CAPTURE_MODE_SHARE_MEMORY, *PCAPTURE_MODE_SHARE_MEMORY; + +typedef struct _ATE_INFO { + PATE_CHIP_STRUCT pChipStruct; + UCHAR Mode; + BOOLEAN PassiveMode; +#ifdef RT3350 + UCHAR PABias; +#endif /* RT3350 */ + CHAR TxPower0; + CHAR TxPower1; +#ifdef DOT11N_SS3_SUPPORT + CHAR TxPower2; +#endif /* DOT11N_SS3_SUPPORT */ + CHAR MinTxPowerBandA; /* Power range of early chipsets is -7~15 in A band */ + CHAR MaxTxPowerBandA; /* Power range of early chipsets is -7~15 in A band */ + CHAR TxAntennaSel; + CHAR RxAntennaSel; + TXWI_STRUC TxWI; /* TXWI */ + USHORT QID; + UCHAR Addr1[MAC_ADDR_LEN]; + UCHAR Addr2[MAC_ADDR_LEN]; + UCHAR Addr3[MAC_ADDR_LEN]; + UCHAR Channel; + UCHAR Payload; /* Payload pattern */ + UCHAR TxMethod; /* Early chipsets must be applied old TXCONT/TXCARR/TXCARS mechanism. */ + UINT32 TxLength; + UINT32 TxCount; + UINT32 TxDoneCount; /* Tx DMA Done */ + UINT32 RFFreqOffset; + UINT32 IPG; + BOOLEAN bRxFER; /* Show Rx Frame Error Rate */ + BOOLEAN bQAEnabled; /* QA is used. */ + BOOLEAN bQATxStart; /* Have compiled QA in and use it to ATE tx. */ + BOOLEAN bQARxStart; /* Have compiled QA in and use it to ATE rx. */ + BOOLEAN bAutoTxAlc; /* Set Auto Tx Alc */ +#ifdef RTMP_INTERNAL_TX_ALC +#if defined(RT3350) || defined(RT3352) + BOOLEAN bTSSICalbrEnableG; /* Enable TSSI calibration */ + CHAR TssiRefPerChannel[CFG80211_NUM_OF_CHAN_2GHZ]; + CHAR TssiDeltaPerChannel[CFG80211_NUM_OF_CHAN_2GHZ]; +#endif /* defined(RT3350) || defined(RT3352) */ +#endif /* RTMP_INTERNAL_TX_ALC */ +#ifdef TXBF_SUPPORT + BOOLEAN bTxBF; /* Enable Tx Bean Forming */ + SHORT txSoundingMode; /* Sounding mode for non-QA ATE. 0=none, 1=Data Sounding, 2=NDP */ + UCHAR calParams[2]; +#endif /* TXBF_SUPPORT */ + UINT32 RxTotalCnt; + UINT32 RxCntPerSec; + UCHAR forceBBPReg; /* force to not update the specific BBP register, now used for ATE TxBF */ + + CHAR LastSNR0; /* last received SNR */ + CHAR LastSNR1; /* last received SNR for 2nd antenna */ +#ifdef DOT11N_SS3_SUPPORT + CHAR LastSNR2; +#endif /* DOT11N_SS3_SUPPORT */ + CHAR LastRssi0; /* last received RSSI */ + CHAR LastRssi1; /* last received RSSI for 2nd antenna */ + CHAR LastRssi2; /* last received RSSI for 3rd antenna */ + CHAR AvgRssi0; /* last 8 frames' average RSSI */ + CHAR AvgRssi1; /* last 8 frames' average RSSI */ + CHAR AvgRssi2; /* last 8 frames' average RSSI */ + SHORT AvgRssi0X8; /* sum of last 8 frames' RSSI */ + SHORT AvgRssi1X8; /* sum of last 8 frames' RSSI */ + SHORT AvgRssi2X8; /* sum of last 8 frames' RSSI */ + UINT32 NumOfAvgRssiSample; + USHORT HLen; /* Header Length */ + +#ifdef RALINK_QA + /* Tx frame */ +#ifdef RTMP_MAC_USB + TXINFO_STRUC TxInfo; /* TxInfo */ +#endif /* RTMP_MAC_USB */ + USHORT PLen; /* Pattern Length */ + UCHAR Header[32]; /* Header buffer */ + UCHAR Pattern[32]; /* Pattern buffer */ + USHORT DLen; /* Data Length */ + USHORT seq; + UINT32 CID; + RTMP_OS_PID AtePid; + /* counters */ + UINT32 U2M; + UINT32 OtherData; + UINT32 Beacon; + UINT32 OtherCount; + UINT32 TxAc0; + UINT32 TxAc1; + UINT32 TxAc2; + UINT32 TxAc3; + UINT32 TxHCCA; + UINT32 TxMgmt; + UINT32 RSSI0; + UINT32 RSSI1; + UINT32 RSSI2; + UINT32 SNR0; + UINT32 SNR1; +#ifdef DOT11N_SS3_SUPPORT + UINT32 SNR2; +#endif /* DOT11N_SS3_SUPPORT */ + INT32 BF_SNR[3]; /* Last RXWI BF SNR. Units=0.25 dB */ + /* TxStatus : 0 --> task is idle, 1 --> task is running */ + UCHAR TxStatus; +#endif /* RALINK_QA */ +#ifdef TXBF_SUPPORT +#define MAX_SOUNDING_RESPONSE_SIZE (57*2*2*9+3+2+6) /* Assume 114 carriers (40MHz), 3x3, 8bits/coeff, + SNR + HT HEADER + MIMO CONTROL FIELD */ + UCHAR sounding; + UINT32 sounding_jiffies; + CHAR soundingSNR[3]; + UINT32 LastRxRate; + UINT32 LastTxRate; + UINT32 soundingRespSize; /* Size of Sounding response */ + UCHAR soundingResp[MAX_SOUNDING_RESPONSE_SIZE]; /* Entire Sounding response */ +#endif /* TXBF_SUPPORT */ + RALINK_TIMER_STRUCT PeriodicTimer; + ULONG OneSecPeriodicRound; +} ATE_INFO, *PATE_INFO; + +/* + Use bitmap to allow coexist of ATE_TXFRAME + and ATE_RXFRAME(i.e.,to support LoopBack mode). +*/ +#define fATE_IDLE 0x00 +#define fATE_TX_ENABLE 0x01 +#define fATE_RX_ENABLE 0x02 +#define fATE_TXCONT_ENABLE 0x04 +#define fATE_TXCARR_ENABLE 0x08 +#define fATE_TXCARRSUPP_ENABLE 0x10 +#define fATE_RESERVED_1 0x20 +#define fATE_RESERVED_2 0x40 +#define fATE_EXIT 0x80 + +/* Enter/Reset ATE */ +#define ATE_START (fATE_IDLE) +/* Stop/Exit ATE */ +#define ATE_STOP (fATE_EXIT) +/* Continuous Transmit Frames (without time gap) */ +#define ATE_TXCONT ((fATE_TX_ENABLE)|(fATE_TXCONT_ENABLE)) +/* Transmit Carrier */ +#define ATE_TXCARR ((fATE_TX_ENABLE)|(fATE_TXCARR_ENABLE)) +/* Transmit Carrier Suppression (information without carrier) */ +#define ATE_TXCARRSUPP ((fATE_TX_ENABLE)|(fATE_TXCARRSUPP_ENABLE)) +/* Transmit Frames */ +#define ATE_TXFRAME (fATE_TX_ENABLE) +/* Receive Frames */ +#define ATE_RXFRAME (fATE_RX_ENABLE) + + +#ifdef RTMP_INTERNAL_TX_ALC +#define EEPROM_TSSI_ENABLE 0x36 +#define EEPROM_TSSI_MODE_EXTEND 0x76 + +#define ATE_MDSM_NORMAL_TX_POWER 0x00 +#define ATE_MDSM_DROP_TX_POWER_BY_6dBm 0x01 +#define ATE_MDSM_DROP_TX_POWER_BY_12dBm 0x02 +#define ATE_MDSM_ADD_TX_POWER_BY_6dBm 0x03 +#define ATE_MDSM_BBP_R1_STATIC_TX_POWER_CONTROL_MASK 0x03 +#endif /* RTMP_INTERNAL_TX_ALC */ + +#define LEN_OF_ARG 16 +#define ATE_ON(_p) (((_p)->ate.Mode) != ATE_STOP) +#define TX_METHOD_0 0 /* Early chipsets must be applied this original TXCONT/TXCARR/TXCARS mechanism. */ +#define TX_METHOD_1 1 /* Default TXCONT/TXCARR/TXCARS mechanism is TX_METHOD_1 */ + +#define ATE_MAC_TX_ENABLE(_A, _I, _pV) \ +{ \ + RTMP_IO_READ32(_A, _I, _pV); \ + (*(_pV)) |= (1 << 2); \ + RTMP_IO_WRITE32(_A, _I, (*(_pV))); \ +} + +#define ATE_MAC_TX_DISABLE(_A, _I, _pV) \ +{ \ + RTMP_IO_READ32(_A, _I, _pV); \ + (*(_pV)) &= ~(1 << 2); \ + RTMP_IO_WRITE32(_A, _I, (*(_pV))); \ +} + +#define ATE_MAC_RX_ENABLE(_A, _I, _pV) \ +{ \ + RTMP_IO_READ32(_A, _I, _pV); \ + (*(_pV)) |= (1 << 3); \ + RTMP_IO_WRITE32(_A, _I, (*(_pV))); \ +} + +#define ATE_MAC_RX_DISABLE(_A, _I, _pV) \ +{ \ + RTMP_IO_READ32(_A, _I, _pV); \ + (*(_pV)) &= ~(1 << 3); \ + RTMP_IO_WRITE32(_A, _I, (*(_pV))); \ +} + +/* Set MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 1. */ +#define ATE_MAC_TX_CTS_ENABLE(_A, _I, _pV) \ +{ \ + RTMP_IO_READ32(_A, _I, _pV); \ + (*(_pV)) |= (1 << 4); \ + RTMP_IO_WRITE32(_A, _I, (*(_pV))); \ +} + +/* Clear MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 0. */ +#define ATE_MAC_TX_CTS_DISABLE(_A, _I, _pV) \ +{ \ + RTMP_IO_READ32(_A, _I, _pV); \ + (*(_pV)) &= ~(1 << 4); \ + RTMP_IO_WRITE32(_A, _I, (*(_pV))); \ +} + +/* Clear BBP R22 to reset Tx Mode (bit7~bit0) = 0. */ +#define ATE_BBP_RESET_TX_MODE(_A, _I, _pV) \ +{ \ + ATE_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV); \ + (*(_pV)) &= (0x00); \ + ATE_BBP_IO_WRITE8_BY_REG_ID(_A, _I, (*(_pV))); \ +} + +/* Set BBP R22 to start Continuous Tx Mode (bit7) = 1. */ +#define ATE_BBP_START_CTS_TX_MODE(_A, _I, _pV) \ +{ \ + ATE_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV); \ + (*(_pV)) |= (1 << 7); \ + ATE_BBP_IO_WRITE8_BY_REG_ID(_A, _I, (*(_pV))); \ +} + +/* Clear BBP R22 to stop Continuous Tx Mode (bit7) = 0. */ +#define ATE_BBP_STOP_CTS_TX_MODE(_A, _I, _pV) \ +{ \ + ATE_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV); \ + (*(_pV)) &= ~(1 << 7); \ + ATE_BBP_IO_WRITE8_BY_REG_ID(_A, _I, (*(_pV))); \ +} + +/* Set BBP R24 to send out Continuous Tx sin wave (bit0) = 1. */ +#define ATE_BBP_CTS_TX_SIN_WAVE_ENABLE(_A, _I, _pV) \ +{ \ + ATE_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV); \ + (*(_pV)) |= (1 << 0); \ + ATE_BBP_IO_WRITE8_BY_REG_ID(_A, _I, (*(_pV))); \ +} + +/* Clear BBP R24 to stop Continuous Tx sin wave (bit0) = 0. */ +#define ATE_BBP_CTS_TX_SIN_WAVE_DISABLE(_A, _I, _pV) \ +{ \ + ATE_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV); \ + (*(_pV)) &= ~(1 << 0); \ + ATE_BBP_IO_WRITE8_BY_REG_ID(_A, _I, (*(_pV))); \ +} + +/* +========================================================================== + Description: + This routine sets initial value of VGA in the RX chain. + AGC is the abbreviation of "Automatic Gain Controller", + while VGA (Variable Gain Amplifier) is a part of AGC loop. + (i.e., VGA + level detector + feedback loop = AGC) + + Return: + VOID +========================================================================== +*/ +#define ATE_CHIP_RX_VGA_GAIN_INIT(__pAd) \ + if (__pAd->ate.pChipStruct->RxVGAInit != NULL) \ + __pAd->ate.pChipStruct->RxVGAInit(__pAd) + +#define ATE_CHIP_SET_TX_RX_PATH(__pAd) \ + if (__pAd->ate.pChipStruct->AsicSetTxRxPath != NULL) \ + __pAd->ate.pChipStruct->AsicSetTxRxPath(__pAd) + + + +#ifdef RTMP_MAC_USB +#define ATE_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) +#define ATE_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) + +#define BULK_OUT_LOCK(pLock, IrqFlags) \ + if(1 /*!(in_interrupt() & 0xffff0000)*/) \ + RTMP_IRQ_LOCK((pLock), IrqFlags); + +#define BULK_OUT_UNLOCK(pLock, IrqFlags) \ + if(1 /*!(in_interrupt() & 0xffff0000)*/) \ + RTMP_IRQ_UNLOCK((pLock), IrqFlags); + +VOID ATE_RTUSBBulkOutDataPacket( + IN PRTMP_ADAPTER pAd, + IN UCHAR BulkOutPipeId); + +VOID ATE_RTUSBCancelPendingBulkInIRP( + IN PRTMP_ADAPTER pAd); + +VOID ATEResetBulkIn( + IN PRTMP_ADAPTER pAd); + +INT ATEResetBulkOut( + IN PRTMP_ADAPTER pAd); +#endif /* RTMP_MAC_USB */ + +INT DefaultATETxPwrHandler( + IN PRTMP_ADAPTER pAd, + IN char index); + + + + + +#if defined(RT28xx) || defined(RT2880) +VOID RT28xxATEAsicSwitchChannel( + IN PRTMP_ADAPTER pAd); + +INT RT28xxATETxPwrHandler( + IN PRTMP_ADAPTER pAd, + IN char index); +#endif /* defined(RT28xx) || defined(RT2880) */ + + +#ifdef RALINK_QA +VOID ATE_QA_Statistics( + IN RTMP_ADAPTER *pAd, + IN RXWI_STRUC *pRxWI, + IN RXINFO_STRUC *pRxInfo, + IN PHEADER_802_11 pHeader); + +INT RtmpDoAte( + IN RTMP_ADAPTER *pAd, + IN RTMP_IOCTL_INPUT_STRUCT *wrq, + IN PSTRING wrq_name); + +INT Set_TxStop_Proc( + IN RTMP_ADAPTER *pAd, + IN PSTRING arg); + +INT Set_RxStop_Proc( + IN RTMP_ADAPTER *pAd, + IN PSTRING arg); + +#ifdef DBG +INT Set_EERead_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_EEWrite_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_BBPRead_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_BBPWrite_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_RFWrite_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* DBG */ +#endif /* RALINK_QA */ + + + +#ifdef RALINK_QA +#define SYNC_CHANNEL_WITH_QA(_A, _pV)\ + if ((_A->bQATxStart == TRUE) || (_A->bQARxStart == TRUE))\ + {\ + return;\ + }\ + else\ + *_pV = _A->Channel +#else +#define SYNC_CHANNEL_WITH_QA(_A, _pV)\ + *_pV = _A->Channel +#endif /* RALINK_QA */ + +VOID rt_ee_read_all( + IN PRTMP_ADAPTER pAd, + OUT USHORT *Data); + +VOID rt_ee_write_all( + IN PRTMP_ADAPTER pAd, + IN USHORT *Data); + +VOID rt_ee_write_bulk( + IN PRTMP_ADAPTER pAd, + IN USHORT *Data, + IN USHORT offset, + IN USHORT length); + +INT Set_ATE_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_DA_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_SA_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_BSSID_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + + +INT Set_ATE_CHANNEL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_INIT_CHAN_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ADCDump_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#ifdef RTMP_INTERNAL_TX_ALC +INT Set_ATE_TSSI_CALIBRATION_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TSSI_CALIBRATION_EX_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + + +#if defined(RT3350) || defined(RT3352) +INT RT335x_Set_ATE_TSSI_CALIBRATION_ENABLE_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +CHAR InsertTssi( + IN UCHAR InChannel, + IN UCHAR Channel0, + IN UCHAR Channel1, + IN CHAR Tssi0, + IN CHAR Tssi1); + +INT RT335xATETssiCalibrationExtend( + IN struct _RTMP_ADAPTER *pAd, + IN PSTRING arg); +#endif /* defined(RT3350) || defined(RT3352) */ + +CHAR ATEGetDesiredTSSI( + IN PRTMP_ADAPTER pAd); + +#endif /* RTMP_INTERNAL_TX_ALC */ + +#ifdef RTMP_TEMPERATURE_COMPENSATION + +INT Set_ATE_READ_EXTERNAL_TSSI_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* RTMP_TEMPERATURE_COMPENSATION */ + +INT Set_ATE_TX_POWER0_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TX_POWER1_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +#ifdef DOT11N_SS3_SUPPORT +INT Set_ATE_TX_POWER2_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* DOT11N_SS3_SUPPORT */ + +INT Set_ATE_TX_Antenna_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_RX_Antenna_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +VOID DefaultATEAsicExtraPowerOverMAC( + IN PRTMP_ADAPTER pAd); + +VOID ATEAsicExtraPowerOverMAC( + IN PRTMP_ADAPTER pAd); +#ifdef RT3350 +INT Set_ATE_PA_Bias_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* RT3350 */ + +INT Default_Set_ATE_TX_FREQ_OFFSET_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + + + + + +#if defined(RT28xx) || defined(RT2880) +INT RT28xx_Set_ATE_TX_FREQ_OFFSET_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* defined(RT28xx) || defined(RT2880) */ + + +INT Set_ATE_TX_FREQ_OFFSET_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Default_Set_ATE_TX_BW_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + + + + + +#if defined(RT28xx) || defined(RT2880) +INT RT28xx_Set_ATE_TX_BW_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* defined(RT28xx) || defined(RT2880) */ + + +INT Set_ATE_TX_BW_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TX_LENGTH_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TX_COUNT_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TX_MCS_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TX_MODE_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TX_GI_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + + +INT Set_ATE_RX_FER_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Read_RF_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Write_RF1_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Write_RF2_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Write_RF3_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Write_RF4_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Load_E2P_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +#ifdef RTMP_EFUSE_SUPPORT +INT Set_ATE_Load_E2P_From_Buf_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Cal_Free_Info_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* RTMP_EFUSE_SUPPORT */ + +INT Set_ATE_Read_E2P_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +#ifdef LED_CONTROL_SUPPORT +#endif /* LED_CONTROL_SUPPORT */ + +INT Set_ATE_AUTO_ALC_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_IPG_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Payload_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +#ifdef TXBF_SUPPORT +INT Set_ATE_TXBF_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXSOUNDING_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXBF_DIVCAL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXBF_LNACAL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXBF_INIT_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXBF_CAL_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXBF_GOLDEN_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXBF_VERIFY_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_TXBF_VERIFY_NoComp_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_ForceBBP_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* TXBF_SUPPORT */ + + +INT Set_ATE_Show_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Help_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +VOID DefaultATEAsicAdjustTxPower( + IN PRTMP_ADAPTER pAd); + + +#ifdef MT7601 +INT Set_ATE_Read_Temperature_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); + +INT Set_ATE_Read_TSSI_DC_Proc( + IN PRTMP_ADAPTER pAd, + IN PSTRING arg); +#endif /* MT7601 */ + +VOID ATEAsicAdjustTxPower( + IN PRTMP_ADAPTER pAd); + +VOID ATESampleRssi( + IN PRTMP_ADAPTER pAd, + IN RXWI_STRUC *pRxWI); + + +#ifdef RTMP_MAC_USB +INT TxDmaBusy( + IN PRTMP_ADAPTER pAd); + +INT RxDmaBusy( + IN PRTMP_ADAPTER pAd); + +VOID RtmpDmaEnable( + IN PRTMP_ADAPTER pAd, + IN INT Enable); + +INT ATESetUpFrame( + IN PRTMP_ADAPTER pAd, + IN UINT32 TxIdx); + +VOID RTUSBRejectPendingPackets( + IN PRTMP_ADAPTER pAd); +#endif /* RTMP_MAC_USB */ + + +NDIS_STATUS ChipStructAssign( + IN PRTMP_ADAPTER pAd); + +NDIS_STATUS ATEInit( + IN PRTMP_ADAPTER pAd); + +#ifdef RALINK_QA +VOID ReadQATxTypeFromBBP( + IN PRTMP_ADAPTER pAd); +#endif /* RALINK_QA */ + +NDIS_STATUS ATEBBPWriteWithRxChain( + IN RTMP_ADAPTER *pAd, + IN UCHAR bbpId, + IN CHAR bbpVal, + IN RX_CHAIN_IDX rx_ch_idx); + + + + + + +#if defined(RT28xx) || defined(RT2880) +VOID RT28xxATERxVGAInit( + IN PRTMP_ADAPTER pAd); +#endif /* defined(RT28xx) || defined(RT2880) */ + + +VOID ATEPeriodicExec( + IN PVOID SystemSpecific1, + IN PVOID FunctionContext, + IN PVOID SystemSpecific2, + IN PVOID SystemSpecific3); + +VOID ATEAsicSetTxRxPath( + IN PRTMP_ADAPTER pAd); + +VOID RtmpRfIoWrite( + IN PRTMP_ADAPTER pAd); + +VOID ATEAsicSwitchChannel( + IN PRTMP_ADAPTER pAd); + +VOID BbpSoftReset( + IN PRTMP_ADAPTER pAd); + +#endif /* __RT_ATE_H__ */ + diff --git a/cleopatre/devkit/mt7601udrv/ate/include/rt_qa.h b/cleopatre/devkit/mt7601udrv/ate/include/rt_qa.h new file mode 100644 index 0000000000..801bcbae7f --- /dev/null +++ b/cleopatre/devkit/mt7601udrv/ate/include/rt_qa.h @@ -0,0 +1,181 @@ +/* + *************************************************************************** + * Ralink Tech Inc. + * 4F, No. 2 Technology 5th Rd. + * Science-based Industrial Park + * Hsin-chu, Taiwan, R.O.C. + * + * (c) Copyright 2002-2010, Ralink Technology, Inc. + * + * All rights reserved. Ralink's source code is an unpublished work and the + * use of a copyright notice does not imply otherwise. This source code + * contains confidential trade secret material of Ralink Tech. Any attemp + * or participation in deciphering, decoding, reverse engineering or in any + * way altering the source code is stricitly prohibited, unless the prior + * written consent of Ralink Technology, Inc. is obtained. + *************************************************************************** + + Module Name: + rt_qa.h + + Abstract: + + Revision History: + Who When What + -------- ---------- ---------------------------------------------- + Name Date Modification logs +*/ + +#ifndef __RT_QA_H__ +#define __RT_QA_H__ + +#ifdef RALINK_QA +#ifndef RALINK_ATE +#error "For supporting QA GUI, please set HAS_ATE=y and HAS_QA_SUPPORT=y." +#endif /* RALINK_ATE */ + +#include "rt_ate.h" + +typedef struct ate_racfghdr { + UINT32 magic_no; + USHORT command_type; + USHORT command_id; + USHORT length; + USHORT sequence; + USHORT status; + UCHAR data[2046]; +} __attribute__((packed))RACFGHDR, *pRACFGHDR; + +/* Stop Transmission */ +#define ATE_TXSTOP ((~(fATE_TX_ENABLE))&(~(fATE_TXCONT_ENABLE))&(~(fATE_TXCARR_ENABLE))&(~(fATE_TXCARRSUPP_ENABLE))) +/* Stop Receiving Frames */ +#define ATE_RXSTOP (~(fATE_RX_ENABLE)) + +/* NOTE : may be different with chipset in the future ++ */ +#define BBP22_TXFRAME 0x00 /* Transmit Frames */ +#define BBP22_TXCONT_OR_CARRSUPP 0x80 /* Continuous Transmit or Carrier Suppression */ +#define BBP22_TXCARR 0xc1 /* Transmit Carrier */ +#define BBP24_TXCONT 0x00 /* Continuous Transmit */ +#define BBP24_CARRSUPP 0x01 /* Carrier Suppression */ +/* NOTE : may be different with chipset in the future -- */ + +/* Eth QA RACFG Command */ +#define RACFG_MAGIC_NO 0x18142880 +/* command id with Cmd Type == 0x0005(for iNIC)/0x0008(for others) */ +#define RACFG_CMD_RF_WRITE_ALL 0x0000 +#define RACFG_CMD_E2PROM_READ16 0x0001 +#define RACFG_CMD_E2PROM_WRITE16 0x0002 +#define RACFG_CMD_E2PROM_READ_ALL 0x0003 +#define RACFG_CMD_E2PROM_WRITE_ALL 0x0004 +#define RACFG_CMD_IO_READ 0x0005 +#define RACFG_CMD_IO_WRITE 0x0006 +#define RACFG_CMD_IO_READ_BULK 0x0007 +#define RACFG_CMD_BBP_READ8 0x0008 +#define RACFG_CMD_BBP_WRITE8 0x0009 +#define RACFG_CMD_BBP_READ_ALL 0x000a +#define RACFG_CMD_GET_COUNTER 0x000b +#define RACFG_CMD_CLEAR_COUNTER 0x000c + +#define RACFG_CMD_RSV1 0x000d +#define RACFG_CMD_RSV2 0x000e +#define RACFG_CMD_RSV3 0x000f + +#define RACFG_CMD_TX_START 0x0010 +#define RACFG_CMD_GET_TX_STATUS 0x0011 +#define RACFG_CMD_TX_STOP 0x0012 +#define RACFG_CMD_RX_START 0x0013 +#define RACFG_CMD_RX_STOP 0x0014 +#define RACFG_CMD_GET_NOISE_LEVEL 0x0015 + +#define RACFG_CMD_ATE_START 0x0080 +#define RACFG_CMD_ATE_STOP 0x0081 + +#define RACFG_CMD_ATE_START_TX_CARRIER 0x0100 +#define RACFG_CMD_ATE_START_TX_CONT 0x0101 +#define RACFG_CMD_ATE_START_TX_FRAME 0x0102 +#define RACFG_CMD_ATE_SET_BW 0x0103 +#define RACFG_CMD_ATE_SET_TX_POWER0 0x0104 +#define RACFG_CMD_ATE_SET_TX_POWER1 0x0105 +#define RACFG_CMD_ATE_SET_FREQ_OFFSET 0x0106 +#define RACFG_CMD_ATE_GET_STATISTICS 0x0107 +#define RACFG_CMD_ATE_RESET_COUNTER 0x0108 +#define RACFG_CMD_ATE_SEL_TX_ANTENNA 0x0109 +#define RACFG_CMD_ATE_SEL_RX_ANTENNA 0x010a +#define RACFG_CMD_ATE_SET_PREAMBLE 0x010b +#define RACFG_CMD_ATE_SET_CHANNEL 0x010c +#define RACFG_CMD_ATE_SET_ADDR1 0x010d +#define RACFG_CMD_ATE_SET_ADDR2 0x010e +#define RACFG_CMD_ATE_SET_ADDR3 0x010f +#define RACFG_CMD_ATE_SET_RATE 0x0110 +#define RACFG_CMD_ATE_SET_TX_FRAME_LEN 0x0111 +#define RACFG_CMD_ATE_SET_TX_FRAME_COUNT 0x0112 +#define RACFG_CMD_ATE_START_RX_FRAME 0x0113 +#define RACFG_CMD_ATE_E2PROM_READ_BULK 0x0114 +#define RACFG_CMD_ATE_E2PROM_WRITE_BULK 0x0115 +#define RACFG_CMD_ATE_IO_WRITE_BULK 0x0116 +#define RACFG_CMD_ATE_BBP_READ_BULK 0x0117 +#define RACFG_CMD_ATE_BBP_WRITE_BULK 0x0118 +#define RACFG_CMD_ATE_RF_READ_BULK 0x0119 +#define RACFG_CMD_ATE_RF_WRITE_BULK 0x011a +#define RACFG_CMD_ATE_SET_TX_POWER2 0x011b +#ifdef TXBF_SUPPORT +#define RACFG_CMD_ATE_TXBF_DUT_INIT 0x011c +#define RACFG_CMD_ATE_TXBF_LNA_CAL 0x011d +#define RACFG_CMD_ATE_TXBF_DIV_CAL 0x011e +#define RACFG_CMD_ATE_TXBF_PHASE_CAL 0x011f +#define RACFG_CMD_ATE_TXBF_GOLDEN_INIT 0x0120 +#define RACFG_CMD_ATE_TXBF_VERIFY 0x0121 +#endif /* TXBF_SUPPORT */ + + +/* QA RACFG Command for ate test from localhost */ +#define RACFG_CMD_ATE_SHOW_PARAM 0xff00 + +/* ATE export paramters to uppler layer */ +typedef struct __ATE_EX_PARAM +{ + unsigned char mode; + char TxPower0; + char TxPower1; +#ifdef DOT11N_SS3_SUPPORT + char TxPower2; +#endif /* DOT11N_SS3_SUPPORT */ + char TxAntennaSel; + char RxAntennaSel; + unsigned char DA[MAC_ADDR_LEN]; + unsigned char SA[MAC_ADDR_LEN]; + unsigned char BSSID[MAC_ADDR_LEN]; + unsigned char MCS; + unsigned char PhyMode; + BOOLEAN ShortGI; + BOOLEAN BW; + unsigned int Channel; + unsigned int TxLength; + unsigned int TxCount; + unsigned int RFFreqOffset; + unsigned int IPG; + unsigned int RxTotalCnt; + unsigned int RxCntPerSec; + char LastSNR0; + char LastSNR1; + char LastSNR2; + char LastRssi0; + char LastRssi1; + char LastRssi2; + char AvgRssi0; + char AvgRssi1; + char AvgRssi2; + short AvgRssi0X8; + short AvgRssi1X8; + short AvgRssi2X8; +}ATE_EX_PARAM, *pATE_EX_PARAM; + +NDIS_STATUS TXSTOP( + IN PRTMP_ADAPTER pAd); + +NDIS_STATUS RXSTOP( + IN PRTMP_ADAPTER pAd); + +#endif /* RALINK_QA */ + +#endif /* __RT_QA_H__ */ -- cgit v1.2.3