From d383f2bcdb6ff13cc562fce1ff55d826035debad Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Mon, 6 Mar 2023 17:36:31 +0100 Subject: Simplify source tree Now just use make in the root directory to build. --- AT91SAM7S256/Source/d_ioctrl.r | 237 ----------------------------------------- 1 file changed, 237 deletions(-) delete mode 100644 AT91SAM7S256/Source/d_ioctrl.r (limited to 'AT91SAM7S256/Source/d_ioctrl.r') diff --git a/AT91SAM7S256/Source/d_ioctrl.r b/AT91SAM7S256/Source/d_ioctrl.r deleted file mode 100644 index 1071276..0000000 --- a/AT91SAM7S256/Source/d_ioctrl.r +++ /dev/null @@ -1,237 +0,0 @@ -// -// Date init 14.12.2004 -// -// Revision date $Date:: 7-12-07 14:09 $ -// -// Filename $Workfile:: d_ioctrl.r $ -// -// Version $Revision:: 4 $ -// -// Archive $Archive:: /LMS2006/Sys01/Main_V02/Firmware/Source/d_ioct $ -// -// Platform C -// - - -#ifdef SAM7S256 - -extern void I2cHandler(void); - -enum -{ - I2C_IDLE = 1, - I2C_ERROR = 2, - I2C_TX = 3, - I2C_RX = 4 -}; - -#define NO_TO_TX BYTES_TO_TX + 1 -#define NO_TO_RX BYTES_TO_RX + 1 -#define TIMEOUT (((OSC/16)/1000)*30) /* 100 ms timeout on I2C*/ -#define I2CCLK 400000L -#define TIME400KHZ (((OSC/16L)/(I2CCLK * 2)) + 1) -#define CLDIV (((OSC/I2CCLK)/2)-3) -#define DEVICE_ADR 0x01 - - -static UBYTE *pIrq; -static UBYTE volatile Cnt; -static UBYTE I2cStatus; -static UBYTE I2cLastStatus; -static UBYTE I2cInBuffer[NO_TO_RX]; -static UBYTE I2cOutBuffer[COPYRIGHTSTRINGLENGTH + 1]; -static UBYTE RxSum; -static ULONG I2CTimerValue; - - -#define DISABLEI2cIrqs *AT91C_TWI_IDR = 0x000001C7 -#define ISSUEStopCond *AT91C_TWI_CR = AT91C_TWI_STOP -#define INSERTPower(Power) IoToAvr.Power = Power -#define INSERTPwm(Pwm) IoToAvr.PwmFreq = Pwm -#define SETTime I2CTimerValue = ((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV) - - -#define DISABLETwi *AT91C_PIOA_PPUDR = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* no pull up */\ - *AT91C_PIOA_MDER = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* SCL + SDA is open drain*/\ - *AT91C_PIOA_SODR = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* SCL + SDA is high */\ - *AT91C_PIOA_OER = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* SCL + SDA is output */\ - *AT91C_PIOA_PER = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* Disable peripheal */\ - - -#define STARTIrqTx I2cStatus = I2C_TX;\ - I2cLastStatus = I2C_TX;\ - pIrq = I2cOutBuffer;\ - *AT91C_TWI_CR = AT91C_TWI_MSEN;\ - *AT91C_TWI_MMR = (AT91C_TWI_IADRSZ_NO | (DEVICE_ADR << 16)); /* no int. adr, write dir */\ - *AT91C_TWI_IER = 0x00000104; /* Enable TX related irq */\ - *AT91C_TWI_THR = *pIrq - - -#define WAITClk {\ - ULONG PitTmr;\ - PitTmr = (*AT91C_PITC_PIIR & AT91C_PITC_CPIV) + TIME400KHZ;\ - if (PitTmr >= (*AT91C_PITC_PIMR & AT91C_PITC_CPIV))\ - {\ - PitTmr -= (*AT91C_PITC_PIMR & AT91C_PITC_CPIV);\ - }\ - while ((*AT91C_PITC_PIIR & AT91C_PITC_CPIV) < PitTmr);\ - } - - -#define RESETI2c {\ - UBYTE Tmp;\ - DISABLETwi;\ - Tmp = 0;\ - /* Clock minimum 9 times and both SCK and SDA should be high */\ - while((!(*AT91C_PIOA_PDSR & AT91C_PA3_TWD)) || (Tmp <= 9))\ - {\ - if ((*AT91C_PIOA_PDSR) & AT91C_PA4_TWCK) /* Clk strectching? */\ - {\ - *AT91C_PIOA_CODR = AT91C_PA4_TWCK; /* SCL is low */\ - WAITClk;\ - *AT91C_PIOA_SODR = AT91C_PA4_TWCK; /* SCL is high */\ - WAITClk;\ - Tmp++;\ - }\ - }\ - *AT91C_TWI_CR = AT91C_TWI_MSDIS;\ - *AT91C_TWI_CR = AT91C_TWI_SWRST;\ - *AT91C_PIOA_ASR = (AT91C_PA4_TWCK | AT91C_PA3_TWD); /* Sel. per. A */\ - *AT91C_PIOA_PDR = (AT91C_PA4_TWCK | AT91C_PA3_TWD); /* Sel. per on pins*/\ - } - - -#define IOCTRLInit *AT91C_AIC_IDCR = (1L<