From b24866225a6301d3a663f874725e83c012dc25d3 Mon Sep 17 00:00:00 2001 From: Florent Duchon Date: Wed, 26 Dec 2012 17:36:00 +0100 Subject: digital/beacon: add bitcloud stack into common directory digital/zigbit --- .../HAL/avr/atmega1281/common/src/halW1.s90 | 211 +++++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halW1.s90 (limited to 'digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halW1.s90') diff --git a/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halW1.s90 b/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halW1.s90 new file mode 100644 index 00000000..a12f063d --- /dev/null +++ b/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halW1.s90 @@ -0,0 +1,211 @@ +/**************************************************************************//** + \file halW1.s90 + + \brief Implementation of 1-wire hardware-dependent module. + + \author + Atmel Corporation: http://www.atmel.com \n + Support email: avr@atmel.com + + Copyright (c) 2008-2011, Atmel Corporation. All rights reserved. + Licensed under Atmel's Limited License Agreement (BitCloudTM). + + \internal + History: + 29/05/07 E. Ivanov - Created + ******************************************************************************/ +/****************************************************************************** + * WARNING: CHANGING THIS FILE MAY AFFECT CORE FUNCTIONALITY OF THE STACK. * + * EXPERT USERS SHOULD PROCEED WITH CAUTION. * + ******************************************************************************/ + +#include +__w1_port VAR 0x14 ; PORTG +__w1_bit VAR 5 ; PORTG5 +__w1_ddr VAR 0x13 ; DDRG +__w1_pin VAR 0x12 ; PING + +/*============================================================= + Resets all devices connected to the bus. Function asserts on + the bus reset pulse and detects presence pulse. The result is + contained in r16. + Parameters: + Returns: + W1_SUCCESS_STATUS - If device(s) was(were) detected. + W1_NO_DEVICE_STATUS - If device(s) was(were) not detected. +===============================================================*/ +PUBLIC halResetW1 +RSEG CODE +halResetW1: + ; Store SREG + push r23 + in r23, 0x3F + ; Disable interrupts + cli + ; Pull down + sbi __w1_ddr, __w1_bit + cbi __w1_port, __w1_bit + ; Reset Low Time (500 us) + ldi r16, 250 + call __delay_us + ldi r16, 250 + call __delay_us + ; Tri-state (external pullup) + cbi __w1_ddr, __w1_bit + ; Presence-Detect Sample Time (70 us) + ldi r16, 70 + call __delay_us + ; Precense-Detect + ldi r16, 0x01 + sbic __w1_pin, __w1_bit + ldi r16, 0x00 + push r16 + ; Tail of Reset High Time + ldi r16, 240 + call __delay_us + pop r16 + ; Restore SREG + out 0x3F, r23 + pop r23 + ret + +/*============================================================= + Reads bit from the bus + Returns: + bit read from the bus in r16 +===============================================================*/ +PUBLIC halReadW1Bit +RSEG CODE +halReadW1Bit: + ; Store SREG + push r23 + in r23, 0x3F + ; Disable interrupts + cli + ; Pull down + sbi __w1_ddr, __w1_bit + cbi __w1_port, __w1_bit + ; Read Low Time (6 us) + ldi r16, 6 + call __delay_us + ; Tri-state (external pullup) + cbi __w1_ddr, __w1_bit + ; Tail of Read Sample Time (10 us) + ldi r16, 10 + call __delay_us + ; Read Sample + clc + sbic __w1_pin, __w1_bit + sec + rol r16 + ; Tail of Timeslot Duration + push r16 + ldi r16, 100 + call __delay_us + pop r16 + ; Restore SREG + out 0x3F, r23 + pop r23 + ret + +/*============================================================= + Reads byte from the bus + Returns: + byte read from the bus in r16 +===============================================================*/ +PUBLIC halReadW1 +RSEG CODE +halReadW1: + push r25 + push r23 + ldi r25, 8 +__read_bit_again: + call halReadW1Bit + ror r16 + ror r23 + dec r25 + tst r25 + brne __read_bit_again + mov r16, r23 + pop r23 + pop r25 + ret + +/*============================================================= + Writes bit to the bus + Parameters: + value - bit that should be written to the bus. +===============================================================*/ +PUBLIC halWriteW1bit +RSEG CODE +halWriteW1bit: + ; Store SREG + push r23 + in r23, 0x3F + ; Disable interrupts + cli + ; Pull down + cbi __w1_port, __w1_bit + sbi __w1_ddr, __w1_bit + ; Write-1 Low Time + push r16 + ldi r16, 6 + call __delay_us + pop r16 + ; Write bit + ror r16 + brcc __w1_write_zero + ; Write-One -> tri-state (external pullup) + cbi __w1_ddr, __w1_bit +__w1_write_zero: + ; Tail of Timeslot Duration + push r16 + ldi r16, 100 + call __delay_us + pop r16 + ; Tri-state (external pullup) + cbi __w1_ddr, __w1_bit + ; Restore SREG + out 0x3F, r23 + pop r23 + ret + +/*============================================================= + Writes byte to the bus + Parameters: + value - byte that should be written to the bus. +===============================================================*/ +PUBLIC halWriteW1 +RSEG CODE +halWriteW1: + push r25 + ldi r25, 8 +__write_bit_again: + call halWriteW1bit + dec r25 + tst r25 + brne __write_bit_again + pop r25 + ret + +/*============================================================= + Delay in microseconds. + Parameters: + us - delay time in microseconds +===============================================================*/ +PUBLIC __delay_us +RSEG CODE +__delay_us: +__w0: +#if FCPU==8000000 + nop + nop + nop + nop +#endif + dec r16 + tst r16 + brne __w0 + ret +; eof halW1.s +END -- cgit v1.2.3