From b24866225a6301d3a663f874725e83c012dc25d3 Mon Sep 17 00:00:00 2001 From: Florent Duchon Date: Wed, 26 Dec 2012 17:36:00 +0100 Subject: digital/beacon: add bitcloud stack into common directory digital/zigbit --- .../HAL/avr/atmega1281/common/src/halUsart.c | 190 +++++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halUsart.c (limited to 'digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halUsart.c') diff --git a/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halUsart.c b/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halUsart.c new file mode 100644 index 00000000..90388ed0 --- /dev/null +++ b/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halUsart.c @@ -0,0 +1,190 @@ +/**************************************************************************//** +\file halUsart.c + +\brief Implementation of usart hardware-dependent module. + +\author + Atmel Corporation: http://www.atmel.com \n + Support email: avr@atmel.com + + Copyright (c) 2008-2011, Atmel Corporation. All rights reserved. + Licensed under Atmel's Limited License Agreement (BitCloudTM). + +\internal + History: + 29/05/07 E. Ivanov - Created +*******************************************************************************/ +/****************************************************************************** + * WARNING: CHANGING THIS FILE MAY AFFECT CORE FUNCTIONALITY OF THE STACK. * + * EXPERT USERS SHOULD PROCEED WITH CAUTION. * + ******************************************************************************/ +/****************************************************************************** + Includes section +******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include + +/****************************************************************************** + Prototypes section +******************************************************************************/ +void halPostUsartTask(HalUsartTaskId_t taskId); + +/****************************************************************************** + External global variables section +******************************************************************************/ +extern volatile bool halEnableDtrWakeUp; +extern void (* dtrWakeUpCallback)(void); + +/****************************************************************************** + Implementations section +******************************************************************************/ +/**************************************************************************//** + \brief Sets USART module parameters. + \param + usartmode - pointer to HAL_UsartDescriptor_t + \return + none. +******************************************************************************/ +void halSetUsartConfig(HAL_UsartDescriptor_t *usartMode) +{ + UCSRnB(usartMode->tty) = 0x00; // disable usart + UBRRn(usartMode->tty) = usartMode->baudrate; // usart speed + + if (USART_MODE_ASYNC == usartMode->mode) + { + UCSRnA(usartMode->tty) = (uint8_t)USART_DOUBLE_SPEED << U2X0; // Double the USART Transmition Speed + UCSRnC(usartMode->tty) = 0x00; + } + else + { + UCSRnA(usartMode->tty) = 0; + UCSRnC(usartMode->tty) = usartMode->edge; // edge select + } + + UCSRnC(usartMode->tty) |= usartMode->mode; + UCSRnC(usartMode->tty) |= usartMode->dataLength; // character size + UCSRnC(usartMode->tty) |= usartMode->parity; // parity mode + UCSRnC(usartMode->tty) |= usartMode->stopbits; // stop bit select + UCSRnA(usartMode->tty) |= (1 << RXC0); // clear receive interrupt + UCSRnB(usartMode->tty) |= (1 << RXEN1) | (1 << TXEN1); // usart enable + UCSRnB(usartMode->tty) |= (1 << RXCIE0) ; // receive interrupt enable +} + +/**************************************************************************//** + \brief The interrupt handler of USART0 - data register is empty. +******************************************************************************/ +ISR(USART0_UDRE_vect) +{ + BEGIN_MEASURE + // We must disable the interrupt because we must "break" context. + halDisableUsartDremInterrupt(USART_CHANNEL_0); + halPostUsartTask(HAL_USART_TASK_USART0_DRE); + END_MEASURE(HALISR_USART0_UDR_TIME_LIMIT) +} + +/**************************************************************************//** + \brief The interrupt handler of USART0 - transmission is completed. +******************************************************************************/ +ISR(USART0_TX_vect) +{ + BEGIN_MEASURE + halDisableUsartTxcInterrupt(USART_CHANNEL_0); + halPostUsartTask(HAL_USART_TASK_USART0_TXC); + END_MEASURE(HALISR_USART0_TX_TIME_LIMIT) +} + +/**************************************************************************//** + \brief The interrupt handler of USART0 - reception is completed. +******************************************************************************/ +ISR(USART0_RX_vect) +{ + BEGIN_MEASURE + uint8_t status = UCSR0A; + uint8_t data = UDR0; + + if (!(status & ((1 << FE0) | (1 << DOR0) | (1 << UPE0)))) + { + halUsartRxBufferFiller(USART_CHANNEL_0, data); + halPostUsartTask(HAL_USART_TASK_USART0_RXC); + } + #if defined(_USE_USART_ERROR_EVENT_) + else // There is an error in the received byte. + { + halUsartSaveErrorReason(USART_CHANNEL_0, status); + halPostUsartTask(HAL_USART_TASK_USART0_ERR); + } + #endif + + END_MEASURE(HALISR_USART0_RX_TIME_LIMIT) +} + +/**************************************************************************//** + \brief The interrupt handler of USART1 - data register is empty. +******************************************************************************/ +ISR(USART1_UDRE_vect) +{ + BEGIN_MEASURE + // We must disable the interrupt because we must "break" context. + halDisableUsartDremInterrupt(USART_CHANNEL_1); + halPostUsartTask(HAL_USART_TASK_USART1_DRE); + END_MEASURE(HALISR_USART1_UDRE_TIME_LIMIT) +} + +/**************************************************************************//** + \brief The interrupt handler of USART1 - transmission is completed. +******************************************************************************/ +ISR(USART1_TX_vect) +{ + BEGIN_MEASURE + halDisableUsartTxcInterrupt(USART_CHANNEL_1); + halPostUsartTask(HAL_USART_TASK_USART1_TXC); + END_MEASURE(HALISR_USART1_TX_TIME_LIMIT) +} + +/**************************************************************************//** + \brief The interrupt handler of USART1 - reception is completed. +******************************************************************************/ +ISR(USART1_RX_vect) +{ + BEGIN_MEASURE + uint8_t status = UCSR1A; + uint8_t data = UDR1; + + if (!(status & ((1 << FE1) | (1 << DOR1) | (1 << UPE1)))) + { + halUsartRxBufferFiller(USART_CHANNEL_1, data); + halPostUsartTask(HAL_USART_TASK_USART1_RXC); + } + #if defined(_USE_USART_ERROR_EVENT_) + else // There is an error in the received byte. + { + halUsartSaveErrorReason(USART_CHANNEL_1, status); + halPostUsartTask(HAL_USART_TASK_USART1_ERR); + } + #endif + END_MEASURE(HALISR_USART1_RX_TIME_LIMIT) +} + +/**************************************************************************//** +/brief External interrupt 4 (DTR) handler +******************************************************************************/ +ISR(INT4_vect) +{ + BEGIN_MEASURE + halWakeupFromIrq(); + + if (halEnableDtrWakeUp) + { /* enable DTR (irq 4) wake up */ + halDisableIrqInterrupt(IRQ_4); + } /* enable DTR (irq 4) wake up */ + + if (NULL != dtrWakeUpCallback) + dtrWakeUpCallback(); + END_MEASURE(HALISR_INT4_TIME_LIMIT) +} +// eof halUsart.c -- cgit v1.2.3