From d578aab00d511d4254ec200558bf2f17db481b73 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Sat, 30 Jun 2007 17:45:54 +0200 Subject: Added hdlcounter for CPLD. Verilog source files and test cases. --- digital/asserv/src/hdlcounter/test_input_latch.wave | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 digital/asserv/src/hdlcounter/test_input_latch.wave (limited to 'digital/asserv/src/hdlcounter/test_input_latch.wave') diff --git a/digital/asserv/src/hdlcounter/test_input_latch.wave b/digital/asserv/src/hdlcounter/test_input_latch.wave new file mode 100644 index 00000000..50af7fd0 --- /dev/null +++ b/digital/asserv/src/hdlcounter/test_input_latch.wave @@ -0,0 +1,14 @@ +*-15,452410 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +test_input_latch.clk +test_input_latch.rst +test_input_latch.q +test_input_latch.ql +test_input_latch.ql1 +test_input_latch.ql2 +test_input_latch.qlr1 +test_input_latch.qlr2 +test_input_latch.qnl1 +test_input_latch.qnl2 +test_input_latch.qnlr1 +test_input_latch.qnlr2 -- cgit v1.2.3