From d578aab00d511d4254ec200558bf2f17db481b73 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Sat, 30 Jun 2007 17:45:54 +0200 Subject: Added hdlcounter for CPLD. Verilog source files and test cases. --- digital/asserv/src/hdlcounter/test_counter_top.wave | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 digital/asserv/src/hdlcounter/test_counter_top.wave (limited to 'digital/asserv/src/hdlcounter/test_counter_top.wave') diff --git a/digital/asserv/src/hdlcounter/test_counter_top.wave b/digital/asserv/src/hdlcounter/test_counter_top.wave new file mode 100644 index 00000000..338660ef --- /dev/null +++ b/digital/asserv/src/hdlcounter/test_counter_top.wave @@ -0,0 +1,18 @@ +*-17,989300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +test_counter_top.clk +test_counter_top.rst +@420 +test_counter_top.countdiv32_0[27:0] +test_counter_top.countdiv32_1[27:0] +test_counter_top.countdiv32_2[27:0] +test_counter_top.countdiv32_3[27:0] +@28 +test_counter_top.oe +test_counter_top.sel[1:0] +@22 +test_counter_top.countout[7:0] +test_counter_top.uut.count0[7:0] +test_counter_top.uut.count1[7:0] +test_counter_top.uut.count2[7:0] +test_counter_top.uut.count3[7:0] -- cgit v1.2.3