From d578aab00d511d4254ec200558bf2f17db481b73 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Sat, 30 Jun 2007 17:45:54 +0200 Subject: Added hdlcounter for CPLD. Verilog source files and test cases. --- digital/asserv/src/hdlcounter/input_latch.v | 46 +++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 digital/asserv/src/hdlcounter/input_latch.v (limited to 'digital/asserv/src/hdlcounter/input_latch.v') diff --git a/digital/asserv/src/hdlcounter/input_latch.v b/digital/asserv/src/hdlcounter/input_latch.v new file mode 100644 index 00000000..5eb059d4 --- /dev/null +++ b/digital/asserv/src/hdlcounter/input_latch.v @@ -0,0 +1,46 @@ +// input_latch.v - Input latch to protect from input change near clock edge. +// hdlcounter - Incremental encoder counter on programmable logic. {{{ +// +// Copyright (C) 2007 Nicolas Schodet +// +// Robot APB Team 2008. +// Web: http://apbteam.org/ +// Email: team AT apbteam DOT org +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +// +// }}} +`timescale 1ns / 1ps + +// Input should be latched at clock rising edge in one and only one flip-flop. +// If this latch is not done, two flip-flops connected to the input might +// receive a different value if the input switch near the clock rising edge. + +module input_latch(clk, rst, q, ql); + input clk; + input rst; + input q; + output ql; + + reg ql; + + always @(posedge clk or negedge rst) begin + if (!rst) + ql <= 0; + else + ql <= q; + end + +endmodule -- cgit v1.2.3