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Diffstat (limited to 'digital/avr/modules/spi/spi_hard.avr.c')
-rw-r--r--digital/avr/modules/spi/spi_hard.avr.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/digital/avr/modules/spi/spi_hard.avr.c b/digital/avr/modules/spi/spi_hard.avr.c
index 15282dde..f875039d 100644
--- a/digital/avr/modules/spi/spi_hard.avr.c
+++ b/digital/avr/modules/spi/spi_hard.avr.c
@@ -46,6 +46,13 @@
# error "spi: not implemented on this chip"
#endif
+/** WARNING: there is some assertions in GPIO settings which should be
+ * verified:
+ * - does SCK initial value match selected mode?
+ * - should a pull-up be used on inputs?
+ * - can SS be reset as an input on uninit?
+ */
+
void
spi_hard_init_ (uint8_t spcr, uint8_t spi2x)
{
@@ -84,6 +91,23 @@ spi_hard_init_ (uint8_t spcr, uint8_t spi2x)
}
void
+spi_hard_uninit (void)
+{
+ /* Reset MISO now for slave mode (see above, no effect in master mode). */
+ IO_DDR (SPI_MISO_IO) &= ~IO_BV (SPI_MISO_IO);
+ IO_PORT (SPI_MISO_IO) &= ~IO_BV (SPI_MISO_IO);
+ /* Disable SPI. */
+ SPCR = 0;
+ /* Reset GPIO configuration. */
+ IO_DDR (SPI_SS_IO) &= ~IO_BV (SPI_SS_IO);
+ IO_PORT (SPI_SS_IO) &= ~IO_BV (SPI_SS_IO);
+ IO_DDR (SPI_MOSI_IO) &= ~IO_BV (SPI_MOSI_IO);
+ IO_PORT (SPI_MOSI_IO) &= ~IO_BV (SPI_MOSI_IO);
+ IO_DDR (SPI_SCK_IO) &= ~IO_BV (SPI_SCK_IO);
+ IO_PORT (SPI_SCK_IO) &= ~IO_BV (SPI_SCK_IO);
+}
+
+void
spi_hard_send (uint8_t data)
{
spi_hard_send_and_recv (data);