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authorNicolas Schodet2007-08-01 09:55:47 +0200
committerNicolas Schodet2007-08-01 09:55:47 +0200
commita17dafb4961bc8b849a09c69d1129f75cf1e267e (patch)
tree933797b20a5bf2ebd7dda2145f079171aad00225
parentd9dbca3c5bbbecbbc12b99c9e330ec1119e281ae (diff)
Fixed switch operand sizes in quad_decoder_div4.
Added an output latch, now output will not change when oe is one.
-rw-r--r--digital/asserv/src/hdlcounter/counter_top.v22
-rw-r--r--digital/asserv/src/hdlcounter/quad_decoder_div4.v4
-rw-r--r--digital/asserv/src/hdlcounter/test_counter_top.v9
3 files changed, 23 insertions, 12 deletions
diff --git a/digital/asserv/src/hdlcounter/counter_top.v b/digital/asserv/src/hdlcounter/counter_top.v
index fa1b737c..0c313704 100644
--- a/digital/asserv/src/hdlcounter/counter_top.v
+++ b/digital/asserv/src/hdlcounter/counter_top.v
@@ -48,11 +48,21 @@ module counter_top(clk, rst, q0, q1, q2, q3, oe, sel, count);
input_latch f3[1:0] (clk, rst, q3, qf3);
quad_decoder_full qd3 (clk, rst, qf3, count3);
- assign count =
- !oe ? 8'bz :
- sel == 0 ? count0 :
- sel == 1 ? count1 :
- sel == 2 ? count2 :
- count3;
+ reg [size-1:0] lcount;
+
+ always @(posedge clk or negedge rst) begin
+ if (!rst)
+ lcount <= 0;
+ else begin
+ if (!oe) begin
+ lcount <= sel == 0 ? count0 :
+ sel == 1 ? count1 :
+ sel == 2 ? count2 :
+ count3;
+ end
+ end
+ end
+
+ assign count = !oe ? 8'bz : lcount;
endmodule
diff --git a/digital/asserv/src/hdlcounter/quad_decoder_div4.v b/digital/asserv/src/hdlcounter/quad_decoder_div4.v
index 5021141b..eb5fab87 100644
--- a/digital/asserv/src/hdlcounter/quad_decoder_div4.v
+++ b/digital/asserv/src/hdlcounter/quad_decoder_div4.v
@@ -60,10 +60,10 @@ module quad_decoder_div4(clk, rst, q, count);
else begin
case ({ q[0], zq1, q[1] })
// 1 to 0 transition on q[1], when q[0] is 0.
- 2'b0_1_0:
+ 3'b0_1_0:
count <= count + 1;
// 0 to 1 transition on q[1], when q[0] is 0.
- 2'b0_0_1:
+ 3'b0_0_1:
count <= count - 1;
default:
count <= count;
diff --git a/digital/asserv/src/hdlcounter/test_counter_top.v b/digital/asserv/src/hdlcounter/test_counter_top.v
index b0ff69a1..820cea4a 100644
--- a/digital/asserv/src/hdlcounter/test_counter_top.v
+++ b/digital/asserv/src/hdlcounter/test_counter_top.v
@@ -42,7 +42,7 @@ module test_counter_top();
// Counter top setup.
wire [0:nc-1] quad_full = 4'b0011;
reg [31:0] filter_size[0:nc-1];
- parameter max_filter = 5;
+ parameter max_filter = 7;
initial begin
filter_size[0] = 4;
filter_size[1] = 4;
@@ -121,7 +121,7 @@ module test_counter_top();
@(negedge clk)
// Check result *after* rising edge.
if (oe) begin
- countassert = countdiv32_smp[sel*max_filter + filter_size[sel]];
+ countassert = countdiv32_smp[sel*max_filter + filter_size[sel] + 2];
countassert8 = quad_full[sel] ? countassert[7:0] : countassert[9:2];
// If equiped with a noise filter, accept a difference of 1.
// This is more difficult to find the exact expected value (I
@@ -135,11 +135,12 @@ module test_counter_top();
assertv8 (8'bz, countout);
end
// Prepare next check.
- if (($mti_random & 6'b111111) == 0)
+ if (oe == 1) begin
oe = 0;
+ sel = $random & 2'b11;
+ end
else begin
oe = 1;
- sel = $random & 2'b11;
end
end
end