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path: root/n/asserv/src/counter/test_counter_top.v
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`timescale 1ns / 1ps

module test_counter_top();
    reg clk, rst;
    reg [1:0] c0, c1, c2, c3;
    wire [1:0] q0, q1, q2, q3;
    reg oe;
    reg [1:0] sel;
    wire [7:0] counter;

    initial begin
	$dumpfile ("test_counter_top.vcd");
	$dumpvars;
	clk = 1;
	rst = 0;
	c0 = 0;
	c1 = 0;
	c2 = 0;
	c3 = 0;
	oe = 1;
	sel = 0;
	#1 rst = 1;
	repeat (10) begin
	    @(negedge clk);
	    @(negedge clk);
	    c0 = c0 + 1;
	    c1 = c1 - 1;
	    @(negedge clk);
	    @(negedge clk);
	    c0 = c0 + 1;
	    c1 = c1 - 1;
	    c2 = c2 + 1;
	    c3 = c3 - 1;
	end
	#4
	#4 sel = 1;
	#4 sel = 2;
	#4 sel = 3;
	#4 sel = 0;
	repeat (10) begin
	    @(negedge clk);
	    @(negedge clk);
	    c0 = c0 - 1;
	    c1 = c1 + 1;
	    @(negedge clk);
	    @(negedge clk);
	    c0 = c0 - 1;
	    c1 = c1 + 1;
	    c2 = c2 - 1;
	    c3 = c3 + 1;
	end
	#4
	#4 sel = 1;
	#4 sel = 2;
	#4 sel = 3;
	#4 sel = 0;
	oe = 0;
	repeat (1000) begin
	    @(negedge clk);
	    @(negedge clk);
	    c0 = c0 + 1;
	    c1 = c1 - 1;
	    @(negedge clk);
	    @(negedge clk);
	    c0 = c0 + 1;
	    c1 = c1 - 1;
	    c2 = c2 + 1;
	    c3 = c3 - 1;
	end
	oe = 1;
	#4
	#4 sel = 1;
	#4 sel = 2;
	#4 sel = 3;
	#4 sel = 0;
	#100 $finish;
    end

    // Clock generator.
    always
	#2 clk = !clk;

    // Instantiation.
    assign q0 = { c0[1], c0[1] ^ c0[0] };
    assign q1 = { c1[1], c1[1] ^ c1[0] };
    assign q2 = { c2[1], c2[1] ^ c2[0] };
    assign q3 = { c3[1], c3[1] ^ c3[0] };
    counter_top UUT (clk, rst, q0, q1, q2, q3, oe, sel, counter);
endmodule