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path: root/n/asserv/src/counter/spi_output.v
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`timescale 1ns / 1ps

module spi_output (clk, rst, val0, val1, val2, val3, sck, ss, so);
    parameter bits = 8;
    input clk;
    input rst;
    input [bits-1:0] val0;
    input [bits-1:0] val1;
    input [bits-1:0] val2;
    input [bits-1:0] val3;
    input sck;
    input ss;
    output so;

    reg ss_l;
    reg sck_l;
    reg [1:0] sel;
    reg [bits:0] sr;

    always @(posedge clk or negedge rst) begin
	if (!rst) begin
	    ss_l <= 0;
	    sck_l <= 0;
	    sel <= 0;
	    sr <= 0;
	end
	else begin
	    if (!ss && ss_l) begin
		sr <= { 1, val0 };
		sel <= 0;
	    end
	    else if (!sck && sck_l) begin
		if (sr)
		    sr <= { 0, sr[bits - 1:1] };
		else begin
		    case (sel)
			2'b00:
			    sr <= val1;
			2'b01:
			    sr <= val2;
			2'b10:
			    sr <= val3;
			2'b11:
			    sr <= val0;
		    endcase
		    sel <= sel + 1;
		end
	    end
	    ss_l <= ss;
	    sck_l <= sck;
	end
    end

    assign so = !ss ? sr[0] : 1'bz;

endmodule