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`timescale 1ns / 1ps

module quad_filter(clk, rst, q, qf);
    input clk;
    input rst;
    input q;
    output qf;

    reg qf;
    //reg [1:0] hist;


    always @(posedge clk or negedge rst) begin
	if (!rst) begin
	    qf <= 0;
	    //hist <= 2'b00;
	end
	else begin
	    /*
	    // Output filter logic.
	    if (hist[1] && hist[0])
		qf <= 1;
	    else if (!hist[1] && !hist[0])
		qf <= 0;
	    else
		qf <= qf;
	    // Input buffer.
	    hist <= { hist[0], q };
	    */
	    qf <= q;
	end
    end

endmodule