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`timescale 1ns / 1ps

module quad_decoder(clk, rst, q, counter);
    parameter bits = 8;
    input clk;
    input rst;
    input [1:0] q;
    output [bits-1:0] counter;

    reg [1:0] ql;
    reg [bits-1:0] counter;

    always @(posedge clk or negedge rst) begin
	if (!rst) begin
	    ql <= 2'b00;
	    counter <= 0;
	end
	else begin
	    case ({ ql, q })
		4'b0001:
		    counter <= counter + 1;
		4'b0010:
		    counter <= counter - 1;
		4'b0111:
		    counter <= counter + 1;
		4'b0100:
		    counter <= counter - 1;
		4'b1110:
		    counter <= counter + 1;
		4'b1101:
		    counter <= counter - 1;
		4'b1000:
		    counter <= counter + 1;
		4'b1011:
		    counter <= counter - 1;
		default:
		    counter <= counter;
	    endcase
	    ql <= q;
	end
    end
endmodule