`timescale 1ns / 1ps module test_quad_filter(); reg clk; reg rst; reg q; wire qf; initial begin //$display ("time\t clk q qf"); //$monitor ("%g\t %b %b %b", $time, clk, q, qf); $dumpfile ("test_quad_filter.vcd"); $dumpvars; clk = 1; rst = 0; q = 0; #1 rst = 1; #4 q = 1; #4 q = 1; #4 q = 1; #4 q = 1; #4 q = 0; #4 q = 0; #4 q = 0; #4 q = 0; #4 q = 0; #4 q = 1; #4 q = 0; #4 q = 0; #4 q = 0; #4 q = 0; #4 q = 0; #4 $finish; end // Clock generator. always #2 clk = !clk; // Instantiation. quad_filter UUT (clk, rst, q, qf); endmodule