`timescale 1ns / 1ps module counter_top(clk, rst, q0, q1, q2, q3, oe, sel, counter); input clk; input rst; input [1:0] q0; input [1:0] q1; input [1:0] q2; input [1:0] q3; input oe; input [1:0] sel; output [7:0] counter; //input sck; // Serial clock //input ss; // Slave select //input si; // Serial in //output so; // Serial out wire [1:0] qf0; wire [1:0] qf1; wire [1:0] qf2; wire [1:0] qf3; wire [7:0] counter0; wire [7:0] counter1; wire [7:0] counter2; wire [7:0] counter3; quad_filter f0[1:0] (clk, rst, q0, qf0); quad_decoder qd0 (clk, rst, qf0, counter0); quad_filter f1[1:0] (clk, rst, q1, qf1); quad_decoder qd1 (clk, rst, qf1, counter1); quad_filter f2[1:0] (clk, rst, q2, qf2); quad_decoder qd2 (clk, rst, qf2, counter2); quad_filter f3[1:0] (clk, rst, q3, qf3); quad_decoder qd3 (clk, rst, qf3, counter3); //assign counter = { counter3, counter2, counter1, counter0 }; //spi_output spio (clk, rst, counter0, counter1, counter2, counter3, sck, ss, so); assign counter = !oe ? 8'bz : sel == 0 ? counter0 : sel == 1 ? counter1 : sel == 2 ? counter2 : counter3; endmodule