From 3410f6e649992bcac7674fdc8e282927fa09e3de Mon Sep 17 00:00:00 2001 From: schodet Date: Sun, 24 Jul 2005 09:17:11 +0000 Subject: Ajout des cartes asserv et du verilog pour le compteur. --- n/asserv/src/counter/counter_top.v | 49 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 n/asserv/src/counter/counter_top.v (limited to 'n/asserv/src/counter/counter_top.v') diff --git a/n/asserv/src/counter/counter_top.v b/n/asserv/src/counter/counter_top.v new file mode 100644 index 0000000..5d32c2c --- /dev/null +++ b/n/asserv/src/counter/counter_top.v @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps + +module counter_top(clk, rst, q0, q1, q2, q3, oe, sel, counter); + input clk; + input rst; + input [1:0] q0; + input [1:0] q1; + input [1:0] q2; + input [1:0] q3; + input oe; + input [1:0] sel; + output [7:0] counter; + //input sck; // Serial clock + //input ss; // Slave select + //input si; // Serial in + //output so; // Serial out + + wire [1:0] qf0; + wire [1:0] qf1; + wire [1:0] qf2; + wire [1:0] qf3; + wire [7:0] counter0; + wire [7:0] counter1; + wire [7:0] counter2; + wire [7:0] counter3; + + quad_filter f0[1:0] (clk, rst, q0, qf0); + quad_decoder qd0 (clk, rst, qf0, counter0); + + quad_filter f1[1:0] (clk, rst, q1, qf1); + quad_decoder qd1 (clk, rst, qf1, counter1); + + quad_filter f2[1:0] (clk, rst, q2, qf2); + quad_decoder qd2 (clk, rst, qf2, counter2); + + quad_filter f3[1:0] (clk, rst, q3, qf3); + quad_decoder qd3 (clk, rst, qf3, counter3); + + //assign counter = { counter3, counter2, counter1, counter0 }; + //spi_output spio (clk, rst, counter0, counter1, counter2, counter3, sck, ss, so); + + assign counter = + !oe ? 8'bz : + sel == 0 ? counter0 : + sel == 1 ? counter1 : + sel == 2 ? counter2 : + counter3; + +endmodule -- cgit v1.2.3