path: root/a/puiss-barillet/note_programmeur.txt
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authorburg2006-03-12 19:46:18 +0000
committerburg2006-03-12 19:46:18 +0000
commit466ea4f42c922b0c45650cf6c5fa4fe67c8bb7df (patch)
tree8ddd71f6595978fd99e8cdc67bf4450c008ab5e8 /a/puiss-barillet/note_programmeur.txt
parent13b56b3d5689d797bcc325b261ea7d22889efb31 (diff)
Modification des schémas:
-correction des optocoupleurs -correction des branchements pour la partie turbine -correction des branchements autour du LMD18200 TODO_schema: -l'alimentation -choisir les composants -tout ça voila bref ... vous savez ...
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+To ensure proper internal logic performance, it is good prac-
+tice to avoid aligning the falling and rising edges of input sig-
+nals. A delay of at least 1 sec should be incorporated be-
+tween transitions of the Direction, Brake, and/or PWM input
+signals. A conservative approach is be sure there is at least
+500ns delay between the end of the first transition and the
+beginning of the second transition.