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--rtl bench de la sortie pwm en fonction de tc test � faire sur41MS environ
library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.std_logic_arith.all;
 use IEEE.std_logic_unsigned.all;
library synopsys;
use synopsys.bv_arithmetic.all;
--ENTITY
entity tb_affichepwm3 is
end tb_affichepwm3;
--ARCHITECTURE
architecture sim1 of tb_affichepwm3 is
  component affichepwm3
   port(rst		: in std_logic;
        clk		: in std_logic;
         clk1usaff	: in std_logic;
      --  tcaff		: in integer;
        valueaff	: in integer;
        outpwm		: out std_logic              
     );      
 end component;
-- declaration des signaux
signal clk : std_logic:='0';
  signal clk1usaff : std_logic:='0';
  signal rst : std_logic;
signal tcaff: integer :=20161;         --mettre a 20161
signal valueaff: integer:=0;
signal outpwm 	: std_logic;
--declaration de constantes
constant CLK1US_PERIOD	:time:= 992 ns;
constant tcmax		:integer:= 20161;  --pour le clk1us
constant CLK_PERIOD 	:time	:= 32 ns ;
  
begin
  U1affichepwm3: affichepwm3 port map (
    rst=>rst,clk=>clk,clk1usaff=>clk1usaff,
  --  tcaff=>tcaff,
    valueaff=>valueaff,
    outpwm=>outpwm
    );
  
--STIMULI
 rst<='1','0'after (CLK1US_PERIOD/3);
  clk<= not clk after (CLK_PERIOD/2);
  clk1usaff<= not clk1usaff after (CLK1US_PERIOD/2);
--tcaff<=tcmax,0 after (tcmax*CLK1US_PERIOD),
       --tcmax after (2*(tcmax*CLK1US_PERIOD)),
       --0 after (3*(tcmax*CLK1US_PERIOD)),
       --tcmax after (4*(tcmax*CLK1US_PERIOD));
        
valueaff<= 0,90 after((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/2)),
           0 after((tcmax*CLK1US_PERIOD)+(CLK1US_PERIOD*2)),
           12 after((2*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2));
end sim1;

--CONFIGURATION
configuration cfg_tb_affichepwm3 of tb_affichepwm3 is
  for sim1
   for all : affichepwm3 use entity work.affichepwm3(affichepwm3behav);
  end for;
end for;
end cfg_tb_affichepwm3;