summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/fpga/fpga-test.vhd
blob: 4459bef026c0e00bd7d55e911e3eb912d72c9b96 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
-- VHDL Test Bench Created from source file fpga.vhd -- 17:38:53 03/30/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;

use	work.nono_const.all;
use	work.isa_const.all;

ENTITY bch_fpga IS
END bch_fpga;

ARCHITECTURE behavior OF bch_fpga IS 
	COMPONENT fpga
	PORT(
		rst : IN std_logic;
		clk_speed : IN std_logic;
		clk_ref : IN std_logic;
		AEN : IN std_logic;
		IOR : IN std_logic;
		IOW : IN std_logic;
		bus_adr : IN std_logic_vector(23 downto 0);
		rxin1 : IN std_logic;    
		bus_data : INOUT std_logic_vector(7 downto 0);      
		irq : OUT std_logic;
		irqrxFIFO : OUT std_logic;
		irqrxRX : OUT std_logic;
		irqrxERR : OUT std_logic;
		irqtx : OUT std_logic;
		txout1 : OUT std_logic
		);
	END COMPONENT;


	SIGNAL rst :  std_logic:='0';
	SIGNAL clk_speed :  std_logic:='0';
	SIGNAL clk_ref :  std_logic:='0';
	SIGNAL AEN :  std_logic;
	SIGNAL IOR :  std_logic;
	SIGNAL IOW :  std_logic;
	SIGNAL bus_adr :  std_logic_vector(23 downto 0);
	SIGNAL bus_data :  std_logic_vector(7 downto 0);
	SIGNAL irq :  std_logic;
	SIGNAL irqrxFIFO,irqrxRX,irqrxERR,irqtx : std_logic;

	SIGNAL rxin1 :  std_logic:='0';
	SIGNAL txout1 : std_logic;

	signal data : integer;
	signal data_received : std_logic_vector(7 downto 0);

BEGIN

	uut: fpga PORT MAP(
		rst => rst,
		clk_speed => clk_speed,
		clk_ref => clk_ref,
		AEN => AEN,
		IOR => IOR,
		IOW => IOW,
		bus_adr => bus_adr,
		bus_data => bus_data,
		irq => irq,
		irqrxFIFO => irqrxFIFO ,
		irqrxRX => irqrxRX,
		irqrxERR => irqrxERR ,
		irqtx => irqtx ,
		rxin1 => rxin1,
		txout1 => txout1 
	);


-- master clock
clk_speed <= (Not clk_speed) after (CK_PERIOD/2); 
-- Reset
rst   <= '1','0' after (100 ns);

-- baudrate/(16*2) used to generate half clock cycle;
clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz

-- feeding back output from transmitter to the input of receiver
rxin1 <= txout1;


check:process
   -- procedure declaration
   -- declared in process due to assignment to read
   -- this procedure reads out data from the receiver
   -- timing can be modified to model any CPU read cycle
   PROCEDURE read_bus(address : in integer) IS
		variable adr : std_logic_vector(23 downto 0);
      BEGIN
			adr:=conv_std_logic_vector(address,24);
			bus_data<="ZZZZZZZZ";
			AEN<='0';
         WAIT FOR 20 ns;
			bus_adr<=adr;
         WAIT FOR 20 ns;
			IOR<='0';
         WAIT FOR 60 ns;
         data_received <= bus_data;
			IOR<='1';
         WAIT FOR 20 ns;
			AEN<='1';
         WAIT FOR 20 ns;
   END read_bus;

   PROCEDURE write_bus(address : IN integer) IS
		variable adr : std_logic_vector(23 downto 0);
		variable dat : std_logic_vector(7 downto 0);
      BEGIN
--			adr:=conv_std_logic_vector(address,24);
--			dat:=conv_std_logic_vector(data,8);
			AEN<='0';
         WAIT FOR 20 ns;
			bus_adr<=conv_std_logic_vector(address,24);
			bus_data <= conv_std_logic_vector(data,8);
         WAIT FOR 20 ns;
			IOW<='0';
         WAIT FOR 60 ns;
			IOW<='1';
         WAIT FOR 20 ns;
			bus_data <= "ZZZZZZZZ";
			AEN<='1';
         WAIT FOR 20 ns;
   END write_bus;


-- RX
-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 )


-- TX
-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
-- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 )

	begin

-- RX
-- data : 257
-- config : 258
-- flag : 259
-- TX
-- data : 260
-- config : 261
-- flag : 262

	wait for 500 ns;

-- configuration du RX (RX_config)
		data<=255;
		write_bus(258);
		read_bus(258);
	wait for 100 ns;

-- configuration du TX
		data<=119;
		write_bus(261);
		read_bus(261);
	wait for 5 us;

-- transmission par le TX
		data<=177;
		write_bus(260);
		read_bus(260);

	wait for 100 ns;


-- transmission par le TX
		data<=22;
		write_bus(260);
		read_bus(260);


	wait for 100 ns;
	wait for 100 ns;

end process;
END behavior;