-- reg_8.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- Registre 8 bits. library IEEE; use IEEE.STD_LOGIC_1164.all; entity reg_8 is port ( rst : in std_logic; clk : in std_logic; en : in std_logic; -- enable input : in std_logic_vector (7 downto 0); output : out std_logic_vector (7 downto 0) ); end reg_8; architecture RTL of reg_8 is begin process (rst, clk) begin if (rst ='1') then output <= x"00"; elsif (clk'event and clk = '1') then if (en='1') then output <= input; end if; end if; end process; end RTL;