-- bch_reg_8.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- test bench du registre 8 bits library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; use work.nono_const.all; entity bch_reg_8 is end bch_reg_8; architecture sim_1 of bch_reg_8 is component reg_8 port( rst : in std_logic; clk : in std_logic; en : in std_logic; -- enable input : in std_logic_vector (7 downto 0); output : out std_logic_vector (7 downto 0) ); end component; signal rst : std_logic; signal clk : std_logic := '0'; signal en : std_logic := '0'; signal input : std_logic_vector (7 downto 0); signal output : std_logic_vector (7 downto 0); begin U0 : reg_8 port map (rst => rst, clk => clk, en => en, input => input, output => output); rst <= '1', '0' after (CK_PERIOD/5); clk <= not clk after CK_PERIOD/2; en <= '0', '1' after (CK_PERIOD*1), '0' after (CK_PERIOD*3), '1' after (CK_PERIOD*5), '0' after (CK_PERIOD*7); input <= x"00", x"05" after (CK_PERIOD/2), x"01" after (CK_PERIOD*3); end sim_1; --configuration configuration cf_bch_reg_8 of bch_reg_8 is for sim_1 for U0 : reg_8 use entity work.reg_8(RTL); end for; end for; end cf_bch_reg_8;