--test bench du compteur sur value pour duree du niveau haut test à faire sur 59ms environ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library synopsys; use synopsys.bv_arithmetic.all; --ENTITY entity tb_clk1us is end tb_clk1us; --ARCHITECTURE architecture sim1 of tb_clk1us is component clk1us port( rst : in std_logic; clk : in std_logic; --inc : buffer integer; clk1usout : out std_logic ); end component; -- declaration des signaux signal rst:std_logic; signal clk:std_logic:='0'; --signal inc : integer; signal clk1usout : std_logic; --declaration de constantes constant CLK_PERIOD :time := 32 ns ; --31,25ns normalememt begin U1clk1us: clk1us port map ( rst=>rst, clk=>clk, -- inc=>inc, clk1usout=>clk1usout ); --STIMULI clk<= not clk after (CLK_PERIOD/2); rst<='1','0' after (CLK_PERIOD/4); end sim1; --CONFIGURATION configuration cfg_tb_clk1us of tb_clk1us is for sim1 for all : clk1us use entity work.clk1us(clk1usbehav); end for; end for; end cfg_tb_clk1us;