-- pwm_nono.vhd -- Eurobot 2004 : APB Team -- Auteur : Fidèle GAFAN et Pierre-andré Galmes -- Bloc de génération de pwm. library IEEE; use IEEE.std_logic_1164.all; use work.nono_const.all; use work.isa_const.all; use work.pwm_const.all; -- ENTITY entity pwm_nono is port( rst : in std_logic; clk : in std_logic; rw : in std_logic; cs : in std_logic; bus_data : inout T_DATA; outpwm : out std_logic ); end pwm_nono; -- ARCHITECTURE architecture RTL of pwm_nono is -- Registre. component reg_rw is port ( clk : in std_logic; rst : in std_logic; rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) enable : in std_logic; data : inout T_DATA; data_out : out T_DATA -- data courant ); end component; -- Générateur d'horloge à 1us. component clk200ns is port( RST : in std_logic; CLK : in std_logic; --40MHz CLK1USOUT : out std_logic ); end component; -- Convertisseur [0-255] vers un temps. component convert_pwm is port( data_in : in T_OCTET; data_out : out T_DOUBLE_OCTET --duree pdt laql la sortie ); end component; -- Générateur de pwm. component pwm_generator is port ( rst : in std_logic; clk : in std_logic; pwm_in : in T_DOUBLE_OCTET; pwm_out : out std_logic ); end component; -- Declaration des signaux locaux signal clkdiv : std_logic; signal reg_out : T_OCTET; signal convert_out : T_DOUBLE_OCTET; begin -- Mapping DES SIGNAUX. -- registre : reg_rw port map( clk, rst, rw, cs, bus_data, reg_out ); -- Clock_div : clk200ns port map( rst, clk, clkdiv ); -- convert_nono : convert_pwm port map( reg_out, convert_out ); -- pwm_gene : pwm_generator port map( rst, clkdiv, convert_out, outpwm ); end RTL;