LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; LIBRARY work; USE work.all; --LIBRARY simprim; --USE simprim.vcomponents.all; --USE simprim.vpackage.all; ENTITY TestBench IS END TestBench; ARCHITECTURE HTWTestBench OF TestBench IS COMPONENT uart PORT ( mclkx16 : IN std_logic; read : IN std_logic; write : IN std_logic; reset : IN std_logic; data : INOUT std_logic_vector(7 downto 0); -- receiver input signal, error, and status flags rx : IN std_logic; rxrdy : OUT std_logic; parity_err : OUT std_logic; framing_err : OUT std_logic; overrun : OUT std_logic; -- transmitter output signal and status flag tx : OUT std_logic; txrdy : OUT std_logic ); END COMPONENT; SIGNAL mclkx16 : std_logic := '1'; -- initialized to 1 SIGNAL read : std_logic := '1'; -- de-assert read initially SIGNAL write : std_logic := '1'; -- de-assert write initially SIGNAL reset : std_logic := '1'; -- initialized to 1 SIGNAL data_int : std_logic_vector(7 downto 0); -- receiver input signal, error, and status flags SIGNAL rx : std_logic; SIGNAL rxrdy : std_logic; SIGNAL parity_err : std_logic; SIGNAL framing_err : std_logic; SIGNAL overrun : std_logic; -- transmitter output signal and status flag SIGNAL tx : std_logic; SIGNAL txrdy : std_logic; -- storage of data SIGNAL data_written : std_logic_vector(7 downto 0); SIGNAL data_received : std_logic_vector(7 downto 0); CONSTANT baudrate : time := 500 ns; -- specify the baudrate for the simulation BEGIN -- instantiate UART top level entity into test bench U1 : uart port map ( mclkx16 => mclkx16, read => read, write => write, reset => reset, data => data_int, rx => rx, rxrdy => rxrdy, parity_err => parity_err, framing_err => framing_err, overrun => overrun, tx => tx, txrdy => txrdy ); ------------------------------------------------------------------------------- -- Begin test bench -- ------------------------------------------------------------------------------- -- generate 16 times baudrate clock frequency -- (mclkx16 = baudrate/16) -- baudrate/(16*2) used to generate half clock cycle; mclkx16 <= (Not mclkx16) after (baudrate/(16*2)); -- Reset Uart reset <= '0' after 2000 ns; -- feeding back output from transmitter to the input of receiver rx <= tx after 1 ns; -- core test program self_check : PROCESS -- procedure declaration -- declared in process due to assignment to write. -- this procedure writes data to the transmitter -- timing can be modified to model any CPU write cycle PROCEDURE write_to_transmitter (data : IN integer) IS VARIABLE din : std_logic_vector(7 downto 0); BEGIN din := conv_std_logic_vector(data,8); write <= '0'; WAIT FOR 100 ns; data_int <= din; WAIT FOR 50 ns; write <= '1'; data_written <= din; WAIT FOR 20 ns; END write_to_transmitter; -- procedure declaration -- declared in process due to assignment to read -- this procedure reads out data from the receiver -- timing can be modified to model any CPU read cycle PROCEDURE read_out_receiver (data_in : IN std_logic_vector(7 downto 0)) IS BEGIN read <= '0'; WAIT FOR 25 ns; data_received <= data_in; WAIT FOR 75 ns; read <= '1'; END read_out_receiver; -- this procedure compares the data sent and received, -- and flags for any error it encounters. -- Comparison is done just prior to next data transmission, -- and after previous received data has been read out. PROCEDURE compare_data (dataw, datar : IN std_logic_vector(7 downto 0)) IS VARIABLE data_wr, data_rv : integer range 0 to 255; BEGIN data_wr := conv_integer(dataw); data_rv := conv_integer(datar); ASSERT (data_wr = data_rv) REPORT "Simulation FAILED!! data_written = "& integer'image(data_wr) & " ===> data_received = "& integer'image(data_rv) SEVERITY FAILURE; END compare_data ; BEGIN WAIT UNTIL mclkx16'EVENT and mclkx16 = '1'; IF reset = '0' THEN FOR i IN 0 TO 255 LOOP -- start test loop; write_to_transmitter(i); -- write_to_transmitter procedure call; WAIT UNTIL (rxrdy = '1'); -- wait for rxrdy; read_out_receiver(data_int); -- read_out_receiver procedure call; compare_data(data_written, data_received); -- compare_data procedure call; END LOOP; REPORT "Simulation OK! Passed all possible combinations successfully!" SEVERITY NOTE; REPORT " Simulation OK! Passed all possible combinations successfully! " SEVERITY WARNING; END IF; END PROCESS; END HTWTestBench; -- Configuration simulation configuration TestBench1 of TestBench is for HTWTestBench for U1: UART use entity work.uart(TOP); end for; end for; end TestBench1;