-- txserie.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre Prot -- ------------------------------------------- -- Port série TX pour le fpga robot -- ------------------------------------------- -- -- * Prend 3 adresses mémoire : -- 0 - Txdata -- 1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0) -- 2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) -- * Mettre le bit On/Off à 1 pour activer la transmission -- * Chaque écriture dans txdata charge la donnée dans la fifo -- * Dès que le registre à décalage est vide, il enlève le dernier élément de -- la fifo et le transmet -- * Deux bits de stop -- * Quand la fifo est pleine, met le flag Full/Int à 1 et génère une -- interruption. Il faut alors mettre à 0 le bit IntEn, qui sera remis à 1 à -- la prochaine écriture dans la fifo -- * On peut lire l'état de la pile dans le registre de flags -- * On peut vider la pile en mettant Purge à 1 -- * Baudrate disponible : -- BdR1/0 ! Baudrate -- 00 ! 9600 -- 01 ! 19200 -- 10 ! 57600 -- 11 ! 115200 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; entity txserie is port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; masterck: in std_logic; txout: out std_logic; minIRQ: out std_logic csData : in std_logic; csConfig : in std_logic; csFlag : in std_logic; ); end txserie; architecture rtl of txserie is component regIO port( cs: in std_logic; bus_data: inout T_DATA; input: in T_DATA; output: out T_DATA; rw: in std_logic; load: in std_logic; ck: in std_logic; rst: in std_logic ); end component; component fifo is port( data_in: in T_DATA; data_out: out T_DATA; ck: in std_logic; ck_in: in std_logic; ck_out: in std_logic; flags: out std_logic_vector(5 downto 0); purge: in std_logic ); end component; entity TXMIT is port ( MCLKX16 : in std_logic; WRITE : in std_logic; RESET : in std_logic; DATA : in std_logic_vector(7 downto 0); TX : out std_logic; TXRDY : out std_logic ); end TXMIT; component clockgene port( ckin: in std_logic; ckout: out std_logic; param: in std_logic_vector(1 downto 0) ); end component; component decoder generic(adr : T_ADDRESS); port( bus_address: in T_DATA; cs: out std_logic ); end component; signal fifoEmpty: std_logic; signal fifoFull: std_logic; signal fifoLI1: std_logic; signal fifoLI0: std_logic; --signal BdR1: std_logic; --signal BdR0: std_logic; signal fifopurge: std_logic:='0'; signal fifoflags: std_logic_vector(5 downto 0); signal fifockin: std_logic; signal fifockout: std_logic; signal txck: std_logic; signal confreg: T_DATA; signal flagreg: T_DATA:="00000000"; signal inter_data: T_DATA; signal txready: std_logic:='1'; begin FIFO1: fifo port map( data_in=>bus_data, data_out=>inter_data, ck_in=>fifockin, ck_out=>fifockout, purge=>fifopurge ); fifockin<=csData and clk and not rw; fifockout<=txready and not fifoempty fifopurge<=confreg(3) or rst; flagreg(0)<=fifoLI1; flagreg(1)<=fifoLI0; flagreg(2)<=fifoAFull; flagreg(3)<=fifoAEmpty; flagreg(4)<=fifoFull; flagreg(5)<=fifoEmpty; minirq<=fifoAFull and confreg(2) --fifo almost full AND Int/En TX1 : TXMIT port map( MCLKX16=>txck, WRITE=>'1', RESET => rst, DATA inter_data, TX => txout, TXRDY => txready ); end TXMIT; geneck<=confreg(4) and masterck; -- On/Off et masterck CLOCK1 : clockgene port map( ckin=geneck, ckout=>txck, param=>confreg(1 downto 0) ); -- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) RCONF : regIO generic map(adr=>A_CONFIG) port map( bus_address=>bus_address, bus_data=>bus_data, input=>(others => '0'), output=>confreg, rw=>rw, load=>'0', ck=>clk, rst=>rst ); -- Flag : (x ! x ! Empty ! Full/Int ! FLI3 ! FLI2 ! FLI1 ! FLI0) RFLAG : regIO generic map(adr=>A_FLAG) port map( bus_address=>bus_address, bus_data=>bus_data, input=>flagreg, output=>open, rw=>rw, load=>'1', ck=>clk, rst=>rst ); end rtl;