JDF G // Created by Project Navigator ver 1.0 PROJECT rxserie DESIGN rxserie DEVFAM spartan2 DEVFAMTIME 0 DEVICE xc2s200 DEVICETIME 0 DEVPKG pq208 DEVPKGTIME 0 DEVSPEED -6 DEVSPEEDTIME 0 DEVTOPLEVELMODULETYPE HDL TOPLEVELMODULETYPETIME 0 DEVSYNTHESISTOOL XST (VHDL/Verilog) SYNTHESISTOOLTIME 0 DEVSIMULATOR Modelsim SIMULATORTIME 0 DEVGENERATEDSIMULATIONMODEL VHDL GENERATEDSIMULATIONMODELTIME 0 SOURCE rxserie.vhd SOURCE ..\uart\rxcver.vhd STIMULUS ..\fifo\bch_sfifo.vhd SOURCE ..\fifo\fifodriver.vhd STIMULUS ..\fifo\bch_fifodriver.vhd SOURCE ..\clockgene\clockgene.vhd SOURCE ..\..\registre\registre.vhd SOURCE sfifo.xco STIMULUS bch_rxserie.vhd SOURCE ..\..\modele\nono_const.vhd SOURCE ..\..\modele\isa_const.vhd [Normal] p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1079088462, ModelSim SE [STATUS-ALL] rxserie.ngcFile=WARNINGS,1079226990 rxserie.ngdFile=WARNINGS,1079300826 [STRATEGY-LIST] Normal=True