-- TestBench Template LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; use work.nono_const.all; use work.isa_const.all; ENTITY bch_rxserie IS END bch_rxserie; ARCHITECTURE behavior OF bch_rxserie IS -- Component Declaration COMPONENT rxserie PORT( rst : in std_logic; bus_clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; clk: in std_logic; clk_ref: in std_logic; rxin: in std_logic; irqFIFO: out std_logic; irqRX: out std_logic; irqERR: out std_logic; csData : in std_logic; csConfig : in std_logic; csFlag : in std_logic); END COMPONENT; signal rst: std_logic; signal bus_clk: std_logic; signal rw: std_logic; signal bus_data: T_DATA; signal data_received: T_DATA; signal clk: std_logic:='0'; signal clk_ref: std_logic:='0'; signal rxin: std_logic:='1'; signal irqFIFO: std_logic; signal irqRX: std_logic; signal irqERR: std_logic; signal csData: std_logic; signal csConfig: std_logic; signal csFlag: std_logic; BEGIN uut: rxserie PORT MAP( rst => rst, bus_clk => bus_clk, rw => rw, bus_data => bus_data, clk => clk, clk_ref => clk_ref, rxin => rxin, irqFIFO => irqFIFO, irqRX => irqRX, irqERR => irqERR, csData => csData, csConfig => csConfig, csFlag => csFlag ); -- master clock clk <= (Not clk) after (CK_PERIOD/2); -- Reset Uart rst <= '1','0' after (10*CK_PERIOD); -- baudrate/(16*2) used to generate half clock cycle; clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz -- feeding back output from transmitter to the input of receiver rxin <= not rxin after 15751 ns; check:process -- procedure declaration -- declared in process due to assignment to read -- this procedure reads out data from the receiver -- timing can be modified to model any CPU read cycle PROCEDURE read_bus IS BEGIN rw <= '1'; bus_data<="ZZZZZZZZ"; WAIT FOR (ISA_CK_PERIOD/2); bus_clk<='1'; WAIT FOR (ISA_CK_PERIOD/2); data_received <= bus_data; WAIT FOR 1 ns; bus_clk<='0'; csFlag<='0'; csConfig<='0'; csData<='0'; WAIT FOR 25 ns; END read_bus; PROCEDURE write_bus(data : IN std_logic_vector(7 downto 0)) IS --VARIABLE din : std_logic_vector(7 downto 0); BEGIN --din := conv_std_logic_vector(data,8); rw <= '0'; bus_data <= data; WAIT FOR (ISA_CK_PERIOD/2); bus_clk <= '1'; WAIT FOR (ISA_CK_PERIOD/2); bus_clk <= '0'; csFlag<='0'; csConfig<='0'; csData<='0'; bus_data <= (others => 'Z'); WAIT FOR 25 ns; END write_bus; begin csConfig<='1'; write_bus("00111111"); --(115200, toutes interruptions ok, On) WAIT FOR 10 us; csData<='1'; read_bus; WAIT FOR 100 us; csFlag<='1'; read_bus; WAIT FOR 100 us; end process; END;