-- txserie.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre Prot -- ------------------------------------------- -- Port série TX pour le fpga robot -- ------------------------------------------- -- -- * Prend 3 adresses mémoire : -- 0 - Txdata -- 1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0) -- 2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) -- * Mettre le bit On/Off à 1 pour activer la transmission -- * Chaque écriture dans txdata charge la donnée dans la fifo -- * Dès que le registre à décalage est vide, il enlève le dernier élément de -- la fifo et le transmet -- * Deux bits de stop -- * Quand la fifo est pleine, met le flag Full/Int à 1 et génère une -- interruption. Il faut alors mettre à 0 le bit IntEn, qui sera remis à 1 à -- la prochaine écriture dans la fifo -- * On peut lire l'état de la pile dans le registre de flags -- * On peut vider la pile en mettant Purge à 1 -- * Baudrate disponible : -- BdR1/0 ! Baudrate -- 00 ! 9600 -- 01 ! 19200 -- 10 ! 57600 -- 11 ! 115200 -- librairies library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; use work.nono_const.all; -- **** entité **** entity txserie is port ( rst : in std_logic; bus_clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA:=(others => 'Z'); clk: in std_logic; clk_ref: in std_logic; txout: out std_logic; minIRQ: out std_logic; csData : in std_logic; csConfig : in std_logic; csFlag : in std_logic ); end txserie; -- **** architecture RTL **** architecture rtl of txserie is -- composants component clockgene port( rst: in std_logic; ckin: in std_logic; ckout: out std_logic; param: in std_logic_vector(1 downto 0) ); end component; component regIO port( cs: in std_logic; bus_data: inout T_DATA; input: in T_DATA; output: out T_DATA; rw: in std_logic; load: in std_logic; ck: in std_logic; rst: in std_logic); end component; component fifodriver port( clk: in std_logic; rst: in std_logic; readreq: in std_logic; writereq: in std_logic; din: IN std_logic_VECTOR(7 downto 0); dout: OUT std_logic_VECTOR(7 downto 0); dready: out std_logic; full: OUT std_logic; empty: OUT std_logic; data_count: OUT std_logic_VECTOR(1 downto 0)); END COMPONENT; component TXMIT port ( MCLKX16 : in std_logic; WRITE : in std_logic; RESET : in std_logic; DATA : in std_logic_vector(7 downto 0); TX : out std_logic; TXRDY : out std_logic); end component; -- signaux signal fifoEmpty: std_logic; signal fifoFull: std_logic; signal fifoLevel: std_logic_vector(1 downto 0); signal fifopurge: std_logic:='0'; signal fifockin: std_logic; signal fifockout: std_logic; signal txck: std_logic; signal geneck:std_logic; signal txload: std_logic:='0'; signal confreg: T_DATA:="00000000"; signal flagreg: T_DATA:="00000000"; signal inter_data: T_DATA; --signal inter_fifo_bus: T_DATA; signal txready: std_logic:='1'; signal fifodready :std_logic; --signal state:integer:=1; --signal state_next:integer:=1; signal state_txload:integer:=0; signal dummy : T_DATA :=(others =>'0'); signal un: std_logic :='1'; -- description de l'architecture begin CLOCK1 : clockgene port map( rst => rst, ckin=>clk_ref,--geneck, ckout=>txck, param=>confreg(1 downto 0)); FIFO1: fifodriver port map( clk => clk, rst => fifopurge, readreq => fifockout, writereq => fifockin, din => bus_data, dout => inter_data, dready => fifodready, full => fifoFull, empty => fifoEmpty, data_count => fifoLevel(1 downto 0)); TX1 : TXMIT port map( MCLKX16 => txck, WRITE => txload, RESET => rst, DATA => inter_data, TX => txout, TXRDY => txready); -- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) RCONF : regIO port map( cs=>csConfig, bus_data=>bus_data, input=>dummy, output=>confreg, rw=>rw, load=>dummy(0), ck=>bus_clk, rst=>rst); -- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) -- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 ) RFLAG : regIO port map( cs=>csFlag, bus_data=>bus_data, input=>flagreg, output=>open, rw=>rw, load=>un, ck=>bus_clk, rst=>rst); -- signaux -- config geneck <= (clk_ref);-- and confreg(4); -- On/Off et masterck fifopurge <= '1' when (rst='1') else confreg(3); -- reset or purge -- flags flagreg(1 downto 0)<=fifoLevel(1 downto 0); flagreg(2)<=fifoFull; flagreg(3)<=fifoEmpty; -- irq minirq<=fifoFull and confreg(2); --fifo full AND Int/En -- controle des flux fifockin <= (csData and not bus_clk and not rw and not rst); fifockout <= (txready and not fifoEmpty); process(fifodready,txready,rst) begin if(rst='1') then state_txload<= 0; else txload <= '0'; case state_txload is when 0 => if(txready='1') then state_txload <= 3; elsif(fifodready='1') then state_txload <= 1; else state_txload <= 0; end if; when 1 => if(txready='1') then state_txload <= 2; txload <= '1'; else state_txload <= 1; end if; when 2 => if(txready='0') then state_txload <= 0; else txload <= '1'; state_txload <= 2; end if; when 3 => if(fifodready='1') then state_txload <= 2; txload <= '1'; else state_txload <= 3; end if; when others => state_txload <= 0; end case; end if; end process; end rtl;