JDF G // Created by Project Navigator ver 1.0 PROJECT txserie DESIGN portserie DEVFAM spartan2 DEVFAMTIME 0 DEVICE xc2s200 DEVICETIME 1078190070 DEVPKG pq208 DEVPKGTIME 0 DEVSPEED -6 DEVSPEEDTIME 0 DEVTOPLEVELMODULETYPE HDL TOPLEVELMODULETYPETIME 0 DEVSYNTHESISTOOL XST (VHDL/Verilog) SYNTHESISTOOLTIME 0 DEVSIMULATOR Modelsim SIMULATORTIME 0 DEVGENERATEDSIMULATIONMODEL VHDL GENERATEDSIMULATIONMODELTIME 0 SOURCE txserie.vhd STIMULUS bch_txserie.vhd SOURCE txmit.vhd SOURCE ..\..\modele\nono_const.vhd SOURCE ..\..\modele\isa_const.vhd SOURCE ..\..\registre\registre.vhd SOURCE ..\..\..\..\..\..\xilinx\vhdl\src\unisims\unisim_VCOMP.vhd SOURCE ..\fifo\fifodriver.vhd SOURCE ..\fifo\sfifo.xco STIMULUS bch_txmit.vhd STIMULUS ..\fifo\bch_fifodriver.vhd SOURCE ..\clockgene\clockgene.vhd STIMULUS bch_clockgene.vhd [Normal] p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079779592, D:\xilinx\vhdl\src p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078871494, ModelSim SE [STRATEGY-LIST] Normal=True