-- fifodriver.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre Prot library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; -- pilote de fifo entity fifodriver is port( masterck,reset: in std_logic; readreq,writereq: in std_logic; fifock:out std_logic; fiforead:out std_logic; fifowrite:out std_logic ); constant PRESCAL :integer:= 1; end fifodriver; architecture rtl of fifodriver is signal subck: integer :=0; signal state_actual,state_next : integer; begin -- la partie COMBI COMBI:process(state_actual,readreq,writereq) begin fifowrite <= '0'; fiforead <= '0'; fifock <= '0'; state_next <= 1; case state_actual is when 1 => if (readreq='1') then state_next <= 2; elsif(writereq='1') then state_next <= 4; end if; when 2 => state_next <= 3; fiforead<='1'; when 3 => state_next <= 1; fiforead<='1'; fifock<='1'; when 4 => state_next <= 5; fifowrite<='1'; when 5 => state_next <= 1; fifowrite<='1'; fifock<='1'; when others => NULL; end case; end process COMBI; -- la partie SEQU SEQU:process(masterck,reset) begin if (reset='1') then state_actual <= 1; elsif (masterck'event and masterck='1') then if(subck=PRESCAL) then subck<=0; state_actual <= state_next ; else subck<=subck+1; end if; end if; end process SEQU; end rtl;