-- fifodriver.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre Prot library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; -- pilote de fifo entity fifodriver is port( masterck,reset: in std_logic; readreq,writereq: in std_logic; fifock:out std_logic; fiforead:out std_logic; fifowrite:out std_logic ); constant PRESCAL :integer:= 1; end fifodriver; -- arch architecture rtl of fifodriver is signal clock:std_logic; signal writeflag,readflag :std_logic; signal subck : integer :=0; begin fifock<=clock; -- process(writereq) -- begin -- if (writereq'event and writereq='1') then -- writeflag<='1'; -- end if; -- end process; -- -- process(readreq) -- begin -- if (readreq'event and readreq='1') then -- readflag<='1'; -- end if; -- end process; process(clock,writereq,readreq) begin if (writereq'event and writereq='1') then writeflag<='1'; end if; if (readreq'event and readreq='1') then readflag<='1'; end if; -- sur front descendant de fifock, on met fifowrite et fiforead à -- jour if(clock'event and clock='0') then if(readflag='1') then readflag<='0'; fiforead<='1'; end if; if(writeflag='1') then writeflag<='0'; fifowrite<='1'; end if; end if; end process; -- la partie SEQU : divise la fréquence d'horloge SEQU:process(masterck) begin if (masterck'event and masterck='1') then if(subck=PRESCAL) then subck<=0; clock<='1'; else subck<=subck+1; clock<='0'; end if; end if; end process SEQU; end rtl;