-- TestBench Template LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY bch_sfifo IS END bch_sfifo; ARCHITECTURE behavior OF bch_sfifo IS -- Component Declaration component sfifo port ( clk: IN std_logic; sinit: IN std_logic; din: IN std_logic_VECTOR(7 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(7 downto 0); full: OUT std_logic; empty: OUT std_logic; rd_ack: OUT std_logic; wr_ack: OUT std_logic; rd_err: OUT std_logic; wr_err: OUT std_logic; data_count: OUT std_logic_VECTOR(1 downto 0)); end component; signal din: std_logic_VECTOR(7 downto 0):="01010101"; signal wr_en: std_logic:='1'; signal clk: std_logic:='0'; signal rd_en: std_logic:='1'; signal sinit: std_logic:='1'; signal dout: std_logic_VECTOR(7 downto 0); signal full: std_logic; signal empty: std_logic; signal data_count: std_logic_VECTOR(1 downto 0); signal rd_ack: std_logic; signal rd_err: std_logic; signal wr_ack: std_logic; signal wr_err: std_logic; BEGIN -- Component Instantiation uut : sfifo port map ( clk => clk, sinit => sinit, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty, rd_ack => rd_ack, wr_ack => wr_ack, rd_err => rd_err, wr_err => wr_err, data_count => data_count); din <= std_logic_vector(unsigned(din) + 1) after 8 ns; sinit <= '1' , '0' after 10 ns; clk <= not clk after 3 ns; rd_en <= '0' , '1' after 50 ns; END behavior;