-- TestBench Template LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS -- Component Declaration component afifo port ( din: IN std_logic_VECTOR(7 downto 0); wr_en: IN std_logic; wr_clk: IN std_logic; rd_en: IN std_logic; rd_clk: IN std_logic; ainit: IN std_logic; dout: OUT std_logic_VECTOR(7 downto 0); full: OUT std_logic; empty: OUT std_logic; almost_full: OUT std_logic; almost_empty: OUT std_logic; wr_count: OUT std_logic_VECTOR(1 downto 0); rd_count: OUT std_logic_VECTOR(1 downto 0); rd_ack: OUT std_logic; rd_err: OUT std_logic; wr_ack: OUT std_logic; wr_err: OUT std_logic); end component; signal din: std_logic_VECTOR(7 downto 0):="01010101"; signal wr_en: std_logic:='1'; signal wr_clk: std_logic:='0'; signal rd_en: std_logic:='1'; signal rd_clk: std_logic:='0'; signal ainit: std_logic:='1'; signal dout: std_logic_VECTOR(7 downto 0); signal full: std_logic; signal empty: std_logic; signal almost_full: std_logic; signal almost_empty: std_logic; signal wr_count: std_logic_VECTOR(1 downto 0); signal rd_count: std_logic_VECTOR(1 downto 0); signal rd_ack: std_logic; signal rd_err: std_logic; signal wr_ack: std_logic; signal wr_err: std_logic; BEGIN -- Component Instantiation U0 : afifo port map ( din => din, wr_en => wr_en, wr_clk => wr_clk, rd_en => rd_en, rd_clk => rd_clk, ainit => ainit, dout => dout, full => full, empty => empty, almost_full => almost_full, almost_empty => almost_empty, wr_count => wr_count, rd_count => rd_count, rd_ack => rd_ack, rd_err => rd_err, wr_ack => wr_ack, wr_err => wr_err); din <= std_logic_vector(unsigned(din) + 1) after 5 ns; ainit <= '1' , '0' after 10 ns; rd_clk <= not rd_clk after 2 ns; wr_clk <= not wr_clk after 3 ns; rd_en <= '0' , '1' after 50 ns; END;