-- modele.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- Fichier modèle pour la déclaration de module. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; entity bch_txserie is end bch_txserie; architecture sim1 of bch_txserie is component txserie generic ( -- adresses des différents registres du module. A_DATA : T_ADDRESS ; A_CONFIG : T_ADDRESS ; A_FLAG : T_ADDRESS -- si autre choses à déclarer... ); port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; bus_address : in T_ADDRESS; masterck: in std_logic; txout: out std_logic; minIRQ: out std_logic ); end component; -- définiton des signaux signal rst : std_logic; signal clk : std_logic := '0'; signal simclk : std_logic := '0'; signal rw : std_logic; -- read / write signal bus_data : T_DATA:="00000000"; signal bus_address : T_ADDRESS; signal masterck: std_logic:='0'; signal txout: std_logic; signal minIRQ: std_logic; signal state_next:integer:=0; begin U1 : txserie generic map ( -- Définition des addresses. A_DATA => "0000000001", A_CONFIG => "0000000010", A_FLAG => "0000000011" ) port map ( rst => rst, clk => clk, rw => rw, bus_data => bus_data, bus_address => bus_address, masterck=> masterck, txout=> txout, minIRQ=> minIRQ ); masterck<= not masterck after (CK_PERIOD/11); simclk<= not simclk after (CK_PERIOD/2); process(simclk) begin if(simclk'event and simclk='1') then state_next<=(state_next + 1); end if; end process; process(state_next) begin bus_address<="0000000000"; clk<='0'; rst<='0'; bus_data<=(others =>'Z'); case state_next is when 1 => bus_address<="0000000010"; bus_data<="00010111"; rw<='0'; when 2 => bus_address<="0000000010"; bus_data<="00010111"; rw<='0'; clk<='1'; when 3 => null; when 4 => bus_address<="0000000001"; bus_data<="00010111"; rw<='0'; when 5 => bus_address<="0000000001"; bus_data<="00010111"; rw<='0'; clk<='1'; when 6 => null; when 7 => bus_address<="0000000011"; rw<='1'; when 8 => bus_address<="0000000011"; rw<='1'; clk<='1'; when 9 => null; when 10 => bus_address<="0000000010"; rw<='1'; when 11 => bus_address<="0000000010"; rw<='1'; clk<='1'; when 12 => null; when others => null; end case; end process; end sim1; configuration cf1_bch_txserie of bch_txserie is for sim1 for all : txserie use entity work.txserie(rtl); end for; end for; end cf1_bch_txserie;