-- modele.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- Fichier modèle pour la déclaration de module. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; entity modele is port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; -- chaque registre se voit administrer un chip select. cs_reg0 : in std_logic; -- chip select cs_reg1 : in std_logic; cs_reg2 : in std_logic ); end entity; architecture test_modele of modele is begin process (rst, clk) begin if (rst = '1') then bus_data <= x"00"; elsif (clk'event and clk = '1') then if (cs_reg0 = '1') then bus_data <= x"01"; else if (cs_reg1 = '1') then bus_data <= x"02"; elsif (cs_reg2 = '1') then bus_data <= x"03"; end if; end if; end if; end process; end test_modele;