-- modele.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- Fichier modèle pour la déclaration de module. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; entity bch_modele is end bch_modele; architecture sim1 of bch_modele is component modele generic ( -- adresses des différents registres du module. A_REG1 : T_ADDRESS; A_REG2 : T_ADDRESS; A_REG3 : T_ADDRESS -- si autre choses à déclarer... ); port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read / write bus_data : inout T_DATA; bus_address : in T_ADDRESS ); end component; -- définiton des signaux signal rst : std_logic; signal clk : std_logic := '0'; signal rw : std_logic; -- read / write signal bus_data : T_DATA; signal bus_address : T_ADDRESS; begin U1 : modele generic map ( -- Définition des addresses. A_REG1 => A_IO1_REG_DIRECTION, A_REG2 => A_IO1_REG_DATA, A_REG3 => A_IO1_REG_INTERRUPT_MASK ) port map ( rst => rst, clk => clk, rw => rw, bus_data => bus_data, bus_address => bus_address ); rst <= '1', '0' after CK_PERIOD; clk <= not clk after (CK_PERIOD/2); rw <= '0'; bus_address <= A_IO1_REG_DIRECTION, A_IO1_REG_DATA after 3*CK_PERIOD, A_IO1_REG_INTERRUPT_MASK after 5*CK_PERIOD; end sim1; configuration cf1_bch_modele of bch_modele is for sim1 for all : modele use entity work.modele(test_modele); end for; end for; end cf1_bch_modele;